阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 高桥正树 于 2020-09-25 设计创作，主要内容包括：本发明提供半导体装置,其抑制半导体芯片的接合导线的表面电极的温度上升。半导体装置(10)包括在正面具备电极区(32a、32b)的半导体芯片(30)、和分别接合于电极区(32a、32b)的多根导线(50)。此时,电极区(32a、32b)的分别与多根导线(50)接合的多个被接合区域(36)配置为俯视时在与半导体芯片(30)的一边平行的X方向上和在与X方向正交的Y方向上各不重复。由此,导线(50)分散地接合于半导体芯片(30)的电极区(32a、32b),从而在电极区(32a、32b)中温度几乎均匀地分布于整体,温度高的区域的不均分布受到抑制。(The invention provides a semiconductor device, which can restrain the temperature rise of the surface electrode of the bonding wire of the semiconductor chip. A semiconductor device (10) includes a semiconductor chip (30) having electrode regions (32a, 32b) on the front surface thereof, and a plurality of wires (50) bonded to the electrode regions (32a, 32b), respectively. In this case, a plurality of bonded regions (36) of the electrode regions (32a, 32b) to which the plurality of wires (50) are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip (30) and in a Y direction orthogonal to the X direction when viewed from above. Thus, the wires (50) are dispersedly bonded to the electrode regions (32a, 32b) of the semiconductor chip (30), so that the temperature is almost uniformly distributed in the entire electrode regions (32a, 32b), and uneven distribution in a region with high temperature is suppressed.)

1. A semiconductor device is characterized by comprising:

a semiconductor chip having a first main electrode on a front surface thereof; and

a plurality of wires respectively coupled to the first main electrodes,

the plurality of bonded regions of the first main electrode bonded to the plurality of wires, respectively, are arranged so as not to overlap each other in a first direction parallel to one side of the semiconductor chip and in a second direction orthogonal to the first direction when viewed from above.

2. The semiconductor device according to claim 1,

the semiconductor chip further includes a second main electrode on a rear surface,

the semiconductor device further includes a conductive plate, and the second main electrode of the semiconductor chip is connected to the conductive plate via a bonding member.

3. The semiconductor device according to claim 1,

the number of the wires is more than 4.

4. The semiconductor device according to claim 1,

the plurality of bonded regions are disposed at positions other than the center portion of the front surface.

5. The semiconductor device according to claim 1,

the bonded regions are disposed at an outer edge portion of the front surface.

6. The semiconductor device according to claim 1,

an even number of the plurality of bonded regions are arranged on the front surface.

7. The semiconductor device according to claim 6,

all the sets of the joined regions in a set of 2 selected from the plurality of joined regions are configured to be point-symmetrical with respect to the center point of the front face.

8. The semiconductor device according to claim 7,

the number of the bonded regions is 4 at the outer edge portion of the front surface.

9. The semiconductor device according to claim 8,

the plurality of bonded regions are configured such that a straight line joining the one group of bonded regions is orthogonal to a straight line joining the other group of bonded regions.

10. The semiconductor device according to claim 7,

the plurality of bonded regions are further configured to be line-symmetric with respect to a straight line passing through the center point of the front surface.

11. The semiconductor device according to claim 1,

the length of one side of the semiconductor chip is 7mm or less.

12. The semiconductor device according to claim 1,

the semiconductor chip includes a diode or a switching element.

13. The semiconductor device according to claim 1,

the semiconductor chip is composed of silicon carbide.

Technical Field

The present invention relates to a semiconductor device.

Background

A semiconductor device includes a semiconductor chip including semiconductor elements such as IGBTs (Insulated Gate Bipolar transistors) and FWDs (Free Wheeling diodes), and is used as a power conversion device by electrically bonding surface electrodes of the semiconductor chip to each other with a metal wire made of aluminum, copper, or the like. At this time, the lead wire for the surface electrode is bonded to the peripheral portion, particularly the corner portion, of the surface electrode as much as possible. This is to avoid the central portion of the surface electrode where the temperature becomes highest when the semiconductor chip is energized, and to avoid the contact between the wires. Further, by increasing the bonding area between the lead and the surface electrode, heat generation per lead can be reduced, and occurrence of breakage due to a difference in thermal stress between the lead and the surface electrode can be suppressed.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2006-066704

Disclosure of Invention

Technical problem

In recent years, the size reduction of semiconductor chips has been progressing. Therefore, the bonding area between the wire and the surface electrode of the semiconductor chip is limited, and the bonding area cannot be increased. Along with this, the amount of heat generated during conduction at the bonding position between the lead and the semiconductor chip also increases. In addition, when the size of the semiconductor chip is reduced, even if the wires are bonded to the corner portions of the surface electrodes, the interval between the wires is reduced, thermal interference occurs between the bonding positions of the wires, and the temperatures of the wires and the surface electrodes of the semiconductor chip increase. The occurrence of damage due to a difference in thermal stress between the wire and the surface electrode may result in a decrease in reliability of a semiconductor device including a semiconductor chip.

The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of suppressing a temperature increase of a surface electrode of a bonding wire of a semiconductor chip.

Technical scheme

According to one aspect of the present invention, there is provided a semiconductor device including: a semiconductor chip having a first main electrode on a front surface thereof; and a plurality of wires each coupled to the first main electrode, wherein a plurality of coupled regions of the first main electrode coupled to the plurality of wires are not overlapped with each other in a first direction parallel to one side of the semiconductor chip and a second direction orthogonal to the first direction when viewed from above.

Technical effects

According to the disclosed technology, it is possible to suppress a temperature increase of a surface electrode of a bonding wire of a semiconductor chip and suppress a decrease in reliability of a semiconductor device.

Drawings

Fig. 1 is a side sectional view of a semiconductor device.

Fig. 2 is a plan view of the semiconductor device.

Fig. 3 is a top view of a semiconductor chip.

Fig. 4 (a) is a diagram for explaining a bonding position between a wire and a semiconductor chip according to the embodiment.

Fig. 5 is a diagram for explaining the surface temperature of the semiconductor chip of the embodiment.

Fig. 6 (a) is a diagram for explaining a bonding position between a lead and a semiconductor chip of a reference example.

Fig. 7 is a graph for explaining the surface temperature of the semiconductor chip of the reference example.

Fig. 8 is a diagram (second drawing) for explaining the bonding position between the wire and the semiconductor chip according to the embodiment.

Fig. 9 is a diagram (second) for explaining a bonding position between a lead and a semiconductor chip of a reference example.

Fig. 10 is a diagram for explaining the bonding position between the lead and the semiconductor chip according to the embodiment (third).

Fig. 11 is a diagram (fourth) for explaining the bonding position of the wire and the semiconductor chip according to the embodiment.

Fig. 12 is a diagram for explaining the bonding position of the wire and the semiconductor chip according to the embodiment (fifth).

Description of the symbols

10 semiconductor device, 20a, 20b ceramic circuit board, 21a, 21b insulating board, 22a 1-22 a3, 22b 1-22 b3 conductive pattern, 23a, 23b metal plate, 30a, 30b, 40a, 40b semiconductor chip, 31 gate, 32 active area, 32a, 32b electrode area, 33 gate runner, 35 bonding area, 36 bonded area, 37 bonding-inhibited area, 50, 55a, 55b wire, 60 heat sink, 70 housing part, 71, 72, 73 wiring part, 71a, 72a, 73a terminal, 74 cover part, 75 packaging part, 80a temperature distribution image

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following description, the "front surface" and the "upper surface" represent surfaces facing upward in the semiconductor device 10 of fig. 1. Similarly, "upper" indicates an upper direction in the semiconductor device 10 of fig. 1. The "back surface" and the "lower surface" represent surfaces facing downward in the semiconductor device 10 of fig. 1. Similarly, "lower" indicates a lower direction in the semiconductor device 10 of fig. 1. The same directivity is shown in other figures as necessary. The terms "front surface", "upper", "back surface", "lower surface" and "side surface" are merely expressions for easily determining relative positional relationships, and do not limit the technical spirit of the present invention. For example, "upper" and "lower" do not necessarily indicate a plumb direction relative to the ground. That is, the directions of "up" and "down" are not limited to the gravity direction.

First, a semiconductor device will be described with reference to fig. 1 and 2. Fig. 1 is a side sectional view of the semiconductor device, and fig. 2 is a plan view of the semiconductor device. Fig. 1 is a cross-sectional view of a portion corresponding to a one-dot chain line α - α in fig. 2. In fig. 2, only the ceramic circuit boards 20a and 20b of the semiconductor device 10 are shown.

As shown in fig. 1, the semiconductor device 10 includes ceramic circuit boards 20a and 20b and a heat sink 60, and the ceramic circuit boards 20a and 20b are provided on the heat sink 60 with solder (not shown) interposed therebetween. As shown in fig. 2, semiconductor chips 30a, 30b, 40a, and 40b are disposed on the ceramic circuit boards 20a and 20 b. The semiconductor device 10 includes a case 70 and a lid 74, the case 70 is provided on the periphery of the heat sink 60 via an adhesive (not shown) so as to surround the ceramic circuit boards 20a and 20b, and the lid 74 is provided on the open upper portion of the case 70. Further, the wiring members 71, 72, 73 are attached to the case portion 70 and the lid portion 74. One end of the wiring member 71 is electrically joined to the ceramic circuit board 20a, and the other end is exposed to the case portion 70 as a terminal 71 a. One end of the wiring member 72 is electrically joined to the ceramic circuit board 20b, and the other end is exposed to the case portion 70 as a terminal 72 a. One end of the wiring member 73 is electrically joined to the ceramic circuit board 20a, and the other end is exposed to the case portion 70 as a terminal 73 a. The ceramic circuit boards 20a and 20b in the case 70 are sealed with a sealing member 75 such as silicone gel or sealing resin.

As shown in fig. 1 and 2, the ceramic circuit boards 20a and 20b include insulating plates 21a and 21b, conductive patterns 22a1 to 22a3 and 22b1 to 22b3 formed on the front surfaces of the insulating plates 21a and 21b, and metal plates 23a and 23b formed on the rear surfaces of the insulating plates 21a and 21 b. The shapes, the numbers, and the arrangement of the conductive patterns 22a1 to 22a3, 22b1 to 22b3 are examples. The insulating plates 21a and 21b are made of high thermal conductivity ceramics such as alumina, aluminum nitride, and silicon nitride having excellent thermal conductivity. The conductive patterns 22a 1-22 a3 and 22b 1-22 b3 are made of metal such as copper or copper alloy with excellent conductivity. The metal plates 23a and 23b are made of a metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. As the ceramic circuit boards 20a and 20b having such a configuration, for example, a DCB (Direct Copper Bonding) board and an AMB (Active Metal soldered) board can be used. The ceramic circuit boards 20a and 20b can dissipate heat by conducting heat generated by the semiconductor chips 30a, 30b, 40a, and 40b to the lower side in fig. 1 through the conductive patterns 22a2 and 22b2, the insulating plates 21a and 21b, and the metal plates 23a and 23 b. The thickness of the conductive patterns 22a1 to 22a3 and 22b1 to 22b3 is preferably 0.10mm to 1.00mm, and more preferably 0.20mm to 0.50 mm. The wiring member 71 is bonded to the conductive pattern 22a2 of the ceramic circuit board 20a via solder (not shown). The wiring member 72 is joined to the conductive pattern 22b2 via solder (not shown). The wiring member 73 is joined to the conductive pattern 22a3 via solder (not shown). The squares shown in the conductive patterns 22a2, 22b2, and 22a3 indicate the bonding regions of the wiring members 71, 72, and 73.

The Semiconductor chips 30a and 30b are made of silicon or silicon carbide, and include switching elements such as IGBTs and power MOSFETs (Metal Oxide Semiconductor Field Effect transistors). Such semiconductor chips 30a and 30b include, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode on the front surface. The back surfaces of the semiconductor chips 30a and 30b are connected to the conductive patterns 22a2 and 22b2 by solder (not shown). The semiconductor chips 40a, 40b are made of silicon or silicon carbide, and include FWD elements such as SBD (Schottky Barrier Diode), PiN (P-intrinsic-N) Diode, and the like. Such semiconductor chips 40a and 40b include output electrodes (cathode electrodes) as main electrodes on the back surfaces thereof and input electrodes (anode electrodes) as main electrodes on the front surfaces thereof. The back surfaces of the semiconductor chips 40a and 40b are connected to the conductive patterns 22a2 and 22b2 by solder (not shown).

The following lead wires 50 are arranged on the ceramic circuit boards 20a and 20b and the semiconductor chips 30a, 30b, 40a, and 40 b. In fig. 1 and 2, the lead wires connecting the respective components other than the control wires are collectively referred to as a lead wire 50. The wires 55a and 55b as control wires are electrically connected to the conductive patterns 22a1 and 22b1 and the gates of the semiconductor chips 30a and 30b, respectively. The other wires 50 are electrically connected between the semiconductor chips 30a and 30b, the semiconductor chips 40a and 40b, and the conductive patterns 22a3 and 22b3 as appropriate. The lead wires 50 are made of a metal having excellent conductivity, such as aluminum or copper, or an alloy containing at least one of these metals. The diameter of these wires is 100 μm or more and 1.00mm or less. Preferably, the diameter of these wires is 250 μm or more and 500 μm or less. If the diameter of these wires is less than 250 μm, the allowable current per 1 wire is small, and a large number of wires are required, so that the number of bonding positions of the semiconductor chips 30a, 30b, 40a, and 40b increases, and the amount of heat generated during conduction at the bonding positions increases. If the diameter of the wires is larger than 500 μm, an excessive force is required for bonding the semiconductor chips 30a, 30b, 40a, and 40b, and the semiconductor chips 30a, 30b, 40a, and 40b may be broken.

The wiring members 71, 72, 73 are made of aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which is excellent in conductivity. In order to improve corrosion resistance, a metal such as nickel or gold may be formed on the surfaces of the wiring members 71, 72, and 73 by plating or the like, for example. Specifically, in addition to nickel and gold, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. Further, gold may be laminated on the nickel-phosphorus alloy.

The heat sink 60 is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which has excellent thermal conductivity. In order to improve the corrosion resistance, a material such as nickel may be formed on the surface of the heat sink 60 by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. A cooler (not shown) may be attached to the rear surface side of the heat sink 60 via solder, silver solder, or the like to improve heat dissipation. The cooler in this case is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which has excellent thermal conductivity. Further, as the cooler, a radiator composed of a plurality of fins or a cooling device using water cooling, or the like can be applied. The heat sink 60 may be formed integrally with such a cooler. In this case, the heat sink 60 is made of aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which has excellent thermal conductivity. In order to improve the corrosion resistance, a material such as nickel may be formed on the surface of the heat sink 60 integrated with the cooler by plating or the like, for example. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The case portion 70 and the cover portion 74 are each in a box shape and a flat plate shape, for example, and are made of thermoplastic resin. Examples of such resins include PPS resins, PBT resins, PBS resins, PA resins, and ABS resins. Further, the case 70 and the lid 74 are formed with opening holes (not shown) into which the terminals 71a, 72a, 73a of the wiring members 71, 72, 73 are inserted.

Next, details of the semiconductor chips 30a and 30b will be described with reference to fig. 3. Hereinafter, the semiconductor chips 30a and 30b will be collectively referred to as a semiconductor chip 30. Fig. 3 is a top view of a semiconductor chip. The semiconductor chip 30 is rectangular in plan view, and includes a gate electrode 31 (control electrode portion), an active region 32 (output electrode portion), and a gate runner 33 extending from the gate electrode 31 to the active region 32 at the center of the front end portion thereof. The semiconductor chip 30 has a size of 7mm or less in the vertical and horizontal directions, respectively.

The gate 31 receives a control voltage. The active region 32 is a region that outputs an output current when the wire 50 is bonded and the semiconductor chip 30 is in an on state. As shown in fig. 3, the active region 32 is composed of electrode regions 32a and 32b arranged with the gate runner 33 interposed therebetween. In addition, the electrode regions 32a, 32b are transistor regions in which a plurality of IGBTs are provided, respectively. The electrode regions 32a, 32b are insulated from each other, and the electrode regions 32a, 32b output independent output currents, respectively. The gate runner 33 is provided along the boundary portion of the electrode regions 32a and 32b as a transistor region. It should be noted that details of the electrode regions 32a, 32b will be described later. The gate runner 33 is electrically connected to the gate of each IGBT (or power MOSFET) of the electrode regions 32a, 32 b.

In addition, a plurality of bonding regions 35 are set in a lattice shape along the X direction and the Y direction on the front surfaces of the electrode regions 32a and 32b of the semiconductor chip 30. The bonding region 35 is a region where the wire 50 can be bonded. In each bonding region 35, 1 wire 50 can be bonded. In the case of fig. 3, 6 joint regions 35 in the vertical direction and 6 joint regions 35 in the horizontal direction are set, and 36 joint regions 35 in total are set. Note that, in fig. 3, for convenience, the directions along X (lateral) are denoted by [1] to [6], and the directions along Y (longitudinal) are denoted by [ a ] to [ f ]. Further, the joining region 35 is sometimes denoted as a, as necessary. Therefore, for example, among 36 joining regions 35, the joining region 35 corresponding to the position of [3] in the X direction and [ c ] in the Y direction is denoted as A3 c.

Next, the bonding position of the wire and the semiconductor chip 30 will be described with reference to fig. 4. Fig. 4 is a diagram for explaining a bonding position of a wire and a semiconductor chip in the embodiment. In fig. 4, a case where 5 wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30 will be described as an example. The following can be applied not only to the semiconductor chip 30 but also to the semiconductor chips 40a and 40 b.

In fig. 4, in the case of bonding 5 wires 50, 6 lattice-shaped bonding regions 35 are set in the X direction and the Y direction in the electrode regions 32a and 32b of the semiconductor chip 30, respectively. The bonding region 35 may be set in a lattice shape divided by the number equal to or more than the number of the wires 50 in the X direction and the Y direction. In the bonding regions 35 of the electrode regions 32a and 32b of the semiconductor chip 30 shown in fig. 4, 1 wire 50 is bonded to each of the 5 bonded regions 36 (hatched regions in fig. 4), and a total of 5 wires 50 are bonded. In this case, the plurality of bonded regions 36 of the electrode regions 32a and 32b, to which 1 of the plurality of wires 50 is bonded, are arranged so as not to overlap each other in the X direction parallel to one side of the semiconductor chip 30 and the Y direction orthogonal to the X direction in plan view. The bonded region 36 is sometimes denoted by B as necessary. For example, among the bonded regions 36 at 5, the bonded region 36 corresponding to the position of [5] in the X direction and [ B ] in the Y direction is sometimes denoted as B5B.

For example, the bonded regions (B2a, B4e, B5B, B6d) other than the bonded region 36(B1f) in the bonded region 36 at 5 will be described. The regions to be joined (B2a, B4e, B5B, B6d) are set so as not to overlap with the joining regions 35(A1f to A6f, A1a to A1f) arranged in the X direction and the Y direction including the region to be joined 36(B1f) in all the joining regions 35. That is, the regions to be joined (B2a, B4e, B5B, B6d) other than the region to be joined 36(B1f) are provided in the joining regions other than the joining regions 35(A1f to A6f, A1a to A1f) including the region to be joined 36(B1 f). Note that the regions to be joined (B1f, B4e, B5B, B6d) other than the region to be joined 36(B2a), the regions to be joined (B1f, B2a, B5B, B6d) other than the region to be joined 36(B4e), the regions to be joined (B1f, B2a, B4e, B6d) other than the region to be joined 36(B5B), and the regions to be joined (B1f, B2a, B4e, B5B) other than the region to be joined 36(B6d) are also provided in the same relationship as described above. By setting the bonded regions 36 to which the wires 50 are bonded in this manner, the wires 50 can be dispersedly bonded to the electrode regions 32a, 32b of the semiconductor chip 30. At this time, the bonding inhibiting regions 37 of the bonding regions 35(A3c, A3d, A4c, A4d) in the central portions of the electrode regions 32a, 32b of the semiconductor chip 30 are not bonded with the wires 50. The center of the electrode regions 32a and 32b as the bonding-inhibited regions 37 is, for example, in a range from the midpoint of the electrode regions 32a and 32b to a distance L1, and the distance L1 is, for example, 25% of the distance from the midpoint of the electrode regions 32a and 32b to the side of the semiconductor chip 30. The distance L1 can be set as appropriate.

Next, the surface temperature of the electrode regions 32a and 32b to which the wires 50 are bonded when the semiconductor chip 30 is energized will be described with reference to fig. 5. Fig. 5 is a diagram for explaining the surface temperature of the semiconductor chip of the embodiment. The temperature distribution image 80 shown in fig. 5 indicates line groups in which oblique line regions corresponding to the bonded regions 36 in fig. 4 and lines (broken lines T1 to T5) formed by a set of the same temperature ranges are connected at predetermined intervals. The region enclosed by the dotted line T1 represents the temperature distribution of 119 ℃ to 130 ℃. The region enclosed by the dotted line T2 represents the temperature distribution of 116 ℃ to 119 ℃. The region enclosed by the dotted line T3 represents the temperature distribution of 112 ℃ to 116 ℃. The region enclosed by the dotted line T4 represents the temperature distribution of 109 to 116 ℃. The region enclosed by the dotted line T5 represents the temperature distribution of 105 ℃ to 109 ℃. From the temperature distribution image 80, it is understood that the temperature is distributed almost uniformly over the entire electrode regions 32a and 32b, and although the region (T1) with a high temperature is located at the center, the region (T1) is small, and the region with a high temperature is not distributed uniformly over the entire electrode regions. The heat generation temperature of the semiconductor chip 30 at this time is about 124 ℃.

Here, a semiconductor chip of a reference example will be described with reference to fig. 6 with respect to the case of fig. 4. Fig. 6 is a diagram for explaining a bonding position between a wire and a semiconductor chip of a reference example. In fig. 6, similarly to fig. 4, a case where 5 wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30 will be described as an example. In fig. 6, 5 wires 50 are bonded to 5 bonded regions 36 (hatched regions: B in fig. 6) of the plurality of bonding regions 35(a) of the electrode regions 32a and 32B of the semiconductor chip 30, respectively.

The semiconductor chip 30 of fig. 6 is bonded with the wires 50 in the bonding regions 35(A1a, A2a, A4f, A5f, A6f) among the plurality of bonding regions 35 to set bonded regions 36(B1a, B2a, B4f, B5f, B6 f). By bonding the wires 50 to the diagonal corners of the electrode regions 32a and 32b in this manner, it is desired to suppress the temperature rise by avoiding the central portion having the highest temperature when the semiconductor chip 30 is energized.

Next, the surface temperature of the electrode regions 32a, 32b of fig. 6 to which the wires 50 are bonded when the semiconductor chip 30 is energized will be described with reference to fig. 7. Fig. 7 is a graph for explaining the surface temperature of the semiconductor chip of the reference example. The temperature distribution image 80a shown in fig. 7 shows, similarly to fig. 5, line groups in which the diagonal line regions corresponding to the bonded regions 36 in fig. 6 and the lines (broken lines T1 to T5) formed by the sets of the same temperature ranges are connected at predetermined intervals. From the temperature distribution image 80a, the temperature rises so as to cross the bonded region 36 located at the corner on the diagonal line of the electrode regions 32a, 32 b. In particular, it can be seen that the central portions of the electrode regions 32a, 32b are temperature distributions of the dotted lines T1, T2 where the temperatures are high. This is considered to cause thermal interference between the diagonally bonded regions 36, and the temperature rise of the central portions of the electrode regions 32a and 32b of the semiconductor chip 30 occurs. Thus, the range of the temperature distribution of the broken lines T1, T2 of fig. 6 and 7 is larger than the range of the temperature distribution of the broken lines T1, T2 of fig. 4 and 5. The heat generation temperature of the semiconductor chip 30 at this time is about 127 ℃, and is increased by about 2.5% relative to the heat generation temperature of the semiconductor chip 30 in fig. 5.

The semiconductor device 10 includes a semiconductor chip 30 having electrode regions 32a and 32b on the front surface thereof, and a plurality of wires 50 bonded to the electrode regions 32a and 32b, respectively. At this time, the plurality of bonded regions 36 of the electrode regions 32a, 32b to which the plurality of wires 50 are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip 30 and in a Y direction orthogonal to the X direction in plan view. Thus, the wires 50 are dispersedly bonded to the electrode regions 32a, 32b of the semiconductor chip 30, so that the temperature is almost uniformly distributed over the entire electrode regions 32a, 32b, and uneven distribution in a region with a high temperature is suppressed. As a result, an increase in the heat generation temperature of the semiconductor chip 30 can be suppressed, and a decrease in the reliability of the semiconductor device 10 can be suppressed.

Further, in the case of fig. 4, the lead wires 50 are bonded to the outer edge portions of the electrode regions 32a, 32 b. This is to suppress a further temperature rise because the temperature rise in the center portions of the electrode regions 32a, 32b is particularly high in the semiconductor chip 30. The outer edge portions of the electrode regions 32a and 32b are in the range from the respective sides of the electrode regions 32a and 32b to a distance L2, and the distance L2 is, for example, 50% of the distance from the midpoint of the electrode regions 32a and 32b to the side of the semiconductor chip 30. The distance L2 can be set as appropriate.

In addition, when the semiconductor chip 30 includes, for example, SiC-MOSFETs or SiC-SBDs as switching elements made of silicon carbide, a large current can flow. On the other hand, in the semiconductor chip 30, the bonded region 36 to which the wire 50 is bonded is likely to increase in temperature. Therefore, when the lead 50 is bonded to the bonded region 36 in this way, it is possible to suppress a temperature increase of the semiconductor device 10 and reliably cope with a large current. In the present embodiment, the center and outer edge portions of the electrode regions 32a and 32b are also in the same range as in fig. 4 except for fig. 4.

Next, a case where the 4 wires 50 are bonded to the electrode regions 32a, 32b of the semiconductor chip 30 will be described with reference to fig. 8. Fig. 8 is a diagram for explaining a bonding position between a wire and a semiconductor chip according to the embodiment. Similarly to fig. 4, the semiconductor chip 30 shown in fig. 8 also includes electrode regions 32a and 32b, and a plurality of bonding regions 35 are set. In fig. 8, 6 lattice-shaped bonding regions 35 are provided in the electrode regions 32a and 32b of the semiconductor chip 30 along the X direction and the Y direction, respectively, for bonding 4 wires 50. The bonding region 35 may be set in a lattice shape divided by the number equal to or more than the number of the wires 50 in the X direction and the Y direction as shown in the drawing. More preferably, the bonding regions 35 are set in a grid shape divided by the same number as the number of the wires 50 in the X direction and the Y direction. In the bonding regions 35, 1 wire 50 is bonded to each of the 4 bonded regions 36 (hatched regions in fig. 8), and a total of 4 wires 50 are bonded. At this time, the plurality of bonded regions 36 of the electrode regions 32a, 32b to which the plurality of wires 50 are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip 30 and in a Y direction orthogonal to the X direction in plan view.

In the joined region 36 at the point 4, for example, joined regions (B2a, B5B, B6e) other than the joined region 36(B1f) are described. The bonded regions (B2a, B5B, B6e) are any of the bonding regions excluding the bonding regions 35(A1f to A6f, A1a to A1f) arranged in the X direction and the Y direction including the bonded region 36(B1f) from all the bonding regions 35. That is, the regions to be joined (B2a, B5B, B6e) other than the region to be joined 36(B1f) are provided in the joining regions other than the joining regions 35(A1f to A6f, A1a to A1f) including the region to be joined 36(B1 f). Further, the joined regions (B1f, B5B, B6e) other than the joined region 36(B2a), the joined regions (B1f, B2a, B6e) other than the joined region 36(B5B), and the joined regions (B1f, B2a, B5B) other than the joined region 36(B6e) are also provided in the same relationship as described above.

As a reference example for the case of fig. 8, a case where the lead wires 50 are simply bonded to the four corners of the electrode regions 32a and 32b of the semiconductor chip 30 will be described with reference to fig. 9. Fig. 9 is a diagram for explaining a bonding position between a lead and a semiconductor chip of a reference example. As shown in fig. 9, bonded regions 36(B1a, B1f, B6a, B6f) are set in the bonding regions 35(A1a, A1f, A6a, A6f) at the corners of the electrode regions 32a, 32B of the semiconductor chip 30, respectively. However, if the bonded regions 36(B1a, B1f, B6a, B6f) are set at the four corners of the electrode regions 32a, 32B of the semiconductor chip 30, thermal interference occurs between the bonded regions 36(B1a, B1f, B6a, B6 f). As a result, the temperature of the central portions of the electrode regions 32a and 32b of the semiconductor chip 30 rises, and the heat generation temperature of the semiconductor chip 30 in fig. 9 becomes higher than that in fig. 8.

Therefore, by setting the bonded regions 36 to which the 4 wires 50 are bonded as shown in fig. 8, the wires 50 can be dispersedly bonded to the electrode regions 32a, 32b of the semiconductor chip 30. Further, at this time, the bonding-inhibited regions 37 of the bonding regions 35(A3c, A3d, A4c, A4d) at the central portions of the electrode regions 32a, 32b of the semiconductor chip 30 are made not to bond the wires 50. Thus, the wires 50 are dispersedly bonded to the electrode regions 32a, 32b of the semiconductor chip 30, so that the temperature is almost uniformly distributed over the entire electrode regions 32a, 32b, and uneven distribution in a region with a high temperature is suppressed. As a result, an increase in the heat generation temperature of the semiconductor chip 30 can be suppressed, and a decrease in the reliability of the semiconductor device 10 can be suppressed.

Next, a case where 6 wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30 will be described with reference to fig. 10. Fig. 10 is a diagram for explaining a bonding position between a wire and a semiconductor chip according to the embodiment. As in fig. 4 and 8, the semiconductor chip 30 shown in fig. 10 also includes electrode regions 32a and 32b, and a plurality of bonding regions 35 are set. In fig. 10, in order to bond 6 wires 50, 6 lattice-shaped bonding regions 35 are provided in the X direction and the Y direction in the electrode regions 32a and 32b of the semiconductor chip 30, respectively. The bonding region 35 may be set in a lattice shape divided by the number equal to or more than the number of the wires 50 in the X direction and the Y direction. More preferably, as shown in fig. 10, the bonding regions 35 are set in a grid shape divided by the same number as the number of the wires 50 in the X direction and the Y direction. In the bonding regions 35, 1 wire 50 is bonded to each of the 6 bonded regions 36 (hatched regions in fig. 10), and a total of 6 wires 50 are bonded. At this time, the plurality of bonded regions 36 of the electrode regions 32a, 32b to which the plurality of wires 50 are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip 30 and in a Y direction orthogonal to the X direction in plan view.

In the case of fig. 10, the bonded regions 36 are provided in the electrode regions 32a and 32b except the bonding-inhibited region 37 in the central portion. Further, at this time, all the groups of the joined regions 36 in a set of 2 selected from the 6 joined regions 36 are disposed in point symmetry with respect to the center point. For example, a group of the joined regions 36(B1c, B6d) is disposed in point symmetry with respect to a center point. Further, a group of the joined regions 36(B2e, B5B) is disposed in point symmetry with respect to the center point. Further, a group of the joined regions 36(B3a, B4f) is disposed in point symmetry with respect to the center point. Further, the bonded regions 36 are arranged line-symmetrically with respect to the diagonal line D of the electrode regions 32a, 32 b. For example, a group of the joined regions 36(B1c, B3a) is disposed line-symmetrically with respect to the diagonal line D. Further, a group of the joined regions 36(B2e, B5B) is disposed line-symmetrically with respect to the diagonal line D. Further, a group of the joined regions 36(B4f, B6D) is disposed line-symmetrically with respect to the diagonal line D.

In the case of an even number of wires 50, an even number of bonded regions 36 can thus be arranged for the electrode regions 32a, 32b of the semiconductor chip 30. In this case, the joined region 36 can be configured to be point-symmetrical with respect to the center point. Further, the bonded regions 36 can be arranged line-symmetrically with respect to the diagonal line D of the electrode regions 32a, 32 b. By arranging the bonded regions 36 in this manner and bonding 1 wire 50 to each of the bonded regions 36, the wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30 in a dispersed manner. Thus, the temperature is distributed almost uniformly over the entire electrode regions 32a and 32b, and the uneven distribution in the region where the temperature is high is suppressed. As a result, an increase in the heat generation temperature of the semiconductor chip 30 can be suppressed, and a decrease in the reliability of the semiconductor device 10 can be suppressed.

In the above description, the number of divisions of the bonding region 35 of the electrode regions 32a, 32b of the semiconductor chip 30 is an example. The number of the electrode regions 32a and 32b, the number of the wires 50, and the diameter can be appropriately set according to the area of the electrode regions 32a and 32b, and not limited to 6 in the X direction and 6 in the Y direction. Even numbers of the wires 50 may be provided with even numbers of the bonded regions 36 to the electrode regions 32a, 32b of the semiconductor chip 30. Therefore, as another example, a case where the electrode regions 32a and 32b of the semiconductor chip 30 are divided into 4 in the X direction and 4 in the Y direction will be described with reference to fig. 11. Fig. 11 is a diagram for explaining a bonding position between a wire and a semiconductor chip according to the embodiment. Here, 4 wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30. As shown in fig. 11, in order to bond 4 wires 50, 4 lattice-shaped bonding regions 35 are provided in the X direction and the Y direction in the electrode regions 32a and 32b of the semiconductor chip 30, respectively. The bonding region 35 may be set in a lattice shape divided by the number equal to or greater than the number of the wires 50 in the X direction and the Y direction. More preferably, as shown in fig. 11, the bonding regions 35 are set in a grid shape divided by the same number as the number of the wires 50 in the X direction and the Y direction. In the bonding regions 35, 1 wire 50 is bonded to each of the 4 bonded regions 36 (hatched regions in fig. 11), and a total of 4 wires 50 are bonded. At this time, the plurality of bonded regions 36 of the electrode regions 32a, 32b to which the plurality of wires 50 are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip 30 and in a Y direction orthogonal to the X direction in plan view. Further, at this time, all the groups of the joined regions 36 in a set of 2 selected from the 4 joined regions 36 are disposed in point symmetry with respect to the center point. For example, a group of the joined regions 36(B1c, B4B) is disposed in point symmetry with respect to a center point. Further, a group of the joined regions 36(B2a, B3d) is disposed in point symmetry with respect to the center point. Further, the bonded regions 36 are arranged such that a straight line connecting the bonded regions 36(B1c, B4B) and a straight line connecting the bonded regions 36(B2a, B3d) are substantially orthogonal to each other.

As another example, a case where the electrode regions 32a and 32b of the semiconductor chip 30 are divided into 8 in the X direction and 8 in the Y direction will be described with reference to fig. 12. Fig. 12 is a diagram for explaining a bonding position between a wire and a semiconductor chip according to the embodiment. Here, 8 wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30. As shown in fig. 12, in order to bond 8 wires 50, 8 lattice-shaped bonding regions 35 are provided in the X direction and the Y direction in the electrode regions 32a and 32b of the semiconductor chip 30, respectively. The bonding region 35 may be set in a lattice shape divided by the number equal to or greater than the number of the wires 50 in the X direction and the Y direction. More preferably, as shown in fig. 12, the bonding regions 35 are set in a grid shape divided by the same number as the number of the wires 50 in the X direction and the Y direction. In the bonding regions 35, 1 wire 50 is bonded to each of the 8 bonded regions 36 (hatched regions in fig. 12), and a total of 8 wires 50 are bonded. At this time, the plurality of bonded regions 36 of the electrode regions 32a, 32b to which the plurality of wires 50 are bonded are arranged so as not to overlap each other in an X direction parallel to one side of the semiconductor chip 30 and a Y direction orthogonal to the X direction in plan view. Further, at this time, all the groups of the joined regions 36 in a set of 2 selected from the 8 joined regions 36 are disposed in point symmetry with respect to the center point. For example, a group of the joined regions 36(B1d, B8e) is disposed in point symmetry with respect to a center point. Further, a group of the joined regions 36(B2f, B7c) is disposed in point symmetry with respect to the center point. Further, a group of the joined regions 36(B3B, B6g) is disposed in point symmetry with respect to the center point. Further, a group of the joined regions 36(B4h, B5a) is disposed in point symmetry with respect to the center point.

As shown in fig. 11 and 12, even numbers of the regions to be bonded 36 can be arranged for even numbers of the wires 50 in the electrode regions 32a and 32b of the semiconductor chip 30. The joined region 36 can be configured to be point-symmetric with respect to the center point. By arranging the bonded regions 36 in this manner and bonding 1 wire 50 to each of the bonded regions 36, the wires 50 are bonded to the electrode regions 32a and 32b of the semiconductor chip 30 in a dispersed manner. This makes the temperature in electrode regions 32a and 32b distributed almost uniformly over the entire region, and suppresses uneven distribution in regions with high temperature. As a result, an increase in the heat generation temperature of the semiconductor chip 30 can be suppressed, and a decrease in the reliability of the semiconductor device 10 can be suppressed.

In the case where the number of the lead wires 50 is 3 or less, even if the bonded regions 36 are set in a dispersed manner as shown in fig. 4, 8, and 10 to 12, the suppression of the increase in the heat generation temperature of the semiconductor chip 30 is almost unchanged as compared with the case where only the bonded regions 36 are set in the outer peripheral portions of the electrode regions 32a, 32b of the semiconductor chip 30. Therefore, in particular, the number of the wires 50 is preferably 4 or more. In addition, even if the bonded regions 36 are set in a dispersed manner as shown in fig. 4, 8, and 10 to 12 in the case where the semiconductor chip 30 has a large size and the number of lead wires is small, the suppression of the increase in the heat generation temperature of the semiconductor chip 30 is not substantially changed as compared with the case where the bonded regions 36 are set only in the outer peripheral portions of the electrode regions 32a, 32b of the semiconductor chip 30. Therefore, in particular, the semiconductor chip 30 preferably has a size of 7mm or less in the longitudinal direction and the lateral direction, respectively, and 4 or more wires 50. In this embodiment, only the same division numbers of 4, 6, and 8 electrode regions 32a and 32b in the X direction and the Y direction of the semiconductor chip 30 are shown, but the division numbers in the X direction and the Y direction may be different. For example, there may be 4 in the X direction, 6 in the Y direction, and so on.