阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 朱慧珑 于 2018-09-19 设计创作，主要内容包括：一种半导体装置,包括：衬底,包括基底衬底、基底衬底上的第一半导体层以及第一半导体层上的第二半导体层；在衬底上形成的沿同一直线延伸的第一和第二鳍状结构,每一鳍状结构至少包括第二半导体层；在所述直线两侧绕第一和第二鳍状结构形成的第一隔离部；分别基于第一和第二鳍状结构在衬底上形成的第一FinFET和第二FinFET,其中,第一和第二FinFET包括在第一隔离部上形成的分别与第一和第二鳍状结构相交的第一和第二栅堆叠；以及第一和第二鳍状结构之间、与第一和第二鳍状结构相交从而将第一鳍状结构和第二鳍状结构彼此隔离的第二隔离部,其中第二隔离部与第一和第二栅堆叠中至少之一平行延伸。(A semiconductor device, comprising: a substrate including a base substrate, a first semiconductor layer on the base substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending along a same straight line, each fin structure including at least a second semiconductor layer; first isolation portions formed around the first and second fin structures on both sides of the straight line; a first FinFET and a second FinFET formed on the substrate based on the first and second fin structures, respectively, wherein the first and second FinFETs include first and second gate stacks formed on the first isolation portion intersecting the first and second fin structures, respectively; and a second isolation portion between and intersecting the first and second fin structures to isolate the first and second fin structures from each other, wherein the second isolation portion extends parallel to at least one of the first and second gate stacks.)

1. A semiconductor device, comprising:

a substrate including a base substrate, a first semiconductor layer disposed on the base substrate, and a second semiconductor layer disposed on the first semiconductor layer;

a first fin structure and a second fin structure formed on the substrate and extending along a same straight line, each of the first fin structure and the second fin structure including at least a second semiconductor layer;

first isolation portions formed around the first fin structure and the second fin structure on both sides of the straight line;

a first fin field effect transistor (FinFET) formed on the substrate based on the first fin structure and a second FinFET formed on the substrate based on the second fin structure, wherein the first FinFET comprises a first gate stack formed on the first isolation portion and intersecting the first fin structure, and the second FinFET comprises a second gate stack formed on the first isolation portion and intersecting the second fin structure; and

a second isolation portion between the first and second fin structures intersecting the first and second fin structures to isolate the first and second fin structures from each other, wherein the second isolation portion extends parallel to at least one of the first and second gate stacks.

2. The semiconductor device according to claim 1, wherein a top surface of the first isolation portion is below a top surface of the second semiconductor layer or below a bottom surface of the second semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein in a longitudinal section taken along the straight line, the second isolation portion includes an upper portion and a lower portion, the lower portion being relatively enlarged with respect to a bottom end of the upper portion.

4. The semiconductor device according to claim 3, wherein a top end of an upper portion of the second isolation portion is relatively enlarged with respect to a bottom end in the longitudinal section.

5. The semiconductor device according to claim 3, wherein a lower portion of the second isolation portion forms a stepped portion with respect to a bottom end of the upper portion, the stepped portion being coplanar with a bottom surface of the second semiconductor layer.

6. The semiconductor device of claim 3, wherein the second isolation portion passes through the second semiconductor layer from top to bottom, wherein a top surface of a portion of the second isolation portion directly under the first fin structure meets a bottom surface of the second semiconductor layer, and a top surface of a portion of the second isolation portion directly under the second fin structure meets the bottom surface of the second semiconductor layer.

7. The semiconductor device of claim 3, wherein, in the direction of extension of the straight line, a portion of the second isolation directly under the first fin structure extends to a location of a source/drain region of the first FinFET, and a portion of the second isolation directly under the second fin structure extends to a location of a source/drain region of the second FinFET.

8. The semiconductor device according to one of claims 3 to 5, further comprising:

a third isolation portion extending along the first fin structure under the second semiconductor layer in the first fin structure and/or a fourth isolation portion extending along the second fin structure under the second semiconductor layer in the second fin structure.

9. The semiconductor device according to claim 8, wherein at least one of the following holds true:

in a longitudinal section taken along the straight line, the third spacer is vertically centrally aligned with the first gate stack; and

in a longitudinal section taken along the straight line, the fourth spacer is vertically centrally aligned with the second gate stack.

10. The semiconductor device according to claim 8, wherein at least one of the following holds true:

the top surface of the third isolation part is connected with the bottom surface of the second semiconductor layer in the first fin-shaped structure;

the top surface of the fourth isolation portion is connected with the bottom surface of the second semiconductor layer in the second fin-shaped structure.

11. The semiconductor device according to claim 8 when dependent on claim 4, wherein top surfaces of the third and fourth isolation portions are coplanar with the step portion.

12. The semiconductor device according to claim 8, wherein at least one of the following holds true:

in the extending direction of the straight line, the third isolation part extends to the position of the source/drain region of the first FinFET;

in the extending direction of the straight line, the fourth isolation portion extends to the position of the source/drain region of the second FinFET.

13. The semiconductor device according to claim 7 or 12, further comprising: at least partially embedding additional semiconductor layers formed in the respective fin structures on opposite sides of each of the first and/or second gate stacks, wherein source/drain regions of each of the first and/or second finFETs are at least partially formed in the additional semiconductor layers,

wherein the additional semiconductor layer of at least one of the first FinFET and the second FinFET is a stacked structure.

14. The semiconductor device according to one of claims 3 to 7, wherein the lower portion and the upper portion of the second isolation portion are aligned centrally in a vertical direction in a longitudinal section taken along the straight line.

15. The semiconductor device according to claim 14, further comprising:

a first sidewall on a sidewall of the first gate stack;

a second sidewall on a sidewall of the second gate stack; and

and the second isolation part is self-aligned to the space limited by the dummy side wall.

16. The semiconductor device according to one of claims 3 to 7, further comprising: an insulating thin layer formed at least on a sidewall of the upper portion of the second isolation portion.

17. The semiconductor device according to claim 1, further comprising: and an insulating thin layer formed on at least a part of the sidewall of the second isolation portion.

Technical Field

The present disclosure relates generally to the field of integrated circuit fabrication, and more particularly, to a semiconductor device including an isolation portion that may reduce area overhead.

Background

With the increasing demand for multifunctional, miniaturized electronic devices, it is desirable to integrate more and more devices on a wafer. However, with current devices being miniaturized to approach physical limits, it is increasingly difficult to further reduce the average area per device. Furthermore, any area overhead may result in increased manufacturing costs.

One of the solutions to satisfy the miniaturization trend is a stereoscopic device such as a FinFET (fin field effect transistor). In the FinFET, the area occupied on the wafer surface is reduced by extending in the height direction. However, isolation between finfets takes up more area than planar devices such as MOSFETs, since two dummy gates are required for each isolation. In addition, the alignment precision of patterning or photolithography also occupies an area when forming the isolation, increasing the manufacturing cost.

Disclosure of Invention

In view of the above problems, the present disclosure proposes a semiconductor device to solve at least the above problems and/or to provide at least the following advantages.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate including a base substrate, a first semiconductor layer disposed on the base substrate, and a second semiconductor layer disposed on the first semiconductor layer; a first fin structure and a second fin structure formed on the substrate and extending along a same straight line, each of the first fin structure and the second fin structure including at least a second semiconductor layer; first isolation portions formed around the first fin structure and the second fin structure on both sides of the straight line; a first fin field effect transistor (FinFET) formed on the substrate based on the first fin structure and a second FinFET formed on the substrate based on the second fin structure, wherein the first FinFET includes a first gate stack formed on the first isolation portion that intersects the first fin structure, and the second FinFET includes a second gate stack formed on the first isolation portion that intersects the second fin structure; and a second isolation portion between and intersecting the first and second fin structures to isolate the first and second fin structures from each other, wherein the second isolation portion extends parallel to at least one of the first and second gate stacks.

According to an embodiment, the top surface of the first isolation portion may be below the top surface of the second semiconductor layer or below the bottom surface of the second semiconductor layer.

According to an embodiment, in a longitudinal section taken along the straight line, the second partition may include an upper portion and a lower portion, the lower portion being relatively enlarged with respect to a bottom end of the upper portion.

According to an embodiment, in the longitudinal section, a top end of an upper portion of the second isolation portion may be relatively enlarged with respect to a bottom end.

According to an embodiment, the lower portion of the second isolation portion may form a stepped portion with respect to a bottom end of the upper portion, the stepped portion being coplanar with a bottom surface of the second semiconductor layer.

According to an embodiment, the second isolation portion may pass through the second semiconductor layer from top to bottom, wherein a top surface of a portion of the second isolation portion directly under the first fin structure meets a bottom surface of the second semiconductor layer, and a top surface of a portion of the second isolation portion directly under the second fin structure meets the bottom surface of the second semiconductor layer.

According to an embodiment, in an extension direction of the straight line, a portion of the second isolation portion directly under the first fin structure may extend to a location of a source/drain region of the first FinFET, and a portion of the second isolation portion directly under the second fin structure may extend to a location of a source/drain region of the second FinFET.

According to an embodiment, the semiconductor device may further include: a third isolation portion extending along the first fin structure under the second semiconductor layer in the first fin structure and/or a fourth isolation portion extending along the second fin structure under the second semiconductor layer in the second fin structure.

According to an embodiment, at least one of the following holds: in a longitudinal section taken along the straight line, the third spacer is vertically centrally aligned with the first gate stack; and in a longitudinal section taken along the straight line, the fourth spacer is vertically center-aligned with the second gate stack.

According to an embodiment, at least one of the following holds: the top surface of the third isolation part is connected with the bottom surface of the second semiconductor layer in the first fin-shaped structure; the top surface of the fourth isolation portion is connected with the bottom surface of the second semiconductor layer in the second fin-shaped structure.

According to an embodiment, top surfaces of the third and fourth isolation portions may be coplanar with the step portion.

According to an embodiment, at least one of the following holds: in the extending direction of the straight line, the third isolation part extends to the position of the source/drain region of the first FinFET; in the extending direction of the straight line, the fourth isolation portion extends to the position of the source/drain region of the second FinFET.

According to an embodiment, the semiconductor device may further comprise a further semiconductor layer formed at least partially embedded in the respective fin structure at opposite sides of each of the first gate stack and/or the second gate stack, wherein the source/drain region of each of the first FinFET and/or the second FinFET is at least partially formed in said further semiconductor layer, wherein said further semiconductor layer of at least one of the first FinFET and the second FinFET is a stacked structure.

According to an embodiment, the lower portion and the upper portion of the second partition may be centrally aligned in a vertical direction in a longitudinal section taken along the straight line.

According to an embodiment, the semiconductor device may further include: a first sidewall on a sidewall of the first gate stack; a second sidewall on a sidewall of the second gate stack; and the dummy side wall is arranged between the first side wall and the second side wall, wherein the second isolation part is self-aligned to the space limited by the dummy side wall.

According to an embodiment, the semiconductor device may further include: an insulating thin layer formed at least on a sidewall of the upper portion of the second isolation portion.

According to an embodiment, the semiconductor device may further include an insulating thin layer formed at least on a portion of the sidewall of the second isolation portion.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a laminated structure in which a base substrate, a first semiconductor layer and a second semiconductor layer are sequentially laminated; forming a fin structure on the stacked structure, wherein a bottom of the fin structure is lower than a bottom surface of the second semiconductor layer; forming first isolation portions around the fin structure on both sides of the fin structure; forming a dummy gate structure intersecting the fin structure on the first isolation portion, and forming a first gate structure and a second gate structure intersecting the fin structure on two opposite sides of the dummy gate structure respectively; respectively forming a first gate side wall, a second gate side wall and a dummy side wall on the side walls of the first gate structure, the second gate structure and the dummy gate structure; removing the dummy gate structure to expose the first semiconductor layer on the inner side of the dummy side wall; selectively etching the first semiconductor layer; filling a dielectric material into a space formed below the second semiconductor layer on the inner side of the dummy side wall due to the selective etching of the first semiconductor layer to form a part of the second isolation part; selectively etching the fin-shaped structure based on the dummy side wall; and filling a dielectric material into the inner side of the dummy side wall to form the other part of the second isolation part.

According to an embodiment, the first gate structure, the second gate structure, and the dummy gate structure may be sacrificial gate structures. In this case, when removing the dummy gate structure, the method may further include removing the first gate structure and the second gate structure. Selectively etching the first semiconductor layer may include: and selectively etching the exposed first semiconductor layer due to the removal of the dummy gate structure, the first gate structure and the second structure. Forming a portion of the second isolation portion may further include: filling a dielectric material into a space formed below the second semiconductor layer on the inner side of the first gate side wall due to the selective etching of the first semiconductor layer to form a third isolation part; and filling a dielectric material into a space formed below the second semiconductor layer on the inner side of the second gate side wall due to the selective etching of the first semiconductor layer to form a fourth isolation part. After forming a portion of the second isolation portion, the third isolation portion and the fourth isolation portion, the method may include forming a replacement gate structure in the dummy sidewall and spaces inside the first and second gate sidewalls, and removing the replacement gate structure inside the dummy sidewall to expose the fin structure, so as to selectively etch the fin structure.

According to an embodiment, the method may further comprise: and forming additional semiconductor layers at least partially embedded in the fin-shaped structure on two opposite sides of the first gate side wall and/or the second gate side wall.

According to an embodiment, the selective etching stops laterally on the further semiconductor layer when the first semiconductor layer is selectively etched. The further semiconductor layer may be a stacked structure.

According to an embodiment, the method may further comprise: and forming an insulating side wall on the side wall of the groove obtained in the dummy side wall by selectively etching the fin-shaped structure.

According to an embodiment, after the selectively etching the fin structure and before forming the insulating sidewall spacers, the method may further include: removing the portion of the second isolation portion.

According to an embodiment, exposing the first semiconductor layer inside the dummy sidewall may include: and selectively etching the first isolation part to at least partially expose the side wall of the first semiconductor layer.

According to still another aspect of the present disclosure, there is also provided an electronic apparatus including the semiconductor device described above.

According to the embodiments of the present disclosure, an isolation portion such as STI, which is self-aligned between the dummy gate sidewalls, may be formed. Therefore, only one dummy gate is needed for each isolation, and the area occupied by the isolation part is reduced. In addition, the alignment precision of patterning or photoetching is increased when the isolation is formed, and the manufacturing cost is reduced. The techniques of this disclosure are particularly applicable to finfets.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIGS. 1(a) -22 are schematic diagrams illustrating a middle staging of a flow for fabricating a semiconductor device according to an embodiment of the disclosure; and

fig. 23-32 are schematic diagrams illustrating a middle-of-the-flow staging of a process for fabricating a semiconductor device according to another embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device is fabricated, for example, on a bulk semiconductor substrate. The semiconductor arrangement may include a first semiconductor device and a second semiconductor device adjacently disposed on a substrate. Such semiconductor devices include, for example, fin field effect transistors (finfets). In this case, each semiconductor device may include a respective fin and a gate stack intersecting the fin. For example, the fins may be obtained by patterning the substrate. In some examples, the first semiconductor device and the second semiconductor device may share the same fin. In addition, gate spacers may be formed on sidewalls of the gate stack.

To electrically isolate the first semiconductor device from the second semiconductor device (if desired), an isolation may be formed therebetween. The spacer may be self-aligned to a space defined by (on an inner side of) a dummy gate sidewall provided between the first semiconductor device and the second semiconductor device. Such self-aligned spacers may be formed by etching a trench (and thus the sidewalls of the trench extending substantially along the inner walls of the dummy gate sidewalls) using the dummy gate sidewalls as a mask, and then filling the trench with a dielectric material.

For example, the dummy gate sidewall spacers may be fabricated according to the same process as the respective gate sidewall spacers of the first semiconductor device and the second semiconductor device. In addition, the dummy gate stack may be formed in the same process as the gate stacks of the first and second semiconductor devices, respectively. In other words, a dummy device (including a dummy gate stack and dummy gate sidewalls) similar to the first and/or second semiconductor device may be formed between the first semiconductor device and the second semiconductor device. These devices (including dummy devices) may have substantially the same gate stack and gate sidewalls, and their gate stacks and, correspondingly, the gate sidewalls may be substantially aligned.

In the case where the first and second semiconductor devices share the same fin, the dummy gate structure may also intersect the fin, thereby forming a dummy FinFET. That is, three devices (including one dummy device) may be formed intersecting a common fin. At this time, the dummy gate isolation portion (or trench) may extend through the fin, thereby isolating the respective active regions of the first and second semiconductor devices.

The source/drain regions of each semiconductor device may be formed in the substrate (e.g., in the fins in the case of finfets) on opposite sides of the respective gate stack. According to an advantageous example, a further semiconductor layer may be formed at least partially embedded in the fin, and the source/drain regions may be formed at least partially in the further semiconductor layer. Such further semiconductor layer may comprise a material different from the substrate in order to stress the channel region. For example, for an N-type device, tensile stress may be applied; while for a P-type device, compressive stress may be applied.

The present disclosure may be presented in a number of ways, some examples of which are described below.

Fig. 1(a) -22 are schematic diagrams illustrating a middle staging of a flow for manufacturing a semiconductor device according to an embodiment of the present disclosure.

As shown in fig. 1(a), 1(b) and 1(c) (fig. 1(a) is a top view, fig. 1(b) is a sectional view taken along line AA 'in fig. 1(a), and fig. 1(c) is a sectional view taken along line BB' in fig. 1 (a)), a bulk material substrate 1002 is provided. The substrate may comprise various suitable bulk semiconductor materials such as Si, Ge, SiGe, etc. Hereinafter, a silicon-based material is described as an example, but the present disclosure is not limited thereto.

In the substrate 1002, a well region 1002-1 may be formed, for example, by ion implantation. For example, for a P-type device, an N-type well region may be formed; and for an N-type device, a P-type well region may be formed. For example, an N-type well region may be formed by implanting an N-type impurity such As P or As in the substrate 1002, and a P-type well region may be formed by implanting a P-type impurity such As B in the substrate 1002. Annealing may also follow the implantation if desired. Those skilled in the art can form N-type well and P-type well in many ways, which will not be described herein.

On the substrate 1002, a mask layer may be formed by, for example, deposition. The mask layer may comprise a stack of an oxide (e.g., silicon nitride) layer 1004 having a thickness of about 5-20nm and a nitride layer (e.g., silicon nitride) 1006 having a thickness of about 50-150 nm. On the mask layer, a photoresist 1008 may be formed, the photoresist 1008 being patterned into a fin shape, for example, by photolithography, so as to subsequently form a fin structure on the substrate.

Next, as shown in fig. 2(a), 2(b) and 2(c) (fig. 2(a) is a top view, fig. 2(b) is a cross-sectional view taken along line AA 'in fig. 2(a), and fig. 2(c) is a cross-sectional view taken along line BB' in fig. 2 (a)), the mask layer and the substrate 1002 are subjected to selective etching such as Reactive Ion Etching (RIE) using the photoresist 1008 as a mask, thereby forming the fin structure F. More specifically, trenches are formed in the substrate 1002 by RIE, and portions between the trenches are relatively protruded, thereby constituting the fin structure F. The RIE may, for example, proceed in a direction generally perpendicular to the substrate surface, and the resulting fin structure F may then extend substantially vertically relative to the substrate surface. The photoresist 1008 may then be removed.

It is to be noted here that although in this example, the fin structure is formed by directly patterning the substrate, the present disclosure is not limited thereto. For example, an epitaxial layer may be formed on the substrate, and the fin structure may be formed by patterning the epitaxial layer. In the present disclosure, the expression "forming a fin structure on a substrate" includes forming a fin structure on a substrate in any suitable manner, and the expression "a fin structure formed on a substrate" includes forming a fin structure on a substrate in any suitable manner.

In addition, in the example shown in fig. 2(a), 2(b), and 2(c), the case where the selective etching at the time of forming the fin structure F enters into the well region 1002-1 is shown. However, the present disclosure is not limited thereto. For example, the position of the selective etching stop can be determined according to the actual requirement, for example, the selective etching stop can be stopped at the top surface of the well region 1002-1.

This fin structure F will then form the active area of the device. As shown in fig. 3 (a cross-sectional view along line BB'), around the active region, an isolation layer 1009 (which may be referred to as a "first isolation portion"), such as a Shallow Trench Isolation (STI), may be provided. For example, STI can be formed by depositing an oxide on the substrate 1002 where the fin structure F is formed, and etching back the oxide. Prior to etch back, the oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP). In the planarization process, the mask layer (1004/1006) on the top of the fin structure F may be removed. The fin structure F protrudes with respect to the top surface of the isolation layer 1009, and the protruding portion thereof may then serve as a fin of the device.

In this example, the top surface of isolation layer 1009 may be substantially flush with the top surface of well region 1002-1. However, the present disclosure is not limited thereto. For example, the top surface of isolation layer 1009 may be (slightly) above or (slightly) below the top surface of well region 1002-1.

In addition, in order to suppress punch-through, a punch-through stopper may be formed in the bottom of the fin structure F (particularly, a portion below the top surface of the isolation layer 1009). For example, the punch-through stopper may be formed by performing ion implantation in a direction substantially perpendicular to the substrate surface, the implanted ions being scattered into the bottom of the fin structure F by the isolation layer 1009. An anneal may be performed to activate the implanted ions.

After the fin structure F and the isolation layer 1009 are formed as described above, a device fabrication process such as gate stack formation, source/drain formation, or the like may be performed.

Specifically, as shown in fig. 4(a) and 4(b) (cross-sectional views along lines AA 'and BB', respectively), a sacrificial gate dielectric layer 1010 and a sacrificial gate conductor layer 1012 may be sequentially formed on the substrate, for example, by deposition. For example, the sacrificial gate dielectric layer 1010 comprises an oxide and has a thickness of about 1-5nm, and the sacrificial gate conductor layer 1012 comprises polysilicon or amorphous silicon and has a thickness of about 50-150 nm. The deposited sacrificial gate conductor layer 1012 may also be subjected to a planarization process such as CMP, if desired. Thereafter, a mask layer may be formed on the sacrificial gate conductor layer 1012, for example, by deposition. The mask layer may comprise a stack of an oxide layer 1014 having a thickness of about 3-5nm and a nitride layer 1016 having a thickness of about 50-150 nm. Over the mask layer, a photoresist 1018 may be formed. The photoresist 1018 is patterned, for example by photolithography, into a shape corresponding to the gate stack to be formed (see fig. 5(a), in this example, into three substantially parallel straight lines).

Then, as shown in fig. 5(a), 5(b) and 5(c) (fig. 5(a) is a top view, fig. 5(b) is a cross-sectional view taken along line AA 'in fig. 5(a), and fig. 5(c) is a cross-sectional view taken along line BB' in fig. 5 (a)), the nitride layer 1016, the oxide layer 1014, the sacrificial gate conductor layer 1012 and the sacrificial gate dielectric layer 1010 are selectively etched, for example, by RIE, using the photoresist 1018 as a mask. The RIE may stop on the isolation layer 1009. Thereafter, the photoresist 1018 may be removed. Thus, three stripe gate structures are formed. By "gate structure" is meant herein one or more layers of the (sacrificial) gate stack, or the (sacrificial) gate stack itself. For example, in the illustrated example, the gate structure may refer to the patterned sacrificial gate conductor layer 1012 and the sacrificial gate dielectric layer 1010 (i.e., the sacrificial gate stack itself).

In this example, the gate structures on the left and right sides will be used subsequently to form the device, while the gate structure in the middle is not really used to form the device, and may therefore be referred to as a "dummy" gate structure.

Subsequently, as shown in fig. 6(a cross-sectional view along line AA'), gate sidewalls 1020 may be formed on the sidewalls of the gate structure. Those skilled in the art know a variety of ways to form such sidewalls. For example, the spacers 1020 may be formed by depositing a layer of nitride substantially conformally on the structure shown in fig. 5(a), 5(b), and 5(c), and then RIE at an angle substantially perpendicular to the substrate surface. The width (dimension in the horizontal direction in the figure) of the side walls 1020 may be about 5-30 nm. Here, the mask layer on top of the gate structure is not removed. This is primarily to protect the grid structure in subsequent processing. In this example, since both nitride layer 1016 and sidewall spacers 1020 comprise nitride, they are shown as one in the figure.

Here, the case where one P-type device and one N-type device are formed is described. To this end, as shown in figure 7 (cross-sectional view along line AA'), regions of the N-type device (the right region in the figure) may be masked by a mask layer. For example, the mask layer may include an oxide layer 1022 and a nitride layer 1024 having a thickness of about 3-10 nm. The mask layer may extend to the top surface of the intermediate gate structure and expose a region of the P-type device (left region in the figure).

Although the case where two devices, one P-type device and one N-type device, are formed, is described herein, the present disclosure is not limited thereto. The techniques of this disclosure may also be applied to form more or fewer semiconductor devices of the same or different types.

Then, as shown in fig. 8 (cross-sectional view along line AA'), an additional semiconductor layer 1026 may be formed at least partially embedded in the fin structure F on opposite sides of the gate structure for a P-type device. In this example, the fin structure F is integral with the substrate 1002, and the semiconductor layer 1026 may even go into the substrate 1002. The semiconductor layer 1026 can comprise a material different from the substrate 1002, such as SiGe (e.g., having an atomic percent content of Ge of about 35-75%, and preferably, the atomic percent content of Ge can be graded) in order to apply a compressive stress to the channel region. Such an embedded semiconductor layer can be formed, for example, as follows: selective etching, such as RIE (which may enter the substrate 1002), is performed on the fin-shaped structure F using the sacrificial gate structure (in this example, the top surface is provided with a nitride layer) and the gate sidewall (in this example, nitride) as masks to form a trench; the trench is then filled (e.g., selectively epitaxially grown, and may then be etched back) with a semiconductor material such as SiGe. The masking layer on the top surface of the sacrificial gate conductor layer can prevent the sacrificial gate conductor layer from being damaged when selectively etching the fin structure F (in this example, the sacrificial gate conductor layer and the fin structure both comprise silicon material).

It is to be noted here that in the drawings, the top surface of the semiconductor layer 1026 is shown to be flush with the top surface of the fin structure F. However, the present disclosure is not limited thereto, and the top surface of the semiconductor layer 1026 may be higher or lower depending on the amount of etch-back, for example.

The semiconductor material may be doped in situ while growing, for example, P-type for a P-type device at a doping concentration of about 1E19-1E22cm^-3. This in-situ doped semiconductor layer 1026 may subsequently form source/drain regions of the semiconductor device. Thereafter, the mask layers 1022 and 1024 may be removed by selective etching such as RIE.

Likewise, the N-type devices on the other side may be similarly processed. For example, as shown in figure 9 (cross-sectional view along line AA'), regions of the P-type device may be masked by a mask layer. For example, the mask layer may include an oxide layer 1028 and a nitride layer 1030 having a thickness of about 3-10 nm. The mask layer may extend onto the top surface of the intermediate gate structure and expose regions of the N-type devices.

Then, as shown in fig. 10 (cross-sectional view along line AA'), an additional semiconductor layer 1032 may also be formed at least partially embedded in the fin structure F on opposite sides of the gate structure of the N-type device. In this example, the fin structure F is integral with the substrate 1002, and the semiconductor layer 1032 may even enter into the substrate 1002. Semiconductor layer 1032 may comprise a material different from that of substrate 1002, such as Si: c (e.g., about 0.32 atomic percent content of C) to apply a tensile stress to the channel region. Such an embedded semiconductor layer may be formed, for example, as described above. The semiconductor material may be doped in situ while it is being grown, for example, N-type for an N-type device. Such in-situ doped semiconductor layer 1032 may subsequently form source/drain regions of a semiconductor device. Thereafter, the mask layers 1030 and 1028 may be removed by selective etching such as RIE.

Although the example of forming epitaxially grown embedded source/drain regions is described above, the present disclosure is not limited thereto. For example, the source/drain regions may be formed by ion implantation directly into the fin F.

Thereafter, gate replacement may be performed.

For example, as shown in FIG. 11 (cross-sectional view along line AA'), an inter-level dielectric layer 1036 may be formed, e.g., deposited, on the substrate. The interlevel dielectric layer 1036 may comprise an oxide of sufficient thickness to fill the spaces between the gate structures. Alternatively, an etch stop liner 1034 may be formed, for example, first. The etch stop liner 1034 may comprise a nitride with a thickness of about 5-20 nm. In this example, etch stop liner 1034 is shown as integral with gate sidewall spacers 1020, and nitride layer 1016 in the mask, since they all comprise nitride. Additionally, for ease of illustration, the gate sidewall spacers 1020 and the increase in thickness of the nitride layer 1016 in the mask due to the deposition of the etch stop liner 1034 are not shown.

Thereafter, as shown in fig. 12 (cross-sectional view along line AA'), a planarization process such as CMP may be performed until the sacrificial gate structure, specifically, the sacrificial gate conductor layer 1012, is exposed. The sacrificial gate conductor layer 1012 may be removed by selective etching, such as wet etching with TMAH solution; and further selectively etching, such as wet etching with HF solution or BOE solution, to remove the sacrificial gate dielectric layer 1010. Thus, a trench is formed inside the gate sidewall 1020. Then, as shown in fig. 13 (cross-sectional view along line AA'), a replacement gate stack may be formed (e.g., deposited and then planarized) within the trench. Specifically, the replacement gate stack may include a replacement gate dielectric layer 1038 and a replacement gate conductor layer 1040. The replacement gate dielectric layer 1038 may comprise a high-K gate dielectric material such as HfO₂And approximately 2-4nm thick, the replacement gate conductor layer 1040 may comprise a metal gate conductor, such as one of TiN, TiAl, TaN, TiC, or a combination thereof. The replacement gate conductor layer 1040 may include materials of different work functions for N-type devices and P-type devices. In addition, in the formationAn interfacial layer (e.g., oxide) having a thickness of about 0.3-1.5nm may also be formed prior to the replacement gate stack.

According to an advantageous example of the present disclosure, the replacement gate conductor layer 1040 may be recessed to be filled with a dielectric material on top thereof. For example, as shown in fig. 14 (cross-sectional view along line AA'), a portion of the replacement gate conductor layer 1040 may be removed by selective etching such as RIE, and then a dielectric layer 1042 such as nitride may be filled (e.g., deposited and then planarized) into the space inside the gate sidewall 1020 at the top thereof resulting from the removal of the portion.

Then, as shown in fig. 15 (cross-sectional view along line AA'), P-type device regions and N-type device regions may be masked by a mask layer 1044, such as photoresist, for example, the mask layer 1044 may extend over the dummy gate sidewalls but expose the dummy gate stack regions. Dielectric layer 1042, replacement gate conductor layer 1040, replacement gate dielectric layer 1038, and fin structure F may then be selectively removed in sequence by a selective etch, such as RIE, to form trench T, as shown in fig. 16 (cross-sectional view along line AA'). In this example, replacement gate dielectric layer 1038 on the sidewalls of trench T is not removed, but this portion of replacement gate dielectric layer 1038 may also be removed. Thereafter, the mask layer 1044 may be removed.

The trench T may be self-aligned to the space defined by the gate spacers 1020 due to the selective etch with respect to the gate spacers 1020 (although in this example, a portion of the top thereof may be removed during the RIE of the nitride dielectric layer 1042). Specifically, the sidewalls of trench T extend substantially along the inner walls of gate sidewall spacers 1020 (in this example, inwardly receding substantially replaces the thickness of gate dielectric layer 1038, and is almost negligible).

In order to avoid influencing the topography of the upper sidewalls of the trench T when the trench T is further enlarged (in particular widened) below, a suitable dielectric material, for example nitride or SiC, may be formed on the sidewalls of the trench T. For example, as shown in fig. 17 (cross-sectional view along line AA'), a dielectric layer 1046 having a thickness of about 2-7nm may be formed on the sidewalls of the trench T by a sidewall formation process.

Then, as shown in fig. 18 (a cross-sectional view along line AA'), the groove may be further deepened by the bottom wall of the groove T. For example, RIE may continue to be performed on the substrate 1002 through the trench T, so that the trench T deepens. Then, the substrate 1002 may be further subjected to isotropic etching such as wet etching by the deepened trench T, so that the lower portion of the trench T is widened. The upper part of the trench T is not widened due to the presence of the dielectric layer 1046 on the sidewalls. By such a dielectric layer 1046, the insulating electrical properties, e.g. electrical breakdown, low-k, etc., may be improved.

Alternatively, after forming the dielectric layer 1046, the substrate 1002 may be isotropically etched directly through the bottom of the trench to simultaneously widen and deepen the trench T, rather than deepening and then widening as described above.

By such a deepened, widened trench, it is advantageous to improve isolation between devices, for example, to reduce leakage current or short circuits between devices.

Next, as shown in fig. 19 (a cross-sectional view along line AA'), a dielectric material such as oxide may be filled (e.g., deposited and then planarized) into the trench T to form an isolation 1048 (which may be referred to as a "second isolation"). Since the trench T is self-aligned to the space defined by the gate sidewall 1020, the isolation portion 1048 formed in the trench T is also self-aligned to the space defined by the gate sidewall 1020.

In this example, since the upper portion of the trench T is narrow and the lower portion is wide, the isolation portion 1048 may be formed along the inner wall of the trench T at the lower portion of the trench T and have a hollow structure, forming an air gap. Such air gaps contribute to low k.

By such a trench T and the isolation 1048 formed in the trench T, the fin structure F is divided into two portions electrically isolated from each other, serving as fins of the N-type device and the P-type device, respectively.

Of course, the present disclosure is not limited thereto, but the lower portion of the trench T may be completely filled. For example, as shown in fig. 20 (a sectional view along line AA'), after the hollow structure shown in fig. 19 is formed, the isolation portion 1048 may be selectively etched, such as RIE. The RIE may be performed in a direction substantially perpendicular to the substrate surface such that the isolation 1048 on the upper portion of the trench may be removed, while the isolation 1048 on the lower sidewall of the trench may remain (shown as 1048'). In this example, since the inter-layer dielectric layer 1036 includes an oxide like the isolation portions 1048, the inter-layer dielectric layer 1036 may also be removed during RIE. The trench may then continue to be filled with a dielectric material, such as an oxide. During the filling process, a hollow structure as shown in fig. 19 may still occur. At this time, the operation described in conjunction with fig. 20 may be performed again. This filling and etching step may be repeated until the trench T is completely filled with dielectric. The filled dielectric may be subjected to a planarization process such as CMP (dielectric layer 1042, which may stop on top of the gate conductor layer) so that the space between the gate sidewalls is also filled, and an interlayer dielectric layer 1050 is retrieved, as shown in fig. 21 (cross-sectional view along line AA').

After the formation of the devices and self-aligned spacers as described above, other peripheral components may also be formed. For example, as shown in fig. 22, source/drain contacts 1052 may be formed. Such source/drain contacts 1052 may be formed by etching contact holes and then filling with a conductive material such as a metal (e.g., Cu or W). A diffusion barrier layer such as TiN may also be formed on the sidewalls of the contact holes prior to filling with the conductive material.

As shown in fig. 22, the semiconductor device according to this embodiment of the present disclosure may include a P-type device and an N-type device. Each device may include a corresponding gate stack (including a replacement gate dielectric layer 1038 and a replacement gate conductor layer 1040) and gate sidewall spacers 1020 on sidewalls of the gate stack. Between the two devices, a dummy gate sidewall spacer may be formed. As described above, the isolation portion is self-aligned to the space defined by the dummy gate sidewall. Due to the self-alignment, in top view, the lower part of the isolation part is symmetrical with respect to the longitudinal extension line of the space defined by the dummy gate sidewall. The partition has a configuration that is small at the top and large at the bottom. Since the isolation portions are formed by the same trench, they have the same longitudinal axis, i.e., the lower and upper portions of the second isolation portion are centrally aligned in the vertical direction.

According to other embodiments, the gate sidewall spacers 1020 (including the dummy gate sidewall spacers) may be partially or even completely removed due to subsequent processes. In the above embodiment, the dielectric thin layer is formed only on the upper sidewalls of the trenches T. According to other embodiments, after widening and deepening the trench, a thin dielectric layer may be further formed along the inner wall of the trench.

Fig. 23-32 are schematic diagrams illustrating a middle-of-the-flow staging of a process for fabricating a semiconductor device according to another embodiment of the present disclosure. Hereinafter, differences between this embodiment and the above-described embodiment will be mainly described.

As shown in fig. 23, a substrate 1002a may be provided. For the substrate 1002a, the above description of the substrate 1002 can be referred to, and the description is omitted here.

On the substrate 1002a, a first semiconductor layer 1003 and a second semiconductor layer 1002b may be provided, for example, by epitaxial growth. Adjacent layers of the substrate 1002a, the first semiconductor layer 1003, and the second semiconductor layer 1002b may have etch selectivity with respect to each other, e.g., include different semiconductor materials. For example, where the substrate 1002a is a bulk silicon substrate, the first semiconductor layer 1003 may comprise SiGe (e.g., about 10-30 atomic percent Ge) having a thickness of about 10-50 nm; the second semiconductor layer 1002b may include Si to a thickness of about 10-100 nm.

Similarly, on the second semiconductor layer 1002b, a hard mask layer, such as an oxide layer 1004 and a nitride layer 1006, may be formed. For this, reference may be made to the above description of the oxide layer 1004 and the nitride layer 1006, which are not described herein again.

This may then be done as described above in connection with fig. 1(a) -10, and will not be described again here. With respect to the spatial positional relationship, the substrate 1002a may refer to a portion of the above substrate 1002 located below the well region 1002-1, the first semiconductor layer 1003 may refer to the well region 1002-1, and the second semiconductor layer 1002b may refer to a portion of the above substrate 1002 located above the well region 1002-1.

According to another embodiment of the present disclosure, a stop layer may be formed first when forming the embedded source/drain. For example, as shown in figure 24 (cross-sectional view along line AA '), the stop layer 1026' may be grown prior to the semiconductor layer 1026 when processing a P-type device. For the semiconductor layer 1026, the above description can be referred to, and details thereof are not repeated here. The stop layer 1026' may comprise a semiconductor material having an etch selectivity relative to the first semiconductor layer 1003, such as SiGe (e.g., about 10 atomic percent Ge, different from the atomic percent Ge content of the first semiconductor layer 1003 to provide etch selectivity), having a thickness of about 1-3 nm. The stop layer 1026' may also be doped in-situ to form a portion of the source/drain regions.

For N-type devices, processing may be performed similarly. That is, before the semiconductor layer 1032 is formed, a stopper layer (not shown) may be formed.

Hereinafter, a case where the stop layer is not formed will be described as an example.

As shown in fig. 25 (cross-sectional view along line AA '), an inter-level dielectric layer 1036' may be formed, for example, on the substrate. Here, the interlayer dielectric layer 1036' may include SiC in order to provide etch selectivity in a subsequent process. For this, reference may be made to the above description in connection with fig. 11 and 12, which are not described in detail here.

According to an advantageous example, in order to reduce punch-through, an isolation layer may be formed through the fin underneath.

For example, as shown in fig. 26(a) and 26(b) (cross-sectional views along lines AA 'and BB', respectively), the sacrificial gate structure may be removed to expose the space inside the gate sidewall. The underlying STI isolation layer 1009 is exposed due to the removal of the sacrificial gate structure. If the top surface of the STI isolation layer 1009 is not lower than the top surface of the first semiconductor layer 1003 and thus shields the first semiconductor layer 1003, the STI isolation layer 1009 may be subjected to an etch back such as RIE so as to expose the first semiconductor layer 1003 (particularly to expose at least a part of the side wall thereof), as shown in fig. 26 (b).

Due to the exposure of the first semiconductor layer 1003, at least a portion of the first semiconductor layer 1003 may be removed to form a void below the second semiconductor layer 1002 b. For example, as shown in fig. 27(a) and 27(b) (cross-sectional views along the AA 'line and the BB' line, respectively), the first semiconductor layer 1003 may be selectively etched. In order to be able to control the amount of etching well, in particular in the direction of longitudinal extension of the fin-shaped structure F, Atomic Layer Etching (ALE) may be used. Since the first semiconductor layer 1003 is selectively etched through the space inside the gate sidewall, the resulting voids may be self-aligned to the space inside the gate sidewall, i.e., they are center-aligned in the vertical direction. In addition, the top surfaces of these voids correspond to the top surface of the first semiconductor layer 1003 (or, the bottom surface of the second semiconductor layer 1002 b), and are thus coplanar. This can reduce process fluctuations.

According to another embodiment, when selectively etching the first semiconductor layer 1003, the etching may stop at the semiconductor layers 1026, 1032 at the source/drain regions in the lateral direction (in the case of forming the stop layer 1026 ', at the stop layer 1026 '), as shown in fig. 28 (a cross-sectional view along line AA ').

Subsequently, as shown in fig. 29(a) and 29(b) (sectional views along the AA 'line and the BB' line, respectively), the voids may be filled (e.g., deposited and then etched back) with a dielectric material such as an oxide to form an isolation layer 2001. As shown in fig. 29(b), the isolation layer 2001 extends under the second semiconductor layer 1002b, and may extend to the source/drain region positions on both sides as described above. Since the voids are self-aligned to the spaces inside the gate stack, the spacers 2001 are self-aligned to the spaces inside the gate stack, i.e., they are center-aligned in the vertical direction. The interface between the STI isolation layer 1009 and the isolation layer 2001 is shown here in dashed lines, since both are oxides.

In this example, the top surface of the STI isolation layer 1009 may be lower than the bottom surface of the second semiconductor layer 1002b after etch-back. However, the present disclosure is not limited thereto. For example, the top surface of the STI isolation layer 1009 may be (slightly) higher or (slightly) lower than the bottom surface of the second semiconductor layer 1002b according to the amount of etch-back.

Here, since the interlayer dielectric layer 1036' includes SiC, it is not removed when the oxide is etched back. Thus, space is left only inside the gate sidewall for subsequent formation of the gate structure.

Thereafter, the processing may be performed as described above in connection with fig. 13 to 15. For example, a gate structure is formed, the gate conductor layer is recessed and filled with a dielectric layer 1042 (which may be SiC in this example), and the device region is masked to expose the dummy gate stack region.

As shown in fig. 30 (cross-sectional view along line AA'), dielectric layer 1042, replacement gate conductor layer 1040, replacement gate dielectric layer 1038, and fin structure F may be selectively removed in sequence by a selective etch, such as RIE, to form trench T. The etch may stop at the underlying spacers 1009, 2001. As described above, the trench T may be self-aligned to the space defined by the gate sidewall 1020.

Then, as shown in fig. 31 (a cross-sectional view along line AA'), the trench T may be filled (e.g., deposited and then planarized) with a dielectric material such as oxide to form an isolation 2003. Similarly, the isolation portion 2003 may be self-aligned to the space defined by the gate sidewall 1020.

According to another embodiment, as shown in fig. 32 (cross-sectional view along line AA'), before filling the dielectric, the isolation layer 2001 may be removed, and a dielectric layer 2005 may be formed on the inner wall of the trench, and then the dielectric may be refilled. Such a dielectric layer 2005 can help improve insulating electrical properties such as electrical breakdown, low-k and protection devices, etc.

As shown in fig. 31 and 32, the semiconductor device may include a P-type device and an N-type device, similar to the above-described embodiments. Each device may include a corresponding gate stack (including a replacement gate dielectric layer 1038 and a replacement gate conductor layer 1040) and gate sidewall spacers 1020 on sidewalls of the gate stack. Between the two devices, a dummy gate sidewall spacer may be formed. As described above, the spacers 1021, 1023 are self-aligned to the space defined by the dummy gate sidewall.

The isolation portions 2001 and 2003 constitute isolation between devices (may be referred to as "second isolation portions"). Likewise, in the cross sections of fig. 31 and 32, the lower spacer portion 2001 is enlarged relative to the upper spacer portion 2003. By such enlargement, the spacer 2001 may form a stepped portion with respect to the spacer 2003, and such a stepped portion may be coplanar with the top surface of the first semiconductor layer 1003 or the bottom surface of the second semiconductor layer 1002 b.

In addition, the semiconductor device may further include an isolation layer 2001 formed under the fin structure F in the P type device and/or N type device region. As described above, this insulating layer 2001 extends under the fin structure F, corresponding to increased electrical isolation under the channel region of the device. Thus, advantages similar to those of the SOI structure, such as reduction of leakage current, can be achieved. In another aspect, the isolation layer 1003 may not extend below the source/drain regions, such that at least a portion of the source/drain regions interface with the bulk substrate, and thus some of the disadvantages of SOI structures, such as self-heating effects, may be avoided.

In accordance with other embodiments, isolation layer 2001 may not be formed in P-type device and/or N-type device regions. This may be achieved, for example, by masking the device regions during the process of forming the isolation layer 2001.

Although the gate last process is used in the above embodiment, the present disclosure is not limited thereto. The techniques of the present disclosure may also be applied to gate-first processes.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.