阅读说明：本技术 基于不定形ZrOx的负电容晶体管 (Based on amorphous ZrOxNegative capacitance transistor of ) 是由 刘艳 张思清 刘欢 于 2021-01-04 设计创作，主要内容包括：本发明公开了基于不定形ZrO-x的负电容晶体管,包括：顶部栅极层、类铁电栅介质层、源漏电极层和N型Ge平台。其中顶部栅极层、类铁电栅介质层、源漏电极层在N型Ge平台上依次分布,其中顶部栅极采用TaN材料、类铁电栅介质层采用不定形ZrO-x材料、源漏电极层采用金属B和金属Ni材料。基于不定形ZrO-x的负电容晶体管在1V栅压下实现了45.06mV/decade的亚阈值摆幅和小于60mV的回滞。不定形ZrO-x对器件铁电性能的影响可以用氧空位偶极子解释。该设计有助于推动未来低功耗晶体管的发展。(The invention discloses a method for preparing amorphous ZrO based ceramic x The negative capacitance transistor of (1), comprising: the top grid layer, the ferroelectric-like grid dielectric layer, the source drain electrode layer and the N-type Ge platform. Wherein the top gate layer, the quasi-ferroelectric gate dielectric layer and the source/drain electrode layer are sequentially distributed on the N-type Ge platform, the top gate is made of TaN material, and the quasi-ferroelectric gate dielectric layer is made of amorphous ZrO x The material and the source drain electrode layer are made of metal B and metal Ni. Based on amorphous ZrO x The negative capacitance transistor realizes the subthreshold swing of 45.06mV/decade and the hysteresis of less than 60mV under the grid voltage of 1V. Amorphous ZrO x The effect on the ferroelectric properties of the device can be explained by the oxygen vacancy dipole. The design is favorable for promoting the future low workThe development of depletion transistors.)

1. Based on amorphous ZrO_xThe negative capacitance transistor of (2), characterized in that: the negative capacitance transistor is a transistor having amorphous ZrO_xThe Ge channel negative capacitance transistor of the gate dielectric comprises a ferroelectric-like gate dielectric layer (1), a top gate layer (2), a source drain electrode layer (3) and an N-type Ge platform (4), wherein the ferroelectric-like gate dielectric layer (1), the top gate layer (2) and the source drain electrode layer (3) are sequentially distributed on the N-type Ge platform (4) to form a negative capacitance transistor structure; the ferroelectric-like gate dielectric layer (1) is made of TaN material, and the top gate layer (2) is made of amorphous materialForm ZrO_xThe material, the source drain electrode layer (3) adopts metal B⁺And the N-type Ge platform (4) is made of N-Ge (001) material.

2. Amorphous ZrO-based ceramic composition according to claim 1_xThe negative capacitance transistor of (2), characterized in that: the manufacturing method of the negative capacitance transistor comprises the following steps:

1) amorphous ZrO is deposited on the N-type Ge platform (4) by an atomic layer material deposition process_xForming a ferroelectric-like gate dielectric layer (1) by using the material;

2) depositing TaN material on the quasi-ferroelectric gate dielectric layer (1) by using a reactive sputtering process to form a top gate layer (2);

3) depositing metal B on the ferroelectric-like gate dielectric layer (1) by using an electron beam lithography process and an electron beam evaporation process⁺And a metal Ni material, forming a source/drain electrode layer (3).

3. Amorphous ZrO-based ceramic electronic article according to claim 2_xThe negative capacitance transistor of (2), characterized in that: the thickness of the ferroelectric-like gate dielectric layer (1) is 4.2 nanometers.

4. Amorphous ZrO-based ceramic electronic article according to claim 2_xThe negative capacitance transistor of (2), characterized in that: the thickness of the TaN material is 50 nanometers.

5. Amorphous ZrO-based ceramic electronic article according to claim 2_xThe negative capacitance transistor of (2), characterized in that: the thickness of the source drain electrode layer is 30 nanometers.

6. Amorphous ZrO-based ceramic composition according to claim 1_xThe negative capacitance transistor of (2), characterized in that: based on amorphous ZrO_xThe negative capacitance transistor can realize the subthreshold swing of 45.06mV/decade and the hysteresis of less than 60mV under the grid voltage of 1V.

Technical Field

The invention belongs to the technical field of electronic devices, particularly relates to a negative capacitance transistor, and particularly relates to a transistor based on amorphous ZrO_xA negative capacitance transistor of (1).

Background

Integrated Circuit (IC) technology has entered "post-mole" with the continued scaling down of Complementary Metal Oxide Semiconductor (CMOS) device dimensions. Integrated circuit industries and techniquesThe driving force of (2) is gradually becoming to reduce power consumption rather than transistor miniaturization. However, boltzmann storm of transistors, exceeding the sub-threshold swing of 60mV/decade, has limited energy/power efficiency. In recent years, many novel devices have been proposed that can achieve sub-threshold swings of less than 60mV/decade, including impact ionization transistors, tunneling transistors, and negative capacitance transistors. Negative-capacitance transistors with Ferroelectric (FE) thin films have been considered as the most attractive choice among these emerging devices due to simple structure, steep subthreshold swing and improved drive current. The NCFET reported so far mainly comprises PbZrTiO₃(PZT), P (VDF-TrFE) and HfZrO_x(HZO). However, the development of these new technology nodes is limited by the higher process temperatures and the non-ideal gate leakage current along grain boundaries. Recently, researchers have studied amorphous Al generated from voltage modulated oxygen vacancy dipoles₂O₃And ZrO_xFerroelectricity in the thin film. Amorphous ferroelectric thin films have significant advantages in terms of reduced process temperature and reduced leakage current compared to crystalline ferroelectric thin films. Accordingly, there has been much research on the application of ferroelectric transistors having amorphous ferroelectric thin films to nonvolatile memories and analog synapses. However, there has not been based on amorphous ZrO_xSystem research of the negative capacitance transistor.

Disclosure of Invention

It is an object of the present invention to provide a material based on amorphous ZrO_xA negative capacitance transistor of (1).

Another object of the present invention is to provide a method for producing a ceramic body based on amorphous ZrO_xA method of manufacturing a negative capacitance transistor.

It is a further object of the present invention to provide amorphous ZrO based ceramics_xThe physical mechanism of the negative capacitance transistor.

First, technical principle

The invention provides a ZrO layer with 4.2nm ZrO_xA Ge NCFET for the ferroelectric dielectric layer. We have experimentally observed ZrO_xSteep subthreshold swing below 60mV/decade for (5nm) NCFETs, which may be attributed to ZrO_xNC effect of the ferroelectric layer. Then, we analyzed Ge/ZrO_xThe relationship between the polarization P of the/TaN capacitor and the applied voltage V. Ge/ZrO_xThe ferroelectric-like behavior of/TaN capacitors is caused by voltage modulated oxygen vacancy dipoles. Furthermore, we convert Al₂O₃/HfO₂NCFET and ZrO_xImproved I in NCFETs_DSAnd I_GThe sudden drop in (c) is due to NC effects. We have also observed Al₂O₃/HfO₂NCFET and ZrO_xNDR phenomenon in NCFETs. In addition, we further analyzed the interfacial dipole induced Al₂O₃/HfO₂Physical mechanism of NCFET NC effect reduction. ZrO (ZrO)_xThe NCFET has a steep slope of less than 60mV/decade, improved drain voltage and low operating voltage, and is suitable for the development of low-power consumption negative capacitance transistors in the post-Mole age.

Second, device structure

Based on amorphous ZrO_xThe negative capacitance transistor of (2), characterized in that: the negative capacitance transistor is a transistor having amorphous ZrO_xThe Ge channel negative capacitance transistor of the gate dielectric comprises a ferroelectric-like gate dielectric layer, a top gate layer, a source drain electrode layer and an N-type Ge platform, wherein the ferroelectric-like gate dielectric layer, the top gate layer and the source drain electrode layer are sequentially distributed on the N-type Ge platform to form a negative capacitance transistor structure; the ferroelectric-like gate dielectric layer is made of TaN material, and the top gate layer is made of amorphous ZrO_xThe source-drain electrode layer is made of metal B⁺And the N-type Ge platform is made of an N-Ge (001) material.

The method for manufacturing the negative capacitance transistor comprises the following steps:

1) amorphous ZrO is deposited on the N-type Ge platform (4) by an atomic layer material deposition process_xForming a ferroelectric-like gate dielectric layer (1) by using the material;

2) depositing TaN material on the quasi-ferroelectric gate dielectric layer (1) by using a reactive sputtering process to form a top gate layer (2);

3) depositing metal B on the ferroelectric-like gate dielectric layer (1) by using an electron beam lithography process and an electron beam evaporation process⁺And a metal Ni material, forming a source/drain electrode layer (3).

The invention has the following advantages:

the invention proposes that the content is within +/-1V V_GSZrO with sub-threshold swing (SS) in the range of 45.06mV/decade_xNCFET, which will bring new ideas for future low operating voltage NCFET design. Ge/ZrO_xThe ferroelectric behavior of/TaN capacitors is believed to be caused by oxygen vacancy dipoles. Amorphous HfO₂And ZrO_xThe NC effect of the thin film device can be reduced by a sudden drop in gate leakage current, a Negative Differential Resistance (NDR) phenomenon, I_DSIs demonstrated by a subthreshold swing below 60 mV/decade. And no ZrO_xCompared with a control device based on 5nm ZrO_xHas a clockwise hysteresis of 0.24V and a subthreshold swing of less than 60mV/decade, I_DSThe enhancement is 12%. And ZrO_xCompared with NCFET, Al₂O₃/HfO₂Suppressed NC effect and Al in NCFET₂O₃/HfO₂The negative interface dipole at the interface causes a partial switching of the oxygen-vacancy dipole in the forward scan.

Drawings

FIG. 1 shows Al produced in (a)₂O₃/HfO₂Schematic diagram of NCFET and (b) HRTEM image; (c) produced ZrO_xSchematic representation of NCFET and (d) HRTEM image.

FIG. 2 is Al₂O₃/5nm HfO₂NCFET and 4.2nm ZrO_xKey process steps for NCFETs.

FIG. 3 shows (a) the range of different scanning voltages V and (b) the 4.2nm ZrO at different measurement frequencies_xP-V curve of the capacitor.

FIG. 4 is (a) when V_DS-0.5V and V_DSwhen-0.05V, measured Al₂O₃/5nm ZrO_xI of NCFET_DS-V_GSA curve; (b) ZrO (ZrO)_xI of NCFET and control MOSFET_DS-V_DSA curve; (c) when V is_DS-0.5V and V_DSWhen the grain size is-0.05V, 5nm ZrO_xI of NCFET_G-V_GSCurve line.

FIG. 5 is a graph showing (a) when V_DS-0.5V and V_DSWhen ═ 0.05V, measured5nm ZrO_xI of NCFET_DS-V_GSA curve; (b) ZrO (ZrO)_xI of NCFET and control MOSFET_DS-V_DSA curve; (c) when V is_DS-0.5V and V_DSWhen the grain size is-0.05V, 5nm ZrO_xI of NCFET_G-V_GSCurve line.

FIG. 6 shows (a) Al₂O₃/5nm HfO₂NCFET and (b)5nm ZrO_xSS-I of NCFET_DSCurve line.

Detailed Description

In order to make the objects and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to FIG. 1, the amorphous ZrO-based ceramic composition of the present invention_xThe negative capacitance transistor of (1) includes: the ferroelectric-like gate structure comprises a ferroelectric-like gate dielectric layer 1, a top gate layer 2, a source drain electrode layer 3 and an N-type Ge platform 4. The ferroelectric-like gate dielectric layer 1, the top gate layer 2 and the source drain electrode layer 3 are sequentially distributed on the N-type Ge platform 4, and the ferroelectric-like gate structure is characterized in that: the ferroelectric-like gate dielectric layer is made of TaN material, and the top gate layer is made of amorphous ZrO_xThe source-drain electrode layer is made of metal B⁺And the N-type Ge platform is made of an N-Ge (001) material.

The invention is based on amorphous ZrO_xThe following example is given for the method of the negative capacitance transistor of (1).

Example (b): making based on amorphous ZrO_xA negative capacitance transistor of (1).

Referring to fig. 2, the implementation steps of this example are as follows:

step 1: growing a ferroelectric-like gate dielectric layer ZrO_x

Amorphous ZrO is deposited on the N-type Ge platform (4) by an atomic layer material deposition process_xForming a ferroelectric-like gate dielectric layer (1) by using the material; the thickness of the ferroelectric-like gate dielectric layer is 4.2 nanometers.

Step 2: growing top gate layer TaN

Depositing TaN material on the quasi-ferroelectric gate dielectric layer (1) by using a reactive sputtering process to form a top gate layer (2); the thickness of the TaN material was 50 nm.

And step 3: growing a source drain electrode layer B⁺/Ni

Depositing metal B on the ferroelectric-like gate dielectric layer (1) by using an electron beam lithography process and an electron beam evaporation process⁺And a metal Ni material to form a source drain electrode layer (3); the thickness of the source drain electrode layer is 30 nanometers.

The above description is only one preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

FIGS. 1(a) and (c) show Al produced₂O₃/HfO₂NCFET and ZrO_xSchematic diagram of NCFET. The High Resolution Transmission Electron Microscope (HRTEM) image in FIG. 1(b) depicts a sample with Al₂O₃Amorphous HfO on Ge (001) of interfacial layer₂(5nm) film. The HRTEM image in FIG. 1(d) depicts amorphous ZrO on Ge (001)_x(4.2nm) film. In FIG. 2, the use of ZrO is shown_xAnd Al₂O₃/HfO₂Key process steps for NCFETs. Al was grown on n-Ge (001) substrates by Atomic Layer Deposition (ALD) at 300 deg.C₂O₃Amorphous HfO₂(5nm) and amorphous ZrO_x(4.2nm) different gate dielectric layers. TMA, TDMAHf, TDMAZr and H₂O is used as a precursor for Al, Hf, Zr and O, respectively. The pulse times for the Al, Hf and Zr precursors were 1.6s and 8s, respectively. The purge times for the Al, Hf and Zr precursors were 0.2s and 8s, respectively. The TaN top gate electrode was then deposited on the HfO by reactive sputtering₂Or ZrO_xOn the surface. The source/drain (S/D) regions are defined by photolithography and dry etching. Thereafter, boron (B) is deposited in the source/drain (S/D) region⁺) And nickel (Ni). Finally, at 10⁸A Rapid Thermal Anneal (RTA) was performed at 350 deg.C for 30 seconds in a Pa nitrogen atmosphere.

Results and discussion

FIG. 3(a) shows Ge/ZrO at 3.3kHz_xP-V of/TaN capacitorCurve line. Gate length (L) of capacitor_G) And 8 μm. We can observe that, over a large voltage sweep range, Ge/ZrO_xResidual polarization P of/TaN capacitor_rCan be enhanced. FIG. 3(a) shows amorphous ZrO_xIs believed to originate from voltage-driven oxygen-vacancy dipoles. FIG. 3(b) shows Ge/ZrO at different frequencies from 200Hz to 10kHz_xP-V curves for/TaN capacitors. We can see that ZrO is amorphous at all frequencies_xThe ferroelectric properties of (2) are stable. However, amorphous ZrO_xResidual polarization strength P of_rDecreases as the frequency increases. This phenomenon can be explained by incomplete dipole flipping at high measurement frequencies. Amorphous ZrO with increasing measuring frequency_xThe time for the direction of the middle electric field to turn is reduced. Therefore, the inversion of part of the oxygen-vacancy dipoles is incomplete, thereby lowering the remanent polarization P_r。

FIG. 4(a) shows when V_DSat-0.05V and-0.5V, Al₂O₃/HfO₂I of NCFET_DS-V_GSCurve line. L of two devices_GIs 3 μm. The hysteresis values are 0.14V (V) respectively_DS＝-0.05V，I_ds1 nA/. mu.m) and 0.08V (V)_DS＝-0.5V，I_ds1 nA/. mu.m). The clockwise hysteresis is due to the migration of oxygen vacancies and the corresponding negative charges. At positive (negative) V_GSWith oxygen vacancy dipole at Ge/Al₂O₃Accumulation (depletion) in the interface. Therefore, the threshold voltage (V)_TH) Increasing (decreasing) under a forward (reverse) scan of the gate voltage. FIG. 4(b) shows a comparison of Al₂O₃/HfO₂Output curves for NCFET and control FET. At | V_GS-V_TH|＝|V_DSWhen | ═ 0.8V, Al₂O₃/HfO₂The saturation current of the NCFET exceeded 26 μ a/μm and increased by 23% compared to the control FET. The enhanced current is obtained by inverting the charge intensity (Q) in the reverse polarization electric field_inv) And amplification of the surface potential. In addition to the enhanced current, the apparent NDR phenomenon evidences amorphous HfO₂NC effect of (2). The NDR effect is due to V_DSIncrease of (2), drain and trenchIncomplete oxygen vacancy dipole switching due to coupling of the traces. FIG. 4(c) compares when V_DS5nm Al at-0.05V and-0.5V₂O₃/HfO₂Gate leakage current I of NCFET_G-V_GSCurve line. I occurring only during the reverse scan_GSudden drop indicates amorphous HfO₂Reduced voltage and increased surface potential. The non-NC effect during the forward scanning is due to the amorphous HfO₂Due to partial flipping of the mid-oxygen vacancy dipole. Al (Al)₂O₃And HfO₂The different oxygen atom-containing capabilities between the layers may result in Al₂O₃/HfO₂Redistribution of oxygen vacancies and negative interface dipoles at the interface. Amorphous HfO due to the presence of negative interface dipole₂It is difficult to achieve a complete polarization flip in the forward scan (NC effect).

FIG. 5(a) shows when V_DSZrO at-0.05V and-0.5V_xTransfer curve of NCFET. L of two devices_GAnd was 4 μm. The clockwise hysteresis is 0.24V (V) respectively_DS＝-0.05V，I_ds1 nA/. mu.m) and 0.14V (V)_DS＝-0.5V，I_DS1 nA/. mu.m). FIG. 5(b) compares ZrO_xOutput curves for NCFET and control FET. When | V_GS-V_TH|＝|V_DSWhen 1V, ZrO_xThe saturation current of the NCFET exceeds 30 μ A/μm and rises by 12% compared to the control FET. The enhanced current enhancement phenomenon and the more obvious NDR phenomenon are shown to be compatible with 5nm HfO₂Film phase ratio amorphous ZrO_xThe NC effect (5nm) is enhanced. FIG. 5(c) compares when V_DSZrO 5nm at-0.05V and-0.5V_xGate leakage current I of NCFET_G-V_GSCurve line. Al only occurring during reverse scanning as shown in FIG. 4(c)₂O₃/HfO₂I of NCFET_GSudden drop compared to I in FIG. 5(c) occurring during both forward and reverse scans_GThe sudden drop also proves amorphous ZrO_xIn the enhanced NC effect.

FIGS. 6(a) and (b) show when V_DSAl at-0.05V and-0.5V₂O₃/HfO₂And ZrO_xSS-I of NCFET_DSCurve line. When V is shown in FIG. 6(b)_DSat-0.05V and-0.5V, at V_GSSub-threshold swing (SS) of less than 60mV/decade can be achieved during both forward and reverse scans. When V is_DSat-0.05V, the SS reached 745.1mV/dec for the forward direction and 55.2mV/dec for the reverse direction. When V is_DSat-0.5V, the SS reached 51.16mV/dec for the forward direction and 46.52mV/dec for the reverse direction. Due to Al₂O₃/HfO₂And ZrO_xThe ability to scavenge is different, therefore in Al₂O₃/HfO₂Partial dipole switching is induced in NCFETs. Thus, 5nm ZrO_xThe NCFET achieves a subthreshold swing of less than 60mV/decade and a more pronounced NC effect.

Conclusion

We report ZrO with sub-threshold swing less than 60mV/decade, low operating voltage of 1V, and hysteresis less than 60mV_xA negative capacitance transistor. We have explained amorphous ZrO by oxygen vacancy dipole inversion_xThe ferroelectric properties of (2). Compared to the control FET, Al₂O₃/HfO₂NCFET and ZrO_xNCFET obtains improved I_DSAnd NDR phenomena. Al (Al)₂O₃/HfO₂The suppressed NC effect in NCFETs can be attributed to Al₂O₃/HfO₂The partial dipoles at the interface flip. ZrO with steep subthreshold swing below 60mV/decade, improved drain voltage and low operating voltage_xThe NCFET provides a new approach for the design of the low-power consumption NCFET in the future.