阅读说明：本技术 基于复合介质栅双晶体管光敏探测器的钳位电路 (Clamping circuit based on composite dielectric gate double-transistor photosensitive detector ) 是由 马浩文 王凯 沈凡翔 王子豪 李张南 顾郅扬 胡心怡 柴智 陈辉 常峻淞 李龙飞 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种基于复合介质栅双晶体管光敏探测器的钳位电路,该钳位电路包括运算放大器和源跟随晶体管,所述运算放大器的同相端与参考电位相连,所述运算放大器的反相端与所述源跟随晶体管的漏端和所述复合介质栅双晶体管光敏探测器的漏端相连,所述运算放大器的输出端与所述源跟随晶体管的栅端相连,所述源跟随晶体管的源端与读出电路相连。本发明的钳位电路,利用运算放大器的虚短特性,能够以更低的功耗、更小的面积,实现更加稳定的钳位功能。(The invention discloses a clamping circuit based on a composite dielectric gate double-transistor photosensitive detector, which comprises an operational amplifier and a source following transistor, wherein the in-phase end of the operational amplifier is connected with a reference potential, the inverting end of the operational amplifier is connected with the drain end of the source following transistor and the drain end of the composite dielectric gate double-transistor photosensitive detector, the output end of the operational amplifier is connected with the gate end of the source following transistor, and the source end of the source following transistor is connected with a reading circuit. The clamping circuit of the invention utilizes the virtual short characteristic of the operational amplifier, and can realize more stable clamping function with lower power consumption and smaller area.)

1. A clamp circuit based on a composite dielectric gate double-transistor photosensitive detector comprises a source end and a drain end and is characterized by comprising an operational amplifier and a source follower transistor, wherein the operational amplifier comprises a same-phase end, an opposite-phase end and an output end, the source follower transistor comprises a gate end and a drain end, the same-phase end of the operational amplifier is connected with a reference potential, the opposite-phase end of the operational amplifier is connected with the drain end of the source follower transistor and the drain end of the composite dielectric gate double-transistor photosensitive detector, the output end of the operational amplifier is connected with the gate end of the source follower transistor, and the source end of the source follower transistor is connected with a reading circuit.

2. The clamp circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein:

the composite dielectric gate two-transistor based photosensitive detector comprises a MOS-C part and a MOSFET part, wherein the MOSFET part is arranged on one side of the MOS-C part,

the MOS-C part comprises a first bottom dielectric layer, a first charge coupling layer, a second top dielectric layer and a first control grid which are sequentially stacked above the first P-type semiconductor substrate;

the MOSFET part comprises a second bottom dielectric layer, a second charge coupling layer, a second top dielectric layer and a second control grid which are sequentially stacked above a second P-type semiconductor substrate;

the second bottom dielectric layer is connected with the first bottom dielectric layer, the second charge coupling layer is connected with the first charge coupling layer, the second top dielectric layer is connected with the first top dielectric layer, and the second control grid electrode is connected with the first control grid plate.

3. The clamp circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 2, wherein: and an N-type source electrode region and an N-type drain electrode region are arranged on one side, close to the second bottom dielectric layer, of the second P-type semiconductor substrate.

4. The clamp circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 2, wherein: and a threshold adjusting injection region is arranged on one side of the second P-type semiconductor substrate close to the second bottom dielectric layer.

5. The clamp circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 2, wherein: the widths of the first bottom dielectric layer, the first charge coupling layer, the second top dielectric layer and the first control grid electrode are all a, the widths of the second bottom dielectric layer, the second charge coupling layer, the second top dielectric layer and the second control grid electrode are all b, and b is a/3-2 a/3.

6. An analog-to-digital conversion circuit based on a composite dielectric gate two-transistor photosensitive detector, which is characterized in that a plurality of composite dielectric gate two-transistor photosensitive detectors form an array, wherein the drain terminals of each row of the composite dielectric gate two-transistor photosensitive detectors are connected to form bit lines, and each bit line is connected with the clamping circuit according to any one of claims 1 to 5.

7. The analog-to-digital conversion circuit based on the composite dielectric gate double-transistor photosensitive detector as claimed in claim 6, wherein the gate terminals of the composite dielectric gate double-transistor photosensitive detectors in each row are connected to form a word line, and the source terminals are connected to form a source line.

8. The analog-to-digital conversion circuit based on the composite dielectric gate double-transistor photosensitive detector as claimed in claim 6, wherein the substrates of a plurality of the composite dielectric gate double-transistor photosensitive detectors are connected to form a P substrate end, and the P substrate end is placed in the deep N-type well.

Technical Field

The invention belongs to the field of integrated circuits, and relates to a clamping circuit based on a composite dielectric gate double-transistor photosensitive detector.

Background

CCD and CMOS-APS, the two most common imaging devices at present, both have their own limitations. Due to the complex control time sequence and voltage requirements of the CCD, the working speed is low, and the integration is not easy; the CMOS-APS adopts a photosensitive diode and has a complex structure, so that the filling coefficient is low and the full-well charge is small.

In chinese patent CN201210442007, a two-transistor photosensitive detector is proposed, which is characterized in that a single semiconductor device can implement complete functions of resetting, sensing and reading, so as to form a complete pixel, and the fill factor of the pixel can be greatly improved. The composite dielectric gate double-transistor photosensitive detector is used as a new generation of imaging device, has higher working speed, larger filling coefficient and more full-well charges, can be integrated with a CMOS (complementary metal oxide semiconductor) process, and has inherent advantages compared with a CCD (charge coupled device) and a CMOS-APS (complementary metal oxide semiconductor-active plate). But at present, no clamping circuit based on a composite dielectric gate double-transistor photosensitive detector exists.

Therefore, a clamp circuit based on a composite dielectric gate two-transistor photosensitive detector is needed to solve the above technical problems.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a clamping circuit based on a composite dielectric gate double-transistor photosensitive detector to solve the problems in the prior art.

In order to achieve the above purpose, the invention provides the following technical scheme:

a clamp circuit based on a composite dielectric gate double-transistor photosensitive detector comprises a source end and a drain end, and comprises an operational amplifier and a source follower transistor, wherein the operational amplifier comprises a same-phase end, an opposite-phase end and an output end, the source follower transistor comprises a gate end and a drain end, the same-phase end of the operational amplifier is connected with a reference potential, the opposite-phase end of the operational amplifier is connected with the drain end of the source follower transistor and the drain end of the composite dielectric gate double-transistor photosensitive detector, the output end of the operational amplifier is connected with the gate end of the source follower transistor, and the source end of the source follower transistor is connected with a reading circuit.

Preferably, the composite dielectric gate two-transistor based photosensitive detector comprises a MOS-C part and a MOSFET part, wherein the MOSFET part is arranged on one side of the MOS-C part,

the MOS-C part comprises a first bottom dielectric layer, a first charge coupling layer, a second top dielectric layer and a first control grid which are sequentially stacked above the first P-type semiconductor substrate;

the MOSFET part comprises a second bottom dielectric layer, a second charge coupling layer, a second top dielectric layer and a second control grid which are sequentially stacked above a second P-type semiconductor substrate;

the second bottom dielectric layer is connected with the first bottom dielectric layer, the second charge coupling layer is connected with the first charge coupling layer, the second top dielectric layer is connected with the first top dielectric layer, and the second control grid electrode is connected with the first control grid plate.

Preferably, an N-type source region and an N-type drain region are arranged on one side, close to the second bottom dielectric layer, of the second P-type semiconductor substrate.

Preferably, a threshold adjusting injection region is arranged on one side, close to the second bottom dielectric layer, of the second P-type semiconductor substrate.

Preferably, the widths of the first bottom dielectric layer, the first charge coupling layer, the second top dielectric layer and the first control gate are all a, and the widths of the second bottom dielectric layer, the second charge coupling layer, the second top dielectric layer and the second control gate are all b, wherein b is a/3-2 a/3.

Has the advantages that: the clamp circuit based on the composite dielectric gate double-transistor photosensitive detector utilizes the virtual short characteristic of the operational amplifier, and can realize a more stable clamp function with lower power consumption and smaller area.

The invention also discloses an analog-digital conversion circuit based on the composite dielectric gate double-transistor photosensitive detector, wherein a plurality of composite dielectric gate double-transistor photosensitive detectors form an array, drain terminals of the composite dielectric gate double-transistor photosensitive detectors in each row are connected to form bit lines, and each bit line is connected with the clamping circuit as claimed in any one of claims 1 to 5.

Furthermore, the grid ends of the composite dielectric grid double-transistor photosensitive detectors in each row are connected to form a word line, and the source ends of the composite dielectric grid double-transistor photosensitive detectors in each row are connected to form a source line.

Furthermore, the substrates of the composite dielectric gate double-transistor photosensitive detectors are connected to form a P substrate end, and the P substrate end is placed in the deep N-type trap.

Has the advantages that: the analog-to-digital conversion circuit based on the composite dielectric gate double-transistor photosensitive detector adopts the clamping circuit, and the clamping circuit utilizes the virtual short characteristic of the operational amplifier, so that the more stable clamping function can be realized with lower power consumption and smaller area.

Drawings

FIG. 1 is a schematic diagram of a composite dielectric gate two-transistor photosensitive detector;

FIG. 2 is a circuit diagram of the clamping circuit of the present invention;

FIG. 3 is a block diagram of a clamp circuit according to embodiment 1 of the present invention;

fig. 4 is a block diagram of a clamp circuit according to embodiment 2 of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the composite dielectric gate two-transistor photosensitive detector adopted by the invention comprises a MOS-C part and a MOSFET part. The MOS-C part comprises a first bottom dielectric layer, a first charge coupling layer, a first top dielectric layer and a first control grid which are sequentially stacked above the first P-type semiconductor substrate. The MOSFET part comprises a second bottom dielectric layer, a second charge coupling layer, a second top dielectric layer and a second control grid which are sequentially stacked above a second P-type semiconductor substrate, wherein an N-type source electrode region and an N-type drain electrode region are arranged in the second P-type semiconductor substrate and on one side close to the second bottom dielectric layer, and a threshold adjusting injection region is arranged in the second P-type semiconductor substrate and below the second bottom dielectric layer.

Example 1

Referring to fig. 2 and 3, in the present embodiment, a clamp circuit is used for a pixel of a composite dielectric gate two-transistor photosensitive detector. C1, C2 and M0 form a composite dielectric gate double-transistor photosensitive detector, and the clamping circuit is used for stabilizing the drain voltage of the composite dielectric gate double-transistor photosensitive detector so that the composite dielectric gate double-transistor photosensitive detector can output stable current to a subsequent reading circuit.

Example 2

Referring to fig. 4, in the present embodiment, the clamp circuit is used in an array of composite-gate two-transistor photosensitive detectors, and the array of composite-gate two-transistor photosensitive detectors has 2 rows and 2 columns. Grid ends of the composite dielectric grid double-transistor photosensitive detectors in each row are connected to form word lines, drain ends of the composite dielectric grid double-transistor photosensitive detectors are connected to form bit lines, and source ends of the composite dielectric grid double-transistor photosensitive detectors are connected to form source lines; all composite dielectric gate two-transistor photosensitive detector substrates are connected to form a substrate and are placed in a deep N well (gray area in the figure). And the inverting ends of the clamping circuits #1 and #2 are respectively connected to bit lines of the composite dielectric gate two-transistor photosensitive detector array to provide stable voltage for the composite dielectric gate two-transistor photosensitive detector array.