阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 任飞 于 2019-10-22 设计创作，主要内容包括：一种半导体结构及其形成方法,提供衬底；在所述衬底上形成若干相互分立的主鳍部与伪鳍部,所述伪鳍部包括第一区以及位于所述第一区上的第二区,所述第二区的材料与所述主鳍部的材料不同,所述第二区的材料与所述第一区的材料不同；在所述衬底上形成隔离层,所述隔离层覆盖所述主鳍部的部分侧壁,所述隔离层覆盖所述第一区侧壁；在形成所述隔离层之后,刻蚀去除所述第二区。通过形成相互分立的主鳍部与伪鳍部,保证了在刻蚀过程中刻蚀环境的一致性,防止形成的主鳍部底部尺寸因刻蚀环境的改变而变大；另外通过刻蚀工艺对不同材料的刻蚀选择性,去除部分伪鳍部,避免了采用光刻图形化工艺所带来的缺陷,进而提升最终形成的半导体结构的性能。(A semiconductor structure and a forming method thereof, a substrate is provided; forming a plurality of main fin parts and a plurality of pseudo fin parts which are separated from each other on the substrate, wherein each pseudo fin part comprises a first area and a second area which is positioned on the first area, the material of the second area is different from that of the main fin parts, and the material of the second area is different from that of the first area; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the main fin portion, and the isolation layer covers the side walls of the first region; and after the isolating layer is formed, etching to remove the second region. By forming the main fin part and the pseudo fin part which are separated from each other, the consistency of etching environment in the etching process is ensured, and the size of the bottom of the formed main fin part is prevented from being enlarged due to the change of the etching environment; in addition, partial pseudo fin parts are removed through the etching selectivity of the etching process to different materials, so that the defects caused by the adoption of a photoetching patterning process are avoided, and the performance of the finally formed semiconductor structure is improved.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a plurality of main fin parts and a plurality of pseudo fin parts which are separated from each other on the substrate, wherein each pseudo fin part comprises a first area and a second area which is positioned on the first area, the material of the second area is different from that of the main fin parts, and the material of the second area is different from that of the first area;

forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the main fin portion, and the isolation layer covers the side walls of the first region;

and after the isolating layer is formed, etching to remove the second region.

2. The method for forming a semiconductor structure according to claim 1, wherein the first region is made of an insulating material.

3. The method of claim 1, wherein the substrate, the main fin, and the dummy fin are formed by a method comprising: providing an initial substrate; forming a plurality of first openings which are separated from each other in the initial substrate; forming a first fin material layer and a second fin material layer on the first fin material layer in the first opening, wherein the first opening is filled with the second fin material layer; forming a mask layer on the second fin material layer; forming a plurality of mutually-separated graphical structures on the mask layer; and etching the mask layer, the second fin material layer, the initial substrate and the first fin material layer by taking the patterned structure as a mask to form the substrate, the main fin and the pseudo fin.

4. The method for forming a semiconductor structure according to claim 3, wherein the method for forming the first opening comprises: forming a mask structure on the initial substrate; forming a patterning layer on the mask structure, wherein the patterning layer is internally provided with an opening for exposing a part of the mask structure; etching the mask structure and the initial substrate by taking the patterning layer as a mask to form the first opening; removing the patterned layer after forming the first opening.

5. The method of forming a semiconductor structure of claim 3, wherein the first fin material layer is formed by a method comprising: forming an initial first fin material layer in the first opening, wherein the initial first fin material layer fills the first opening; and etching back part of the initial first fin material layer to form the first fin material layer, wherein the top surface of the first fin material layer is lower than that of the initial substrate.

6. The method of forming a semiconductor structure of claim 3, wherein the second layer of fin material is formed by a method comprising: forming an initial second fin material layer on the surface of the first fin material layer, wherein the initial second fin material layer is filled in the first opening; and flattening the initial second fin part material layer to form the second fin part material layer.

7. The method of claim 3, wherein a material of the second layer of fin material is different from a material of the first layer of fin material.

8. The method of claim 7, wherein a material of the second fin material layer comprises silicon nitride; the material of the first fin material layer comprises silicon oxide.

9. The method of claim 3, wherein the patterning process comprises a self-aligned multi-patterning process.

10. The method for forming a semiconductor structure of claim 3, wherein the step of etching the mask layer, the second fin material layer, the initial substrate, and the first fin material layer using the patterned structure as a mask comprises the steps of: etching the mask layer and the second fin material layer by using the graphical structure as a mask through a first etching process until the top surface of the initial substrate is exposed; etching the initial substrate and the second fin material layer by adopting a second etching process until the top surface of the first fin material layer is exposed; and etching the initial substrate and the first fin material layer by adopting a third etching process to form the substrate, the main fin and a pseudo fin, wherein the pseudo fin comprises a first area formed by the first fin material layer and a second area formed by the second fin material layer.

11. The method for forming a semiconductor structure of claim 10, wherein the first etch process comprises an anisotropic dry etch process, and wherein an etch gas of the first etch process comprises Cl₂HBr, carrier gas comprises He, wherein Cl₂The flow rate of the catalyst is 80sccm to 2000sccm, the flow rate of HBr is 50sccm to 2000sccm, and the flow rate of He is 100sccm to 2000 sccm.

12. The method for forming a semiconductor structure of claim 10, wherein the second etching process uses an anisotropic dry etching process, and the etching gas of the second etching process comprises HBr and Cl₂、SF₆、NF₃、O₂、Ar、He、CH₂F₂And CHF₃The flow rate of the etching gas is 50-500 sccm.

13. The method for forming a semiconductor structure of claim 10, wherein the third etching process comprises an anisotropic dry etching process, and the etching gas of the third etching process comprises C₄F₈、C₅F₈And C₄F₆Wherein the flow rate of the etching gas is 1sccm to 400 sccm.

14. The method of forming a semiconductor structure of claim 1, wherein the spacer layer is formed by a method comprising: forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the main fin portion and the pseudo fin portion; and removing part of the initial isolation layer until the first region is exposed to form the isolation layer.

15. The method of forming a semiconductor structure of claim 2, wherein a material of the isolation layer is the same as a material of the first region.

16. The method of claim 14, wherein removing a portion of the initial isolation layer comprises a SiCoNi etch process or a Certas etch process.

17. The method for forming a semiconductor structure according to claim 1, wherein the removing the second region comprises an isotropic wet etching process using an etching solution comprising a hydrofluoric acid solution or a BOE solution.

18. The method of forming a semiconductor structure of claim 1, further comprising, after removing the second region of the dummy fin: and forming an interface layer on the surface of the exposed main fin portion.

19. The method of forming a semiconductor structure of claim 18, wherein a material of the interfacial layer comprises silicon oxide; the forming process of the interface layer adopts an in-situ water vapor process.

20. A semiconductor structure formed by the method of any of claims 1 to 19, comprising:

a substrate;

a first region on the substrate having a plurality of mutually separated main fin portions and dummy fin portions;

the isolation layer is located on the substrate and covers a part of side walls of the main fin portion, and the isolation layer covers the side walls of the first region of the pseudo fin portion.

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the continuous progress of semiconductor technology, the process nodes of semiconductor devices are continuously decreasing. However, due to the limitation of the precision of the existing photolithography process, the mask pattern formed by the existing photolithography process is difficult to meet the requirement of the continuous reduction of the feature size of the semiconductor device, and the development of the semiconductor technology is inhibited.

In order to further reduce the size of a semiconductor device based on the conventional photolithography process, a multiple patterning process is proposed in the related art. Among them, the Self-Aligned Quadruple patterning process (SAQP) has a promising application because it can form a smaller-sized mask.

However, the performance of the semiconductor structure formed by the multiple patterning process in the prior art still needs to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can effectively improve the performance of the formed semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of main fin parts and a plurality of pseudo fin parts which are separated from each other on the substrate, wherein each pseudo fin part comprises a first area and a second area which is positioned on the first area, the material of the second area is different from that of the main fin parts, and the material of the second area is different from that of the first area; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the main fin portion, and the isolation layer covers the side walls of the first region; and after the isolating layer is formed, etching to remove the second region.

Optionally, the first region material is an insulating material.

Optionally, the method for forming the substrate, the main fin portion, and the dummy fin portion includes: providing an initial substrate; forming a plurality of first openings which are separated from each other in the initial substrate; forming a first fin material layer and a second fin material layer on the first fin material layer in the first opening, wherein the first opening is filled with the second fin material layer; forming a mask layer on the second fin material layer; forming a plurality of mutually-separated graphical structures on the mask layer; and etching the mask layer, the second fin material layer, the initial substrate and the first fin material layer by taking the patterned structure as a mask to form the substrate, the main fin and the pseudo fin.

Optionally, the method for forming the first opening includes: forming a mask structure on the initial substrate; forming a patterning layer on the mask structure, wherein the patterning layer is internally provided with an opening for exposing a part of the mask structure; etching the mask structure and the initial substrate by taking the patterning layer as a mask to form the first opening; removing the patterned layer after forming the first opening.

Optionally, the method for forming the first fin material layer includes: forming an initial first fin material layer in the first opening, wherein the initial first fin material layer fills the first opening; and etching back part of the initial first fin material layer to form the first fin material layer, wherein the top surface of the first fin material layer is lower than that of the initial substrate.

Optionally, the method for forming the second fin material layer includes: forming an initial second fin material layer on the surface of the first fin material layer, wherein the initial second fin material layer is filled in the first opening; and flattening the initial second fin part material layer to form the second fin part material layer.

Optionally, the material of the second fin material layer is different from the material of the first fin material layer.

Optionally, the material of the second fin material layer includes silicon nitride; the material of the first fin material layer comprises silicon oxide.

Optionally, the forming process of the patterned structure includes a self-aligned multiple patterning process.

Optionally, the method for forming the substrate, the main fin portion, and the dummy fin portion by etching the mask layer, the second fin portion material layer, the initial substrate, and the first fin portion material layer using the patterned structure as a mask includes: etching the mask layer and the second fin material layer by using the graphical structure as a mask through a first etching process until the top surface of the initial substrate is exposed; etching the initial substrate and the second fin material layer by adopting a second etching process until the top surface of the first fin material layer is exposed; and etching the initial substrate and the first fin material layer by adopting a third etching process to form the substrate, the main fin and a pseudo fin, wherein the pseudo fin comprises a first area formed by the first fin material layer and a second area formed by the second fin material layer.

Optionally, the first etching process includes an anisotropic dry etching process, and the etching gas of the first etching process includes Cl₂HBr, carrier gas comprises He, wherein Cl₂The flow rate of the catalyst is 80sccm to 2000sccm, the flow rate of HBr is 50sccm to 2000sccm, and the flow rate of He is 100sccm to 2000 sccm.

Optionally, the second etching process adopts an anisotropic dry etching process, and etching gas of the second etching process includes HBr and Cl₂、SF₆、NF₃、O₂、Ar、He、CH₂F₂And CHF₃The flow rate of the etching gas is 50-500 sccm.

Optionally, the third etching process includes an anisotropic dry etching process, and the etching gas of the third etching process includes C₄F₈、C₅F₈And C₄F₆Wherein the flow rate of the etching gas is 1sccm to 400 sccm.

Optionally, the forming method of the isolation layer includes: forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the main fin portion and the pseudo fin portion; and removing part of the initial isolation layer until the first region is exposed to form the isolation layer.

Optionally, the material of the isolation layer is the same as the material of the first region.

Optionally, the process for removing a portion of the initial isolation layer includes a SiCoNi etching process or a Certas etching process.

Optionally, the process for removing the second region includes an isotropic wet etching process, and the etching solution used in the isotropic wet etching process includes a hydrofluoric acid solution or a BOE solution.

Optionally, after removing the second region of the dummy fin portion, the method further includes: and forming an interface layer on the surface of the exposed main fin portion.

Optionally, the material of the interface layer comprises silicon oxide; the forming process of the interface layer adopts an in-situ water vapor process.

Correspondingly, the invention also provides a semiconductor structure formed by the method, which comprises the following steps: a substrate; a first region on the substrate having a plurality of mutually separated main fin portions and dummy fin portions; the isolation layer is located on the substrate and covers a part of side walls of the main fin portion, and the isolation layer covers the side walls of the first region of the pseudo fin portion.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the technical scheme, a plurality of main fin parts and pseudo fin parts which are separated from each other are formed on a substrate, each pseudo fin part comprises a first area and a second area located on the first area, the main fin parts and the second areas are made of different materials, and the second areas of the pseudo fin parts are removed by etching selectivity of an etching process on different materials. By the formed main fin portion and the pseudo fin portion, the initial environment of the graphical structure for forming the main fin portion and the pseudo fin portion can be unchanged, the consistency of the etching environments of the main fin portion and the pseudo fin portion in the etching process is guaranteed, and the bottom size of the formed main fin portion is prevented from being increased due to the change of the etching environments; in addition, the second region of the pseudo fin part is removed through the etching selectivity of the etching process to different materials, so that the problem of poor fin part removing effect caused by the adoption of a photoetching patterning process is solved, and the performance of the finally formed semiconductor structure is improved.

Further, in the technical solution of the present invention, the material of the first region is an insulating material, and the material of the isolation layer is the same as the material of the first region. The first region formed by the insulating material and the isolation layer can be used as an isolation structure between the main fin parts, so that the step of removing the first region is omitted, and the production efficiency is effectively improved.

Furthermore, in the technical scheme of the invention, the SiCoNi etching process is adopted as the process for removing part of the initial isolation layer, and the etched surface formed by adopting the SiCoNi etching process has lower roughness, has fewer defects on the etched surface, is not easy to generate electric leakage, and can effectively improve the performance of the finally formed semiconductor structure.

Drawings

FIGS. 1-3 are schematic structural diagrams illustrating various steps in an embodiment of a fin formation process;

FIGS. 4 to 6 are schematic structural diagrams illustrating the structure after a portion of the fin portion is removed by a photolithography patterning process;

fig. 7 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, the performance of the semiconductor structure formed by the multiple patterning process in the prior art still needs to be improved.

The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1 to 3 are schematic structural diagrams of steps of an embodiment of a fin formation process.

Referring to fig. 1, an initial substrate 100 is provided, where the initial substrate 100 includes a first region I, a second region II, and a third region III, and the first region I, the second region II, and the third region III are adjacent to each other in sequence; forming a mask layer 101 on the initial substrate 100; a plurality of mutually discrete initial patterning structures 102 are formed on the mask layer 101, and the process for forming the initial patterning structures 102 adopts a multiple patterning process.

Referring to fig. 2, the initial patterned structure 102 corresponding to the second region II is removed to form a patterned structure 105.

Referring to fig. 3, the mask layer 101 and the initial substrate 100 are etched by using the patterned structure 105 as a mask to form a substrate 103 and a plurality of mutually discrete fin portions 104 on the substrate 103; after the substrate 103 and the fin 104 are formed, the patterned structure 105 and the mask layer 101 are removed.

In the above embodiment, according to the requirement on the density of the finally formed fin 104, the initial patterned structure 102 corresponding to the second region II is removed to form the patterned structure 105, and after the patterned structure 105 is formed, the environment of the patterned structure 105, which is originally adjacent to the second region II, in the first region I and the third region III is changed, specifically, the adjacent patterned structure 105 with a larger distance is formed in the first region I and the third region III. As the distance between the adjacent patterned structures 105 in the first region I and the third region III is increased, in the subsequent etching process, the stress applied by the etching solution on the patterned structures 105 adjacent to the first region I and the third region III is decreased, which causes the dimension of the bottom of the finally correspondingly formed fin portion 104 to be increased, and further affects the performance of the finally formed semiconductor structure

In order to solve the above problems, another method for forming a fin portion is proposed, and fig. 4 to 6 are schematic cross-sectional structures of fin portions formed by the method.

In the method for forming the fin portion, a graphical structure is adopted as a mask for etching, and a plurality of fin portions 201 with the same interval and the same width are formed; after the fin 201 is formed, a photolithographic patterning process is used to remove a portion of the fin 201 according to design requirements.

However, due to the limitations of the manufacturing process, the removal of a portion of the fin 201 by the photolithography process may easily result in incomplete removal of the fin 201 (as shown in fig. 4), excessive removal of the fin (as shown in fig. 5), or damage to the remaining fin 201 (as shown in fig. 6), which may affect the performance of the finally formed semiconductor structure.

On the basis, the invention provides a semiconductor structure and a forming method thereof. By forming the main fin part and the pseudo fin part which are separated from each other, the consistency of etching environment in the etching process is ensured, and the size of the bottom of the formed main fin part is prevented from being increased; in addition, partial pseudo fin parts are removed through the etching selectivity of the etching process to different materials, so that the defects caused by the adoption of a photomask process are avoided, and the performance of the finally formed semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 7 to 15 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 7 to 12, a substrate is provided; forming a plurality of main fin parts and a plurality of pseudo fin parts which are separated from each other on the substrate, wherein each pseudo fin part comprises a first area and a second area which is positioned on the first area, the material of the second area is different from that of the main fin parts, and the material of the second area is different from that of the first area. As will be described in detail below.

Referring to fig. 7, an initial substrate 300 is provided; a plurality of first openings 301 are formed in the initial substrate 300, which are separated from each other.

In this embodiment, the material of the initial substrate 300 is silicon; in other embodiments, the material of the initial substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

In this embodiment, the method for forming the first opening 301 includes: forming a mask structure 311 on the initial substrate 300; forming a patterning layer (not shown) on the mask structure 311, the patterning layer having an opening (not shown) therein that exposes a portion of the mask structure; etching the mask structure 311 and the initial substrate 300 by using the patterning layer as a mask to form the first opening 301; after the first opening 301 is formed, the patterning layer is removed.

The openings in the patterned layer exposing portions of the mask structure 311 are used to define the positions of the subsequently formed dummy fins.

In this embodiment, the mask structure 311 includes a first mask layer 312 and a second mask layer 313 on the first mask layer 312.

The first mask layer 312 is made of nitrogen-doped silicon oxycarbide; the first mask layer 312 formed by the nitrogen-doped silicon oxycarbide has good bonding capacity with the device layer initial substrate, and when the etched first mask layer 312 is used as a mask to etch the initial substrate 300 subsequently, the first mask layer 312 is not easy to peel off or warp, so that the first mask layer 312 has good capacity of keeping an etched pattern, the first opening 301 formed in the initial substrate 300 is favorable for having good appearance, and the accuracy of the etched pattern is effectively improved.

The second mask layer 313 is made of titanium nitride, the bonding capability between the second mask layer 313 and the first mask layer 312 is good, and the second mask layer 313 can protect the surface of the first mask layer 312 when a layer to be etched is etched in the subsequent process, so that the first mask layer 312 cannot be thinned; moreover, the second mask layer 313 has a relatively high physical strength, so that the patterns of the second mask layer 313 and the first mask layer 312 can be kept stable during subsequent etching of the layer to be etched, which is beneficial to further improving the appearance of the first opening 301.

In other embodiments, the mask structure may also be a single layer structure.

In this embodiment, the depth of the first opening 301 is the same as the height of the subsequently formed dummy fin portion, and the width of the first opening 301 is greater than the width of the subsequently formed dummy fin portion.

Referring to fig. 8, a first fin material layer 302 and a second fin material layer 303 on the first fin material layer 302 are formed in the first opening 301, and the first opening 301 is filled with the second fin material layer 303.

In this embodiment, the method for forming the first fin material layer 302 includes: forming an initial first fin material layer (not shown) within the first opening 301, the initial first fin material layer filling the first opening 301; planarizing the initial first fin material layer; after the planarization process, a portion of the initial first fin material layer is etched back to form the first fin material layer 302, and a top surface of the first fin material layer 302 is lower than a top surface of the initial substrate 300.

In this embodiment, the initial first fin material layer is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, which is a process of forming a plasma on a local portion of a gas containing atoms of a thin film by using microwaves or radio frequencies, and the plasma has a strong chemical activity and is easily reacted to deposit a desired thin film on a substrate. The formation process of the initial first fin material layer formed by the plasma enhanced chemical vapor deposition process has the characteristics of high deposition rate, good film formation quality and strong filling capacity, so that the first fin material layer 302 formed subsequently can be well combined with the first opening 301.

In this embodiment, the thickness of the first fin material layer 302 is the same as the thickness of the subsequent isolation layer, and the thickness direction of the first fin material layer 302 and the thickness direction of the isolation layer are perpendicular to the bottom surface of the first opening 301.

The thickness of the first fin material layer 302 is set to be the same as that of the isolation layer, so that the thickness of a first region of the pseudo fin formed by the first fin material layer 302 is the same as that of the isolation layer, the first region and the isolation layer can be used as an isolation structure between the main fins at the same time, the step of further processing the first region is omitted, and production efficiency is effectively improved.

In this embodiment, the process of etching back a portion of the initial first fin material layer uses an anisotropic dry etching process.

In this embodiment, the method for forming the second fin material layer 303 includes: forming an initial second fin material layer on the surface of the first fin material layer 302 to fill the first opening 301; planarizing the initial second fin material layer to form the second fin material layer 303.

In this embodiment, the formation process of the initial second fin material layer adopts a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, which enables the second fin material layer 303 to be formed later to be better combined with the first opening 301.

In this embodiment, the process of planarizing the initial second fin material employs a chemical mechanical polish process.

The first fin material layer 302 is used for forming a first region of the subsequent pseudo fin, the second fin material layer 303 is used for forming a second region of the subsequent pseudo fin, and materials of the first fin material layer 302 and the second fin material layer 303 are different because the materials of the first region and the second region are different.

Through different material settings of the first area and the second area, the first area and the second area can be guaranteed to have a larger etching selection ratio in a subsequent etching process, and then the second area is guaranteed to be removed only and the first area is guaranteed to be damaged less, so that when the first area is used as a subsequent isolation structure of the main fin portion, the structure is complete, and the isolation effect is effectively improved.

In the embodiment, the material of the first fin material layer 302 includes silicon oxide; the material of the second fin material layer 303 includes silicon nitride.

Referring to fig. 9, a mask layer 304 is formed on the second fin material layer 303; a plurality of patterned structures 305 are formed on the mask layer 304, which are discrete from each other.

In the present embodiment, the process of forming the patterned structure 305 employs a self-aligned multi-patterning process. Through the self-aligned multi-patterning process, a portion of the patterned structure 305 corresponds to the first opening 301 one by one, and the portion of the patterned structure 305 is used for forming the subsequent dummy fin portion.

In this embodiment, after the patterned structure 305 is formed, the mask layer 304, the second fin material layer 303, the initial substrate 300, and the first fin material layer 302 are etched using the patterned structure 305 as a mask to form the substrate, the main fin, and the dummy fin. Please refer to fig. 10 to fig. 12 for a specific forming process.

Referring to fig. 10, the patterned structure 305 is used as a mask, and the mask layer 304 and the second fin material layer 303 are etched by a first etching process until the top surface of the initial substrate 300 is exposed, so as to form a mask body (not shown).

In this embodiment, since the initial substrate 300 further has a mask structure 311 on the surface, the first etching process further etches and removes a portion of the mask structure 311.

The first etching process is stopped on the surface of the initial substrate 300, so that the mask layer 304, the second fin material layer 303 outside the first opening 301, and the mask structure 311 after etching jointly form a mask body of the main fin portion and the dummy fin portion.

The first etching process adopts anisotropic dry etching, and the first etching process should satisfy the requirement of having low etching selectivity on the mask layer 304, the second fin material layer 303 and the mask structure 311, and also satisfy the requirement of having high etching selectivity on the initial substrate 300, so that it can be ensured that the final etching is stopped on the top surface of the initial substrate 300.

The etching gas of the first etching process comprises Cl₂HBr, and He as carrier gas, wherein Cl₂The flow rate of the catalyst is 80sccm to 2000sccm, the flow rate of HBr is 50sccm to 2000sccm, and the flow rate of He is 100sccm to 2000 sccm.

In the present embodiment, after exposing the top surface of the initial substrate 300, the patterned structure 305 (not shown) is removed.

Referring to fig. 11, the initial substrate 300 and the second fin material layer 303 are etched by using a second etching process until the top surface of the first fin material layer 302 is exposed, so as to form a second region B of the dummy fin 306.

The second etching process adopts anisotropic dry etching, and the second etching process should meet the requirement of having low etching selectivity on the second fin material layer 303 and the initial substrate 300, so as to ensure that the initial substrate 300 and the second fin material layer 303 are etched at the same time at similar etching rates, and improve the production efficiency.

The etching gas adopted by the second etching process comprises HBr and Cl₂、SF₆、NF₃、O₂、Ar、He、CH₂F₂And CHF₃The flow rate of the etching gas is 50-500 sccm.

In the parameter range of the second etching process, the requirement on etching selectivity can be met, meanwhile, the etching rate is well controlled, and the situation that the initial substrate 300 is etched more to influence the structure of the subsequently formed main fin portion is effectively prevented.

In the present embodiment, after the second region B of the dummy fin 306 is formed, the mask layer 304 is removed (not shown).

Referring to fig. 12, a third etching process is performed to etch the initial substrate 300 and the first fin material layer 302, so as to form the substrate 307, the main fin 308, and the first region a of the dummy fin 306.

The third etching process adopts anisotropic dry etching, and the third etching process should satisfy the requirement of having low etching selectivity to the first fin material layer 302 and the initial substrate 300, and also satisfy the requirement of having high etching selectivity to the second region B, so as to reduce damage to the second region B while ensuring that the initial substrate 300 and the first fin material layer 302 are etched at similar etching rates.

The etching gas adopted by the third etching process comprises C₄F₈、C₅F₈And C₄F₆Wherein the flow rate of the etching gas is 1sccm to 400 sccm.

By not changing the initial environment of the patterned structure 305, the patterned structure 305 is used as a mask to form a plurality of mutually discrete main fin portions 308 and dummy fin portions 306, so that the consistency of the etching environments of the main fin portions 308 and the dummy fin portions 306 is ensured in the etching process, and the bottom size of the formed main fin portions 308 is prevented from being increased due to the change of the etching environment, thereby further influencing the performance of the finally formed semiconductor structure.

Referring to fig. 13, an isolation layer 309 is formed on the substrate 307, wherein the isolation layer 309 covers a portion of the sidewalls of the main fin portion 308, and the isolation layer 309 covers the sidewalls of the first region a.

In this embodiment, the method for forming the isolation layer 309 includes: forming an initial isolation layer (not shown) on the substrate 307, the initial isolation layer covering the main fins 308 and the dummy fins 306; part of the initial isolation layer is removed until the first region a is exposed, forming the isolation layer 309.

The process for removing part of the initial isolation layer is a SiCoNi etching process or a Certas etching process. In this embodiment, the SiCoNi etching process is used as the process for removing a portion of the initial isolation layer, and the etched surface formed by using the SiCoNi etching process has low roughness, has few defects on the etched surface, is not easy to generate electric leakage, and can effectively improve the performance of the finally formed semiconductor structure.

The material of the first region a is an insulating material, and the isolation layer 309 is the same as the material of the first region a. Since the first region a is formed by etching the first fin material layer 302, the first region a is also made of silicon oxide, and the first region a formed by using an insulating material and the isolation layer 309 can be simultaneously used as an isolation structure between the main fins 308, so that the step of removing the first region a is omitted, and the production efficiency is effectively improved.

In the embodiment, after the initial isolation layer is formed and before part of the initial isolation layer is removed, the surface of the initial isolation layer is subjected to planarization treatment; after the planarization process, the mask structure 311 (not shown) is removed.

Referring to fig. 14, after the isolation layer 309 is formed, the second region B is etched away.

And the process for removing the second region B by etching adopts an isotropic wet etching process, and the etching solution adopted by the isotropic wet etching process comprises a hydrofluoric acid solution or a BOE solution. In this embodiment, the etching solution used in the isotropic wet etching process includes a hydrofluoric acid solution.

And removing the second region B of the pseudo fin part through the etching selectivity of the etching process to different materials, so that the problem of poor fin part removing effect caused by the adoption of a photomask process is avoided, and the performance of the finally formed semiconductor structure is improved.

Referring to fig. 15, after removing the second region B, an interfacial layer 310 is formed on the exposed surface of the primary fin portion 308.

In this embodiment, the material of the interfacial layer 310 is silicon oxide; the formation process of the interfacial layer 310 employs an in-situ moisture process.

The interface layer 310 formed by the in-situ water vapor process is high in density, uniform in thickness, good in step coverage capability, capable of tightly covering the side wall and the top surface of the main fin portion 308, and good in protection effect on the surface of the main fin portion 308.

Accordingly, in an embodiment of the present invention, a semiconductor structure formed by the above method is further provided, with continued reference to fig. 14, including: a substrate; a first region a having a plurality of mutually discrete main fins 308 and dummy fins 306 on the substrate 307; an isolation layer 309 located on the substrate 307, wherein the isolation layer 309 covers a portion of a sidewall of the main fin portion 308, and the isolation layer 309 covers a sidewall of the first region a of the dummy fin portion 306.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.