阅读说明：本技术 用于多路径低噪声放大器的紧凑架构 (Compact architecture for multipath low noise amplifier ) 是由 乔纳森·詹姆斯·克拉伦 于 2019-09-13 设计创作，主要内容包括：描述了在移动接收器前端中使用以支持多个路径和多个频带的方法和设备。所提出的设备和方法通过针对每个同时输出使用一个低噪声放大器而提供了可扩展性、频带捷变以及尺寸减小的益处。基于所公开的教导,还提出了多频带信号的可变增益放大。(Methods and apparatus for use in a mobile receiver front end to support multiple paths and multiple frequency bands are described. The proposed apparatus and method provide scalability, band agility, and size reduction benefits by using one low noise amplifier for each simultaneous output. Based on the disclosed teachings, variable gain amplification of multi-band signals is also proposed.)

1. A Radio Frequency (RF) receiver, comprising:

a plurality of current gain blocks; and

a plurality of output loads;

wherein:

(i) each current gain block selectively connected to one or more of the plurality of output loads;

(ii) a current gain block of the plurality of current gain blocks is configured to:

receiving an input signal;

generating one or more amplified signals corresponding to the input signal, and

(iii) an output load of the plurality of output loads is configured to receive the respective one or more amplified signals and is configured to generate the respective one or more output signals.

2. The RF receiver of claim 1 wherein the plurality of current gain blocks and the plurality of output loads are implemented on the same chip or die.

3. The receiver of claim 1, wherein:

the plurality of current gain blocks are tunable;

the input signal corresponds to one or more frequency bands; and is

The current gain block of the plurality of current gain blocks is further configured to be tuned into the one or more frequency bands.

4. The RF receiver of claim 3 wherein the output load is tunable to support a second frequency band comprising a combination of one or more first frequency bands supported by respective current gain blocks.

5. The RF receiver of claim 1, wherein each of the plurality of current gain blocks comprises:

one or more gain transistors;

a first variable capacitor coupled across a gate and a source of a gain transistor of the one or more gain transistors;

one or more cascode transistors coupling the one or more gain transistors to respective one or more of the plurality of output loads; and is

The drains of the one or more cascode transistors are connectable to a power supply via an RF choke.

6. The RF receiver of claim 1, wherein each of the plurality of current gain blocks comprises:

one or more gain transistors;

a first variable inductor coupling sources of the one or more gain transistors to a first reference voltage or ground;

one or more cascode transistors coupling the one or more gain transistors to respective one or more of the plurality of output loads; and is

The drains of the one or more cascode transistors are connectable to a power supply via an RF choke.

7. The RF receiver of claim 5 wherein each of a plurality of current gain blocks further comprises a first variable inductor coupling the source of the one or more gain transistors to a first reference voltage or ground.

8. The RF receiver of claim 7 wherein a combination of the variable capacitor and the variable inductor is used to tune the respective current gain block to the respective one or more frequency bands.

9. The RF receiver of claim 8 wherein a combination of the variable capacitor and the variable inductor is used to set a desired gain and impedance appropriate for the respective one or more frequency bands.

10. The RF receiver of claim 7 wherein the output load comprises:

an RF choke coil; and

a transistor stack coupling the cascode transistor to a second variable inductor coupled to a second reference voltage or ground.

11. The RF receiver of claim 7 wherein the output load comprises:

an RF choke coil; and

a transistor stack and a second variable capacitor;

wherein the second variable capacitor couples the transistor stack to an output terminal of the output load.

12. The RF receiver of claim 11, wherein:

the transistor stack couples the cascode transistor to a second variable inductor coupled to a second reference voltage or ground; and is

The combination of the second variable inductor and the second variable capacitor is used for tuning purposes.

13. The RF receiver of claim 12 wherein the transistor stack comprises PMOS transistors.

14. The RF receiver of claim 13 configured to receive a bias voltage via a gate of the cascode transistor.

15. The RF receiver of claim 14 wherein the cascode transistor is configured to be in an on state or an off state in response to an applied bias voltage.

16. The RF receiver of claim 15 wherein each output load is configured to receive an amplified signal from only one of the respective ones of the plurality of current gain blocks.

17. The RF receiver of claim 1 wherein at least one of the plurality of current gain blocks is different from all other of the plurality of gain blocks.

18. The RF receiver of claim 1 wherein all of the plurality of current gain blocks are the same.

19. The RF receiver of claim 1 wherein each of the plurality of current gain blocks is different from any other of the plurality of current gain blocks.

20. The RF receiver of claim 7 wherein at least one of the current gain blocks in the plurality of current gain blocks has a variable gain.

21. The receiver of claim 12, further comprising: a first switch and a second switch configured to control a signal through the current gain block, wherein:

the first switch is coupled across a combination of the gain transistor and the cascode transistor;

the second switch couples the input terminal to the output terminal;

in a first gain state, the first switch is closed and the second switch is open, thereby bypassing the one or more gain transistors and creating a first signal path through the transistor stack from the input terminal to the output terminal;

in a second gain state, the first switch is open and the second switch is open, thereby bypassing the stacked transistors and creating a second signal path from the input terminal to the output terminal via a combination of the one or more gain transistors and the one or more cascode transistors; and is

In a third state, the first switch is open and the second switch is closed, thereby creating a third path directly from the input terminal to the output terminal without amplification.

22. The receiver of claim 12, further comprising: a first switch and a second switch configured to control a gain of the current gain block, wherein:

the first switch is coupled across a combination of the gain transistor and the cascode transistor,

the second switch is coupled across the stacked transistor;

in a first state, the first switch is closed and the second switch is open, thereby creating a first signal path through the stacked transistors from the input terminal to the output terminal;

in a second state, the first switch is open and the second switch is closed, thereby bypassing the stacked transistors and creating a second signal path from the input terminal to the output terminal via a combination of the one or more gain transistors and the one or more cascode transistors; and is

In a third state, the first switch and the second switch are closed, thereby bypassing the stack transistor and the gain transistor and creating a third signal path from the input terminal to the output terminal.

23. A method of amplifying a signal having a frequency spectrum comprising a plurality of frequency bands:

providing one or more current gain blocks;

providing one or more output loads;

connecting each of the one or more current gain blocks to one or more output loads;

amplifying at least one signal corresponding to one or more of the plurality of frequency bands to generate one or more amplified signals, an

Driving at least one of the one or more output loads using the one or more amplified signals to generate at least one or more amplified output signals.

24. The method of claim 23, wherein the one or more amplified output signals comprise two or more amplified output signals.

25. A Radio Frequency (RF) receiver front end, comprising:

a plurality of band filters corresponding to one or more frequency bands representing an input signal;

one or more band switches;

one or more current gain blocks connecting each respective band switch of the one or more band switches to one or more output loads;

wherein:

each band switch is configured to select at least one band filter of the plurality of band filters;

a current gain block corresponding to the band switch is configured to be selectively tuned into the at least one of the one or more frequency bands;

the at least one of the one or more band filters receiving the input signal to generate a filtered signal;

the current gain block is configured to receive the filtered signal to generate one or more amplified signals; and is

The one or more output loads are configured to receive the one or more amplified signals and to generate respective one or more output signals.

Technical Field

The present disclosure relates to Low Noise Amplifiers (LNAs), and more particularly, to methods and apparatus for use in a mobile receiver front end to support multiple paths and multiple frequency bands.

Background

The complexity of Low Noise Amplifier (LNA) front-end circuits for mobile communications, which need to support multiple frequency bands and support multiple amplifier paths (carrier aggregation and/or dual connectivity) that are active simultaneously, continues to increase. As an example, in the Long Term Evolution (LTE) standard, carrier aggregation is used to increase bandwidth. Such carrier aggregation may include various modes of operation, such as intra-band continuous/discontinuous carrier aggregation and inter-band carrier aggregation. Therefore, a receiver supporting these various modes is required. At the same time, RF front-end vendors are forced to make design changes quickly while reducing device size and cost. In other words, while there is an increasing demand to reduce the size and manufacturing cost of mobile communication equipment, miniaturization of such equipment has become a necessary design requirement.

Background

Disclosure of Invention

The methods and apparatus taught in the present disclosure address the challenging and conflicting design requirements described in the preceding section. The described methods and apparatus provide an LNA design that enables easier modification of the band input and the number of supported outputs. Such a method and device aim at reducing the device size by using substantially one LNA for each simultaneous output.

According to a first aspect of the present disclosure, there is provided a Radio Frequency (RF) receiver comprising: a plurality of current gain blocks; and a plurality of output loads; wherein: (i) each current gain block selectively connected to one or more of a plurality of output loads; (ii) a current gain block of the plurality of current gain blocks is configured to: receiving an input signal; (ii) generate one or more amplified signals corresponding to the input signal, and (iii) an output load of the plurality of output loads is configured to receive the respective one or more amplified signals and generate the respective one or more output signals.

According to a second aspect of the present disclosure, there is provided a method of amplifying a signal having a spectrum comprising a plurality of frequency bands, the method comprising: providing one or more current gain blocks; providing one or more output loads; connecting each gain block of the one or more current gain blocks to one or more output loads; the method includes amplifying at least one signal corresponding to one or more of the plurality of frequency bands to generate one or more amplified signals, and driving at least one of the one or more output loads using the one or more amplified signals to generate at least one or more amplified output signals.

According to a third aspect of the present disclosure, there is provided a Radio Frequency (RF) receiver front-end comprising: a plurality of band filters corresponding to one or more frequency bands representing an input signal; one or more band switches; one or more current gain blocks connecting each respective band switch of the one or more band switches to one or more output loads; wherein: each band switch is configured to select at least one band filter of a plurality of band filters; a current gain block corresponding to the band switch is configured to be selectively tuned into at least one of the one or more frequency bands; at least one of the one or more band filters receiving an input signal to generate a filtered signal; a current gain block configured to receive the filtered signal to generate one or more amplified signals; and the one or more output loads are configured to receive the one or more amplified signals and generate corresponding one or more output signals.

Drawings

Fig. 1 illustrates a receiver front-end according to an embodiment of the present disclosure.

Fig. 2 shows how different elements of a receiver front-end according to the present disclosure may be arranged on the same chip or die.

Fig. 3 shows the correspondence of frequencies and output loads supported by various current gain blocks of the receiver front-end.

Fig. 4 shows some exemplary frequency bands.

Fig. 5A to 5B show a receiver input stage.

Fig. 5C shows an exemplary current gain block using stacked transistors.

Fig. 5D illustrates an exemplary receiver front end according to an embodiment of the present disclosure.

Fig. 6A illustrates an exemplary LNA architecture according to an embodiment of the present disclosure.

Fig. 6B illustrates an exemplary LNA architecture according to another embodiment of the present disclosure.

Fig. 7 shows an exemplary LNA architecture with three different gain states.

Fig. 8 shows an exemplary LNA architecture with three different gain states.

Detailed Description

Definition of

The term "current gain block" refers herein to an electronic circuit that amplifies an input signal, thereby generating a current to drive an output load.

The term "folded architecture" refers herein to an LNA architecture that uses a combination of Negative Metal Oxide (NMOS) and Positive Metal Oxide (PMOS) transistors in the current gain and load stages to support the smaller available supply voltage margin imposed by design requirements.

Description of the invention

Methods and apparatus in accordance with the present disclosure are presented that provide LNA designs that enable easier modification of the band inputs and the number of outputs supported. Such methods and apparatus:

providing band agility, covering as many bands as possible with one LNA

Aiming at size reduction by using one LNA for each simultaneous output

Supporting step variable gain for low Noise Figure (NF) in high gain state and high linearity in low gain state.

Fig. 1 shows a receiver front end (100) according to an embodiment of the present disclosure. The receiver front-end (100) comprises an antenna (110), the antenna (110) being connected to a plurality of band filters (112) through an antenna switch (111). The plurality of band filters (112) correspond to frequency bands (e.g., f1, … …, f 4). The receiver front-end (100) further comprises two band switches (113, 114), the two band switches (113, 114) being connected to corresponding current gain blocks (117, 118) of the two band switches (113, 114) via coupling inductors (115, 116), respectively. According to an embodiment of the present disclosure, the current gain blocks (117, 118) may each be configured to drive two loads (119, 120) simultaneously and thus generate an output signal at the outputs (out1, out 2). The current gain block (117) may be configured to support any one of the frequency bands (f1, f2), and similarly, the current gain block (118) may be configured to support any one of the frequency bands (B3, B4). Thus, the receiver front-end (100) can support four input frequency bands and two output loads. By way of example and according to design requirements, the current blocks (117, 118) may be tuned to support frequency bands (f1, f3), respectively. In the same embodiment, the band switches (113, 114) may be configured to select the frequency bands (f1, f3), respectively. Those skilled in the art will appreciate that depending on design requirements, no major changes to the design of the current gain block will be required other than moving to the desired frequency band, and this will enable adaptation to various design requirements without going through lengthy design cycles. With further reference to fig. 1, those skilled in the art will also appreciate that the combination of the current gain block (117) and each of the loads (119, 120) may be considered a separate LNA, for example. Due to the separation of the current gain block and the load, the simultaneous reuse of the same current gain block for multiple output loads can be achieved, thereby reducing the footprint to address the stringent size reduction requirements as previously described. With further reference to fig. 1, those skilled in the art will appreciate that embodiments may be made to support any number of frequency bands and use any number of current gain blocks and output loads without departing from the scope and spirit of the present invention.

Fig. 2 shows a diagram (200) of an RF receiver front-end (210) according to an embodiment of the present disclosure, which diagram (200) shows how the current gain block and the output load may be arranged on the same chip or die. This is a simplified diagram in which details of how various elements are interconnected are not shown to avoid the diagram being flooded with interconnect details (overwriting). As shown in fig. 2, the RF receiver front end (210) includes a plurality of current gain blocks (gm1, … …, gm6) and an output load (LD1, … …, LD 4). In other words, the embodiment shown in fig. 2 supports 6 LNA inputs (each LNA input may support multiple sub-band inputs defined by a respective filter, where the multiple sub-band inputs may be combined together by switches or other methods) and 4 outputs. Similar to that described with respect to the receiver front end (100) of fig. 1, the current gain stages (gm1, … …, gm6) may be configured to tune to various frequency bands. Furthermore, according to another embodiment of the present disclosure, and depending on application requirements, each of the current gain blocks (gm1, … …, gm6) may be connected to one or more of the output loads (LD1, … …, LD 4). This provides the benefits of flexibility, scalability and reusability of the receiver front-end (210) for different applications imposing different requirements. In other words, a generic plan view is provided in which the front-end receiver (210) can be adapted to new applications/requirements without going through a new complete design cycle of such a receiver front-end by enabling minor changes and/or customizations to one or more current gain stages and associated interconnections to the load. To further clarify this, reference is made to the table (300) of fig. 3, which table (300) shows the frequency coverage of the current gain blocks (gm1, … …, gm6) of fig. 2. Table (300) also shows to which output load each of the current gain blocks (gm1, … …, gm6) is connected. For example, the current gain block (gm5) is configured to support a frequency band including 2.5GHz and is connected to an output load (LD1, … …, LD 4). Continuing with the same example, those skilled in the art will appreciate that the current gain block (gm2) may be designed to be reconfigurable (on-the-fly programmable) to support multiple frequency bands. Additionally, designs with different gm blocks per band are also contemplated in accordance with embodiments of the present disclosure. For this example and based on application requirements, the current gain block (gm5) is tuned to a frequency band that includes a center frequency of 2.5 GHz. As another example, the current gain block (gm1) may be configured to support a frequency band including a center frequency of 1.5GHz and simultaneously connected to the output loads (LD1, LD2, LD 3). In view of the above, embodiments are envisioned in accordance with the present disclosure in which multiple input frequency bands are supported and each current gain block can drive one or more output loads simultaneously. In other words, since the current gain block and the output load are separate and independent, a scalable design with the ability to support various frequency bands is made possible by the teachings of the present disclosure.

With further reference to fig. 2-3, those skilled in the art will appreciate that after some adjustments/customizations are performed, the receiver front-end (200), after being arranged as shown in fig. 2, may be reused for different applications with similar form factor requirements. By way of example and with reference to table (300) of fig. 3, if the new application does not require the connection of the current gain (gm3) to the output load (load2), customization including disconnecting the relevant metal and grounding it may be implemented to eliminate such connection and thus adapt the receiver front end (200) of fig. 2 to the new application. Those skilled in the art will appreciate that such customization is easier to implement and more straightforward to implement than a complete redesign of the entire receiver front-end. Further, the layout may be designed such that the base layer is configured to support a range of matching component sizes and to support various frequency bands. In view of this, the teachings of the present disclosure provide design flexibility by reducing the time and effort for adding/removing band inputs and simultaneous outputs.

With further reference to fig. 3 and in accordance with some embodiments of the present disclosure, the output loads (LD1, … …, LD4) are tunable to support frequency bands, including combinations of frequency bands supported by respective current gain blocks. According to another embodiment of the present disclosure, one or more of the current gain blocks connected with a particular output load may be inactive while other current gain blocks connected with the particular output load are active. More particularly, and in accordance with other embodiments of the present disclosure, the current gain blocks connected to a particular load are activated one at a time. As an example and referring to fig. 3, the current gain blocks (gm1, … …, gm5) are connected to the load LD 2. Under operating conditions, the current gain block (gm1) drives the load (LD1), while the other current gain blocks (gm2, … …, gm5) may be inactive/off, which means that current is not driven to the load (LD1) by the current gain blocks (gm2, … …, gm 5). According to another embodiment of the present disclosure, multiple loads may be activated at one time, each load having one gain block activated and operating.

Fig. 4 illustrates an example of frequency bands that may be supported by a receiver front end according to an embodiment of the present disclosure. As shown in fig. 4, the current gain blocks (gm1, … …, gm5) may be tuned to 1.2GHz, 1.8GHz to 1.9GHz, 2.2GHz to 2.3GHz, 2.5GHz to 2.6GHz, and 3.5GHz to 3.8GHz, respectively. According to another embodiment of the present disclosure, any output load connected to the current gain block (gm1, … …, gm5) may be designed to support a wider frequency band than the current gain block. By way of example and with further reference to fig. 4, the output load may be designed to support a range of 1.2GHz to 3.8 GHz.

The combination of fig. 5A-5B shows a receiver input stage (500AB) comprising a current gain block (gm1, … …, gm6) (fig. 5A) and an output load (LD1, … …, LD4) (fig. 5B). The current gain blocks (gm1, … …, gm6) receive input signals from their respective input terminals (in1, … …, in 6). As shown in fig. 5A, each of the current gain blocks (gm1, … …, gm6) may be connected to any one of the output loads (LD1, … …, LD4) through a connection point (load1, … …, load 4). As an example, the connection point load1 of the current gain block gm2 (of fig. 5A) is connected to the connection point load1 of the output load LD1 (of fig. 5B). In other words, the receiver input stage (500A) may receive six different inputs from terminals (in1, … …, in6), and each of the current gain blocks (gm1, … …, gm6) may simultaneously drive one or more of the output loads (LD1, … …, LD4) (fig. 5B, 500B) to provide an output signal at the output terminals (out1, … …, out 4). Fig. 2, referenced 15/846,055 of application No. 12/18, 2017 entitled "switched Multi Input Stacked Transistor Amplifier Tree Structure," the entire contents of which are incorporated herein by reference, shows a split LNA, wherein cascode splitting may be applied to each of the current gain blocks (gm1, … …, gm6) of fig. 5A, connecting the output to one of the output loads (LD1, … …, LD4) or to two of such output loads (if the current gain block is connected using the switch (235) of fig. 2 of the above-incorporated references).

Referring to fig. 5A, the current gain blocks (gm1, … …, gm6) have similar functionality and operate based on similar concepts, although the respective composition of each current gain block may be different from a size and/or performance parameter standpoint. For clarity and to avoid flooding the figure, reference numerals corresponding to constituent elements of only one of the current gain blocks (e.g., gm1) are shown in fig. 5A. Similarly, and referring to fig. 5B, the output loads (LD1, … …, LD4) operate based on the same concept and have similar functions. Therefore, for clarity and ease of reading, only the reference numerals corresponding to the constituent elements of the output load (LD1) are shown in fig. 5B. According to embodiments of the present disclosure, and similar to that described with respect to the current gain blocks (gm1, … …, gm6) of fig. 5A, the respective constituent elements of each of the output loads (LD1, … …, LD4) may be different from one another, with reference to, for example, size, performance parameters, type (e.g., inductance and capacitance), or whether they are present. Furthermore, embodiments may also be devised wherein the composition of each of the output loads may comprise one or more inductances or capacitances or combinations thereof.

Referring to the current gain block (gm1) of fig. 5A, the input signal is coupled to the gain transistors (T1, T2) through the coupling capacitor C1 and the coupling inductor L1. The current gain block (gm1) includes two pairs of cascode transistors (T3, T4) and (T5, T6) with respect to the gain transistors (T1, T2). The cascode transistors (T3, T4) have their sources coupled with the drain of the respective gain transistor T1, and the drains of the cascode transistors (T3, T4) are coupled to the respective output loads (LD1, LD2) of fig. 5B at connection points (load1, load 2). Similarly, the sources of the cascode pairs (T5, T6) are connected to the drains of the respective gain transistors (T2), and the drains of the cascode pairs (T5, T6) are connected to the output loads (LD3, LD4) of fig. 5B at connection points (load3, load 4). The current gain block (gm1) further comprises a variable capacitor (Cgs) and a variable inductor (Ls), the combination of which is used for tuning purposes to optimize RF performance. According to embodiments of the present disclosure, the current gain stages (gm1, … …, gm6) may be constructed using the same or different compositions. By way of example, the respective transistors from one current gain block to another may have the same or different sizes. According to other embodiments of the present disclosure, a bias voltage (not shown in fig. 5A) is provided to the gate of each of the cascode transistors (T3, T4) and (T5, T6). The values of the bias voltages applied to the gates of the cascode transistors (T3, … …, T6) may all be the same or different from each other as desired. During operating conditions and depending on the bias voltage value, one or more of the cascode transistors (T3, … …, T6) may not be activated/turned off, and thus will not drive any current to the respective output loads. More specifically, when the current gain block is connected to a particular load through one of the cascode transistors, the bias voltages of the other cascode transistors cause no other input to flow to the particular load. To further clarify this and referring to fig. 5A, when the current gain block (gm1) is activated and provides current to the output load1(LD1), no other input is provided to the output load1(LD1) by the current gain blocks (gm2, … …, gm 6). This is achieved by adjusting the bias voltage value of the gate of the cascode transistor (T3) of the current gain block (gm2, … …, gm 6). In other words, only one of the individual current gain blocks is connected to the selected output load through the respective cascode transistor.

With continued reference to fig. 5A, and similar to that described with respect to the embodiments of fig. 1-2, the current gain blocks (gm1, … …, gm6) may be designed to be tunable to one or more frequency bands. Each current gain block (gm1, … …, gm6) may be selected to be tuned to a particular frequency band, and each current gain block may be tuned away from one of a plurality of frequency bands to which each block may be tuned, depending on the particular application requirements. The input impedance (Zin) of the current gain block (gm1) of fig. 5A may be calculated according to:

where the term "Re" represents the real part and ω is the angular frequency. The above mentioned equations may be used to set the desired gain and impedance for a given frequency band. As mentioned previously, each current gain block (gm1, … …, gm6) may be designed to have various states corresponding to various frequency bands. Depending on the requirements of the receiver, one of the frequency bands may be selected to be tuned to. Different parameter values may be used to support potentially new and different frequency bands for different applications.

Referring to fig. 5B, the output load (LD1) includes: two stacked transistors (T7, T8); an RF choke (L3) connecting the supply voltage (Vdd) to the source of the transistor (T7); and a variable inductor (L4) and a variable capacitor (C2), the combination of the variable inductor (L4) and the variable capacitor (C2) being used to tune the output load (LD1) to a desired frequency band. A first terminal of the variable inductor (L4) is connected to the variable capacitor (C2) and the drain of the transistor (T8), and a second terminal of the variable inductor (L4) may be connected to a reference voltage or ground. According to an embodiment of the present disclosure, the transistors (T1, … …, T6) of fig. 5A are NMOS transistors, and the transistors (T7, T8) are PMOS transistors. According to an embodiment of the present disclosure, an RF choke (L3) is used to drive the current and has negligible impact on the desired band design. Thus, the RF choke (L3) can be made large enough with metallization so that its shunt impedance does not affect the load impedance. Further, according to an embodiment of the present disclosure, the RF choke (L3) may be a current source or an element exhibiting high impedance at RF frequencies. With further reference to fig. 5A, and without departing from the spirit and scope of the present disclosure, various embodiments in accordance with the present disclosure may be envisioned in which each of the transistors (T1, … …, T6) includes a plurality of stacked transistors. Fig. 5C shows a current gain block (500C) for illustrating such an embodiment. In other words, each of the transistor pairs (T1, T1 '), … …, transistor pairs (T6, T6') represents a stacked transistor.

Referring back to fig. 5A, those skilled in the art will appreciate that another embodiment according to the present disclosure having one or more inputs, one or more outputs, and supporting one or more frequency bands may be designed. To further illustrate this, fig. 5D shows an exemplary receiver front end (500D) with two inputs (in1, in2) and two outputs (out1, out 2). The receiver front-end (500D) further comprises a current gain stage (gm1, gm2) connected to the output load (LD1, LD2) via a connection point (load1, load 2). As shown in fig. 5D, the current gain stage (gm1) may be used to drive one load (e.g., LD1), while the current gain stage (gm2) may be used to drive two loads (LD1, LD2) simultaneously or only one load. According to embodiments of the present disclosure, the current gain stages (gm1, gm2) may each be designed to be tunable to one or more arbitrary frequency bands. Continuing the same example, a schematic portion representing the current gain stages (gm1, gm2) of fig. 5D is shown in dashed lines. This is to compare the current gains (gm1, gm2) of fig. 5D with the corresponding portions of the current gains in fig. 5A, and to show the current gain portions of fig. 5A removed for designing the current gains (gm1, gm2) of fig. 5D.

Fig. 6A shows an LNA (650) including a current gain block (610) and an output load (611) according to an embodiment of the present disclosure. With further reference to fig. 5A-5B, and in view of the description with respect to the receiver input stages (500A and 500B), the LNA (650) essentially represents a combination of any of the current gain blocks (gm1, … …, gm6) of the receiver input stage (500A) and any of the output loads (LD1, … …, LD4) of the receiver input stage (500B). According to an embodiment of the present disclosure, the transistors (T61, T62) are NMOS transistors and the transistors (T64, T63) are PMOS transistors. Those skilled in the art will appreciate that the LNA (650) has a folded architecture, enabling accommodation of potentially stringent voltage headroom requirements. Since different transistor types are used for the transistor pairs (T61, T62) and (T63, T64), design requirements imposing a smaller available voltage margin may be supported. According to an embodiment of the present disclosure, the output load (611) may include one or more cascode transistors.

Fig. 6B shows an LNA (651) according to another embodiment of the present disclosure. Similar to LNA (650) of fig. 6A, LNA (651) includes a current gain block (610). The LNA (651) also includes an output load (621), the output load (621) including a transistor pair (T63 ', T64') arranged in a stacked configuration. According to an embodiment of the present disclosure, the transistors (T63 ', T64') are NMOS transistors. According to an embodiment of the present disclosure, the output load (621) may include one or more cascode transistors.

As previously mentioned, the teachings of the present disclosure provide methods and apparatus for supporting low Noise Figure (NF) in high gain states and step variable gain for high linearity in low gain states. Fig. 7 shows an LNA (700) according to an embodiment of the present disclosure, which operates in three different gain states: a high gain state, a medium gain state, and a low gain state. The principles of operation of LNA (700) are similar to those previously described with respect to LNA (650) of fig. 6A. The LNA (700) further comprises a switch (S1, … …, S6), the state of the switch (S1, … …, S6) being to indicate in which gain state the LNA (700) is configured to operate. Fig. 7 shows three different signal paths (710, 711, 712) for an input signal to travel from an input terminal (in) to an output terminal (out). When the LNA (700) is in the mid-gain state, the switches (S1, S3) are closed and all other switches are open. An input signal entering from an input terminal (in) will pass through a path (710) to an output terminal (out). In other words, in the mid-gain state, the transistors (T1, T2) are bypassed, and the input signal experiences gain through a common gate configuration based on the transistors (T3, T4). The signal path (711) corresponds to a high gain state. In this state, the switches (S2, S6) are closed and all other switches are open. Thus, the input signal experiences gain by: first, by passing through transistors (T1, T2) configured as a common source; and then through transistors (T3, T4) configured as a common gate. When in the low gain state, the switches (S4, S5) are closed and all other switches are open. In this state, corresponding to the signal path (712), all transistors are bypassed and the input signal experiences virtually no gain when traveling from the input terminal (in) to the output terminal (out). Those skilled in the art will appreciate that the switches (S2, S6) are optional and are primarily used for isolation purposes. In other words, the switch (S2) or switch (S6) is closed when their corresponding switch pair (S1, S3) or switch pair (S4, S5) is open. Furthermore, embodiments according to the present disclosure may be designed with only series switches and no switches (S2, S3, S4, S6). According to other embodiments of the present disclosure, the switching network may be configured according to desired isolation requirements.

Fig. 8 shows an LNA (800) designed to operate in a first gain state, a second gain state, and a third gain state. The operational principle of the LNA (800) is based on a concept similar to that described for the LNA (700) of fig. 7, the LNA (800) comprising switches (S81, … …, S86). In the first gain state, the switches (S81, S83) are closed and all other switches are open. Thus, the transistors (T1, T2) are bypassed, and an input signal travelling from the input terminal (in) to the output terminal (out) will experience the first gain state by passing through the transistors (T3, T4) configured as a common gate. In the second gain state, the switches (S84, S86) are closed and all other switches are open. Thus, the transistors (T3, T4) are bypassed, and an input signal travelling from the input terminal to the output terminal will experience the second gain state by passing through the transistors (T1, T2) configured as a common source. In the third gain state, the switches (S81, S83, S84, S86) are closed and the switches (S82, S85) are open. Thus, all transistors (T1, T2, T3, T4) are passed. The first gain state, the second gain state, and the third gain state correspond to the signal paths (810, 811, 812) shown with dashed lines in fig. 8, respectively. The common source and common gate configurations as explained above may be used to support two different gains, depending on design requirements. Those skilled in the art will appreciate that the switches (S82, S85) are optional and are primarily used for isolation purposes. In other words, the switch (S82) or switch (S85) is closed when their corresponding switch pair (S81, S83) or switch pair (S84, S86) is open. Referring to fig. 7 through 8, embodiments according to the present disclosure may be designed to support a plurality of one or more gain states using a plurality of one or more switches. Referring to fig. 8, those skilled in the art will appreciate that there is only one connection point between the current gain stage (including transistors (T1, T2)) and the load portion (including transistors (T3, T4)). This allows for a more modular approach compared to the design shown in, for example, fig. 7, resulting in a simpler layout configuration. By way of example, in a design that includes several current gain stages and several loads, the layout configuration may be made easier because only one connection is required between each current gain stage and each load, as compared to a design that requires more than one connection to connect each current gain stage to each respective load.

Various embodiments of the present invention have been described. It will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.

It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims. (Note that parenthetical reference to claim elements is for ease of reference to such elements and does not by itself indicate a particular required order or enumeration of the elements; further, such reference may be re-used in dependent claims as a reference to additional elements and is not considered to begin with a conflicting sequence of references).