阅读说明：本技术 锁相环电路和包括锁相环电路的时钟发生器 (Phase-locked loop circuit and clock generator including the same ) 是由 郑在洪 郑相敦 李京珉 韩秉基 于 2020-09-29 设计创作，主要内容包括：锁相环(PLL)电路可以包括压控振荡器、亚采样PLL电路和分数分频控制电路。分数分频控制电路可以包括：压控延迟线,路由反馈信号以生成延迟信息；复制压控延迟线,其上施加有延迟信息并且被配置为路由参考时钟信号以生成多个延迟参考时钟信号,每个延迟参考时钟信号被延迟多达不同的相应延迟时间；以及数字时间转换器DTC,被配置为根据多个延迟参考时钟信号生成选择参考时钟信号,并将选择参考时钟信号输出到亚采样PLL电路。(A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional division control circuit. The fractional division control circuit may include: a voltage controlled delay line to route the feedback signal to generate delay information; a replica voltage controlled delay line having delay information applied thereto and configured to route a reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal delayed by up to a different respective delay time; and a digital-to-time converter (DTC) configured to generate a selection reference clock signal from the plurality of delayed reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.)

1. A phase-locked loop, PLL, circuit comprising:

a voltage controlled oscillator configured to generate an output clock signal;

a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a fractional division based phase locking operation based on the output clock signal; and

a fractional division control circuit configured to provide a selection reference clock signal for the fractional division based phase locking operation to the sub-sampling PLL circuit,

wherein the fractional division control circuit comprises:

a voltage controlled delay line configured to route the feedback signal and generate delay information based on the feedback signal;

a replica voltage controlled delay line having the delay information applied thereto and configured to route a reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal delayed by up to a different respective delay time; and

a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delayed reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

2. The PLL circuit of claim 1, wherein the replica voltage controlled delay line comprises a plurality of delay elements having the same characteristics as a plurality of delay elements included within the voltage controlled delay line.

3. The PLL circuit of claim 1, wherein the value of the frequency of the reference clock signal is obtained by applying a target fractional division ratio to the frequency of the output clock signal phase-locked by the sub-sampling PLL circuit.

4. The PLL circuit of claim 1, wherein the fractional division control circuit further comprises a Delay Locked Loop (DLL) circuit connected to the voltage controlled delay line and configured to generate the delay information by locking a delay of the feedback signal that has passed through the voltage controlled delay line.

5. The PLL circuit of claim 4, wherein the delay information comprises a bias voltage of a plurality of delay elements included in the voltage controlled delay line.

6. The PLL circuit of claim 4, wherein the DLL circuit is connected to the replica voltage controlled delay line and is further configured to provide the delay information to the replica voltage controlled delay line.

7. The PLL circuit of claim 4, wherein the voltage controlled delay line comprises a plurality of first delay elements connected in series and each configured to delay a received signal by up to a same delay time to output a delayed feedback signal having a particular phase offset relative to the feedback signal.

8. The PLL circuit of claim 7, wherein the replica voltage controlled delay line comprises a plurality of second delay elements connected in series and configured to delay a received signal by up to a same delay time as the plurality of first delay elements of the voltage controlled delay line, and the plurality of second delay elements are further configured to output the plurality of delayed reference clock signals, gradually delayed from the reference clock signal, to the DTC through respective outputs of the plurality of second delay elements.

9. The PLL circuit of claim 4, wherein the DLL circuit is further configured to: when the phase of the delayed feedback signal falls within a certain locking range by adjusting the degree of delay of the feedback signal caused by the voltage-controlled delay line to prevent harmonic locking, an operation for locking the delay of the feedback signal is started.

10. The PLL circuit of claim 1, wherein the DTC comprises:

a multiplexer configured to select a delayed reference clock signal from the plurality of delayed reference clock signals and output the selected delayed reference clock signal; and

a Fine Time Control (FTC) circuit configured to generate the selection reference clock signal by adjusting a delay of the delayed reference clock signal output from the multiplexer.

11. The PLL circuit of claim 10, wherein a number of bits of the received first bit signal for the select operation of the multiplexer is greater than a number of bits of the received second bit signal for the trim operation of the FTC circuit.

12. The PLL circuit of claim 10, wherein a delay adjustment range of the FTC circuit corresponds to a constant delay time between the plurality of delayed reference clock signals.

13. The PLL circuit of claim 10, further comprising: an auxiliary PLL circuit configured to perform an integer-division-based phase-locking operation on the output clock signal prior to a fractional-division-based phase-locking operation of the sub-sampling PLL circuit,

wherein the DTC is configured to adjust a divide ratio in the integer-divide-based phase-lock operation to generate an output clock signal having a frequency approximately equal to a target fractional divide ratio for the fractional-divide-based phase-lock operation within a particular range.

14. A phase-locked loop, PLL, circuit comprising:

a voltage controlled oscillator configured to generate an output clock signal;

a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a fractional division based phase locking operation based on the output clock signal; and

a fractional division control circuit configured to:

providing a select reference clock signal for the fractional division based phase locking operation to the sub-sampling PLL circuit;

generating delay information on a constant delay time within one period of the feedback signal by performing a delay operation using the feedback signal when the feedback signal has a first frequency;

generating a plurality of delayed reference clock signals gradually delayed by the delay time by using a reference clock signal having a second frequency based on the delay information; and

generating the select reference clock signal using the plurality of delayed reference clock signals.

15. The PLL circuit of claim 14, wherein the first frequency and the second frequency comprise a target fractional division ratio when the phase of the output clock signal is locked by the fractional division based phase locking operation.

16. The PLL circuit of claim 14, wherein the fractional division control circuit comprises a digital time converter DTC, the DTC comprising:

a multiplexer configured to select a delayed reference clock signal from the plurality of delayed reference clock signals and output the selected delayed reference clock signal; and

a Fine Time Control (FTC) circuit configured to generate the selection reference clock signal by adjusting a delay of the delayed reference clock signal output from the multiplexer.

17. The PLL circuit of claim 16, wherein the DTC further comprises a delta sigma modulator and a frequency state machine, wherein the delta sigma modulator is configured to generate a first bit signal for a select operation of the multiplexer and a second bit signal for fine time control.

18. The PLL circuit of claim 14, wherein the fractional division control circuit comprises: a voltage controlled delay line configured to receive the feedback signal to generate the delay information; and a replica voltage controlled delay line configured to receive the reference clock signal to generate the plurality of delayed reference clock signals,

wherein the replica voltage controlled delay line includes a same configuration as that of the voltage controlled delay line to perform a gradual delay operation up to a same delay time as that of the voltage controlled delay line when the delay information is applied to the replica voltage controlled delay line.

19. The PLL circuit of claim 18, wherein the delay information comprises bias voltages of a plurality of delay elements included in the voltage controlled delay line.

20. A clock generator, comprising:

a voltage controlled oscillator configured to generate an output clock signal;

an auxiliary phase-locked loop (PLL) circuit configured to perform an integer-division-based phase-locking operation on the output clock signal;

a sub-sampling PLL circuit configured to perform a fractional division based phase locking operation on the output clock signal after the integer division based phase locking operation; and

a fractional division control circuit configured to provide a selection reference clock signal for the fractional division based phase locking operation to the sub-sampling PLL circuit,

wherein the fractional division control circuit comprises:

a voltage controlled delay line configured to route a feedback signal to generate delay information;

a replica voltage controlled delay line having the delay information applied thereto and comprising the same characteristics as the voltage controlled delay line and configured to route a reference clock signal to generate a plurality of delayed reference clock signals delayed by up to different respective delay times; and

a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delayed reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

Technical Field

The present disclosure relates generally to Phase Locked Loops (PLLs) and clock generators having PLLs, and more particularly, to PLLs including sub-sampling PLLs for fractional division based phase locking to a clock.

Background

A PLL within a clock generator or the like is a circuit that can generate a phase-locked clock signal. For example, the clock signal may be used to transmit data in a transmitter or to recover data in a receiver. In this regard, PLLs may be classified as, for example, a loop PLL or an inductor-capacitor (LC) PLL.

Recently, a technique of locking the phase of a clock by sub-sampling has been applied to a PLL to improve noise characteristics. For example, a sub-sampling PLL may include a phase detector and a Voltage Controlled Oscillator (VCO), where the phase detector sub-samples the output of the VCO with a reference clock. Another technique involves fractional division using a fractional divider in the feedback path. However, this limits the performance of fractional divide operations, since the divider does not divide the clock during sub-sampling operations. Techniques have been introduced to address this limitation by using a digital-to-time converter to implement fractional division during sub-sampling operations. However, using this approach may reduce the performance of the clock generator due to limited resolution and quantization noise.

Disclosure of Invention

Embodiments of the inventive concept provide a Phase Locked Loop (PLL) including a fractional division control circuit having a higher resolution in fractional division phase lock control of a clock and capable of reducing quantization noise, and a clock generator including the PLL.

According to an aspect of the inventive concept, there is provided a Phase Locked Loop (PLL) circuit including: a voltage controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive an output clock signal as a feedback signal and perform a fractional division based phase locking operation based on the output clock signal; and a fractional division control circuit configured to provide a selection reference clock signal for a fractional division based phase lock operation to the sub-sampling PLL circuit. The fractional division control circuit includes: a voltage controlled delay line configured to route a feedback signal to generate delay information; a replica voltage controlled delay line having delay information applied thereto and configured to route a reference clock to generate a plurality of delayed reference clock signals, each delayed reference clock signal delayed by up to a different respective delay time; and a digital-to-time converter (DTC) configured to generate a selection reference clock signal from the plurality of delayed reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

According to another aspect of the inventive concept, there is provided a Phase Locked Loop (PLL) circuit including: a voltage controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive an output clock signal as a feedback signal and perform a fractional division based phase locking operation based on the output clock signal; and a fractional division control circuit configured to provide a selection reference clock signal for a fractional division based phase locked operation to the sub-sampling PLL circuit, wherein the fractional division control circuit is further configured to: generating delay information on a constant delay time within one period of a feedback signal by performing a delay operation using the feedback signal having a first frequency; generating a plurality of delayed reference clock signals gradually delayed by up to a delay time by using a reference clock signal having a second frequency based on the delay information; and generating a selection reference clock signal by using the plurality of delayed reference clock signals.

According to another aspect of the inventive concept, there is provided a clock generator including: a voltage controlled oscillator configured to generate an output clock signal; an auxiliary phase-locked loop (PLL) circuit configured to perform an integer-division-based phase-locking operation on an output clock signal; a sub-sampling PLL circuit configured to perform a fractional division based phase locking operation on the output clock signal after an integer division based phase locking operation; and a fractional division control circuit configured to provide a selection reference clock signal for a fractional division based phase locked operation to the sub-sampling PLL circuit, wherein the fractional division control circuit includes: a voltage controlled delay line configured to route a feedback signal to generate delay information; replicating a voltage controlled delay line having delay information applied thereto and including the same characteristics as the voltage controlled delay line and configured to route a reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal delayed by up to a different respective delay time; and a digital-to-time converter (DTC) configured to generate a selection reference clock signal from the plurality of delayed reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

Drawings

Embodiments of the inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements or features, and in which:

FIG. 1 is a block diagram of a clock generator according to an embodiment;

fig. 2 is a flowchart for describing a phase-locking operation of a phase-locked loop (PLL) circuit according to an embodiment;

fig. 3A and 3B are detailed block diagrams of a clock generator according to an embodiment;

fig. 4 is a circuit diagram of the transconductance circuit of fig. 3A or 3B, according to an embodiment;

fig. 5 is a flow chart for describing a method of performing a fractional division based sub-sampling PLL of a PLL circuit according to an embodiment;

FIG. 6 is a timing diagram depicting a delayed output clock signal that has passed through a voltage controlled delay line and a delayed reference clock signal that has passed through a replica voltage controlled delay line, in accordance with an embodiment;

FIG. 7 is a block diagram for describing the operation of a Delay Locked Loop (DLL) circuit according to an embodiment;

fig. 8A is a block diagram of a DLL circuit according to an embodiment, and fig. 8B is a graph for describing an operation of the DLL circuit of fig. 8A;

fig. 9 and 10 are detailed block diagrams of a digital-to-time converter according to an embodiment;

fig. 11 is a block diagram of a wireless communication device according to an embodiment;

fig. 12 is a schematic diagram illustrating a communication device including a clock generator for performing a phase-locked operation on a clock according to an embodiment; and

fig. 13 is a block diagram of an internet of things (IoT) device, according to an embodiment.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of a clock generator 1 according to an embodiment. The clock generator 1 may comprise a Phase Locked Loop (PLL) circuit PLL _ CKT, wherein the PLL circuit PLL _ CKT may comprise a fractional division control circuit 10, an auxiliary PLL circuit 20, a sub-sampling PLL circuit 30 and a Voltage Controlled Oscillator (VCO) 40. According to some embodiments, VCO 40 may be implemented in various configurations, such as a ring oscillator or an inductance-capacitor (LC) oscillator, which may be used as examples hereinafter. Hereinafter, for convenience of description, the phase delay and the time delay may be used interchangeably. Hereafter, "PLL x" and "DLL y" will refer to "PLL circuit x" and "DLL circuit y", respectively, etc., where "x" or "y" is the previously designated icon for the circuit element in question. Thus, for example, "PLL 20" will refer to PLL circuit 20, while "DLL 14" will refer to DLL circuit 14.

The auxiliary PLL 20 may perform a first phase-locking operation by receiving an output clock signal (more generally, an "oscillation signal") from the VCO 40. Hereinafter, the first phase-locking operation may refer to a phase-locking operation for achieving a difference between the phase of the output clock signal falling within a certain locking range and the phase of the reference clock signal, which is advantageous for the second phase-locking operation for the output clock signal of the sub-sampling PLL 30. Therefore, the first phase-locking operation may be referred to as an auxiliary phase-locking operation before the second phase-locking operation of the sub-sampling PLL 30. The first phase-lock operation performed by the helper PLL 20 may be referred to herein as a helper PLL operation. According to an embodiment, the first phase-locking operation may be an integer-division-based phase-locking operation. In this case, the integer division ratio of the first phase-lock operation may be adjusted to a fractional division ratio approximately equal to the target fractional division ratio, wherein the adjustment is performed by the fractional division control circuit 10 described below. In this regard, the auxiliary PLL 20 may include a frequency divider having a configuration in which the frequency dividing ratio is adjusted by the fractional frequency division control circuit 10. Although fig. 1 shows that the auxiliary PLL 20 applies a particular control voltage signal directly to VCO 40, other circuit arrangements are also available. For example, as shown in fig. 3A described below, the auxiliary PLL 20a may share one loop filter 106 with the sub-sampling PLL 30a, and thus may apply a particular control voltage signal Vctrl to the VCO101 through the loop filter 106.

The sub-sampling PLL 30 may receive an output clock signal (the first phase-locked output clock from the auxiliary PLL 20) from the VCO 40 in a feedback path. Accordingly, the output clock signal in the feedback path may be referred to herein as the feedback signal. The sub-sampling PLL 30 may use the feedback signal to perform sub-sampling. The sub-sampling PLL 30 may perform a fractional division based phase locking operation (or a second phase locking operation) on the feedback signal, and the sub-sampling PLL 30 may receive a selection reference clock signal for the fractional division based locking operation from the fractional division control circuit 10. Hereinafter, the fractional division control circuit 10 according to the embodiment will be described.

The fractional division control circuit 10 may include a Digital Time Converter (DTC)12, a Delay Locked Loop (DLL) circuit 14, a voltage controlled delay line 16, and a replica voltage controlled delay line 18. The voltage controlled delay line 16 may receive an output clock signal as a feedback signal from the VCO 40, and may output a feedback signal delayed by up to a maximum phase based on the received feedback signal. The maximum phase may be different according to the type of input/output signal of the VCO 40 or a target fractional division ratio. As an example, the maximum phase may be 360 degrees when the input/output signal of VCO 40 is a single-ended signal, and as another example, the maximum phase may be 180 degrees when the input/output signal of VCO 40 is a differential signal. Although it is assumed hereinafter for convenience of description that the internal signal of the PLL _ CKT is a single-ended signal, other types of signals are available. For example, the internal signal of the PLL _ CKT may alternatively be a differential signal. According to an embodiment, the voltage controlled delay line 16 may include a plurality of first delay elements connected in series with each other, and the voltage controlled delay line 16 may have a configuration designed according to the number of phases that the selection reference clock signal provided to the sub-sampling PLL 30 may have. For example, as the number of phases that the selected reference clock signal may have increases, the number of first delay elements included in the voltage controlled delay line 16 may also increase.

According to an embodiment, the DLL 14 may be connected to the voltage controlled delay line 16 and the delay information may be generated by locking the delay of the feedback signal delayed by the voltage controlled delay line 16. For example, the DLL 14 may generate the delay information by a delay lock operation on the feedback signal through the voltage controlled delay line 16. The delay information may be used for time delay (or phase delay) control at a first frequency (or high frequency) of the feedback signal (or the output clock signal of VCO 40). That is, the delay information may be used to control the feedback signal to delay it by a maximum value of a constant delay time corresponding to one cycle of the feedback signal through the voltage controlled delay line 16. For example, the delay information may include bias voltages of a plurality of first delay elements included in the voltage controlled delay line 16. A bias voltage may be applied to the delay element to allow the delay element to constantly delay the signal by a delay up to a target delay time despite changes in operating environment or process, voltage, and temperature (PVT) conditions of the clock generator 1 or the PLL _ CKT. The DLL 14 may provide the delay information to a replica voltage controlled delay line 18. The DLL 14 may perform a delay locking operation to prevent harmonic locking, thereby generating accurate delay information. For example, the DLL 14 may start an operation for locking the delay of the feedback signal when the phase of the delayed feedback signal falls within a certain locking range by adjusting the degree of delay of the feedback signal caused by the voltage controlled delay line 16.

According to one embodiment, the replica voltage controlled delay line 18, which is a replica of the voltage controlled delay line 16, may include a plurality of second delay elements having the same configuration or characteristics as the plurality of first delay elements included in the voltage controlled delay line 16. The delay information received from the DLL 14 may be applied to the replica voltage controlled delay line 18, and the replica voltage controlled delay line 18 may generate a plurality of delayed reference clock signals by receiving a reference clock signal, each delayed reference clock signal being delayed by up to a different respective delay time. Each of the plurality of delayed reference clock signals may be delayed by a different respective amount. The reference clock signal may have a second frequency lower than the first frequency (or high frequency) of the feedback signal (or the output clock signal of the VCO 40), and a ratio of the first frequency of the output clock signal (or the feedback signal) phase-locked by the sub-sampling PLL 30 to the second frequency of the reference clock signal may have a target fractional division ratio. For example, the replica voltage controlled delay line 18 may include a plurality of second delay elements connected in series and having delay information applied to delay the received signal by up to the same delay time as the plurality of first delay elements of the voltage controlled delay line 16. The received signal may be delayed by the same amount as the plurality of first delay elements of the voltage controlled delay line 16. The replica voltage controlled delay line 18 may output a plurality of delayed reference clock signals, which are gradually delayed from the received reference clock signal by a delay time, to the DTC 12. For example, the plurality of delayed reference clock signals may be output to the DTC 12 by replicating respective outputs of a plurality of second delay elements of the voltage controlled delay line 18.

According to an embodiment, the DTC 12 may receive a plurality of delayed reference clock signals from the replica voltage controlled delay line 18, and may generate a select reference clock signal from the plurality of delayed reference clock signals and output the select reference clock signal to the sub-sampling PLL 30. The DTC 12 may generate a select reference clock signal having a phase adjusted based on a target fractional division ratio. For example, the DTC 12 may select one delayed reference clock signal from a plurality of delayed reference clock signals, and may generate the selected reference clock signal by finely adjusting the delay of the selected delayed reference clock signal. The fine delay range of the selected delayed reference clock signal in the DTC 12 may correspond to a constant delay time between multiple delayed reference clock signals. For example, the fine delay range of the selected delayed reference clock signal in the DTC 12 may be limited to a constant delay time. The DTC 12 may generate an a-bit signal (where a is an integer of 1 or higher) for internally selecting one of a plurality of delayed reference clock signals, and may generate a B-bit signal (where B is an integer of 1 or higher) for adjusting the delay of the selected delayed reference clock signal. The number of bits of the a-bit signal may be greater than the number of bits of the B-bit signal, lower than the number of bits of the B-bit signal, or the same as the number of bits of the B-bit signal.

According to the above-described embodiments, the output clock signal of the VCO 40 may be phase-locked by the sub-sampling PLL 30, and the output clock signal may be output to a sampling block (e.g., an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC)).

It should be noted here that the implementation example of the clock generator 1 shown in fig. 1 is merely an example. The minimum configuration to which the inventive concept can be applied can be designed in various other ways.

The PLL circuit PLL _ CKT according to the embodiment may generate delay information through the voltage controlled delay line 16 by receiving an output clock signal as a feedback signal from the VCO 40, and may use a plurality of delayed reference clock signals generated by providing the delay information to the replica voltage controlled delay line 18 in a phase locking operation based on fractional division, thereby effectively improving resolution of selecting a phase of the reference clock signal. Since the selection reference clock signal is generated by using the output clock signal from the VCO 40, jitter of the output clock signal can be reflected in the selection reference clock signal. The overall jitter performance of PLL CKT may be improved by mitigating timing skew between the select reference clock signal received by sub-sampling PLL circuit 30 and the output clock signal of VCO 40.

Fig. 2 is a flowchart for describing a phase-locking operation of the PLL circuit according to the embodiment. Hereinafter, fig. 2 will be described with reference to fig. 1.

Referring to fig. 2, the PLL circuit PLL _ CKT may perform a first phase locking operation on an output clock signal output from the VCO 40 by using the auxiliary PLL circuit 20 in operation S100. According to an embodiment, the first phase-locking operation may be an integer-division-based phase-locking operation. However, in other embodiments, the first phase-lock operation may be a phase-lock operation based on fractional division, and the fractional division ratio of the first phase-lock operation may be adjusted by the fractional division control circuit 10. The auxiliary PLL circuit 20 may perform a first phase-locking operation for locking the phase of the output clock signal of the VCO 40, and may perform the first phase-locking operation to achieve a difference between the phase of the divided output clock signal and the phase of the reference clock signal within a certain range (hereinafter, referred to as a "dead zone"). The auxiliary PLL circuit 20 may be deactivated when a difference between a phase of the divided output clock signal and a phase of the reference clock signal is in a dead zone.

In operation S110, the PLL _ CKT may perform a second phase locking operation on the output clock signal output from the VCO 40 by using the sub-sampling PLL circuit 30. According to the embodiment, the second phase-locking operation may be a phase-locking operation based on fractional division, and the fractional division ratio of the second phase-locking operation may be adjusted by the fractional division control circuit 10. For example, the sub-sampling PLL 30 may receive the selection reference clock signal from the fractional division control circuit 10, and thus may perform the second phase-locking operation based on the selection reference clock signal.

The fractional division control circuit 10 according to the embodiment may receive the output clock signal from the VCO 40, and may generate the delay information at the frequency of the output clock signal by using the DLL 14 and the voltage controlled delay line 16. The fractional division control circuit 10 may apply delay information to the replica voltage controlled delay line 18 and may generate a plurality of delayed reference clock signals from the reference clock signal by using the replica voltage controlled delay line 18. The fractional division control circuit 10 may generate a selection reference clock signal from the plurality of delayed reference clock signals by using the DTC 12, and may output the selection reference clock signal to the sub-sampling PLL 30.

Fig. 3A and 3B are detailed example block diagrams of clock generator 100 according to various embodiments. Hereinafter, although signals are simply illustrated in fig. 3A and 3B for convenience of explanation, in some embodiments, the VCO101 may output differential signals having phases opposite to each other via two lines, and the clock generator 100 may be implemented to perform a phase-locking operation by using the differential signals. Fig. 3B shows additional signals and signal paths that may be implemented in the clock generator 100 of fig. 3A.

Referring to fig. 3A, the clock generator 100 may include an auxiliary PLL circuit 20a, an FFD control circuit 10a, a sub-sampling PLL circuit 30a (which are examples of the respective circuits 20, 10, and 30 in fig. 1), and a VCO 101. The auxiliary PLL circuit 20a may include a frequency divider 102, a phase frequency detector 103, a dead band circuit 104, and a charge pump 105. Sub-sampling PLL circuit 30a may include loop filter 106, sampler 107, transconductance ("Gm") circuit 108, and pulse generator 109. The FFD control circuit 10a may include a voltage controlled delay line 110, a DLL circuit 111, a replica voltage controlled delay line 112, and a DTC113 a.

The clock generator 100 differs slightly from the clock generator 1 in fig. 1 in that: the auxiliary PLL circuit 20 and the sub-sampling PLL circuit 30 of fig. 1 may share a loop filter 106, with the loop filter 106 included as part of the sub-sampling PLL circuit 30a of fig. 3A.

The VCO101 may provide the output clock signal VCO _ clk to the frequency divider 102, where the frequency divider 102 may divide the output clock signal VCO _ clk, and may provide the divided clock DIV _ clk to the phase frequency detector 103. The divider 102 may be implemented as an integer divider. The phase frequency detector 103 may receive each of the reference clock signal Ref _ clk and the divided clock DIV _ clk, and may provide a detection result to the dead zone circuit 104 by detecting a phase difference ("phase offset") between the reference clock signal Ref _ clk and the divided clock DIV _ clk. Although fig. 3A shows phase frequency detector 103 receiving reference clock signal Ref _ clk from DTC113A, in other examples, reference clock signal Ref _ clk may be received through a different path. The deadband circuit 104 may determine whether the phase difference between the reference clock signal Ref _ clk and the divided clock DIV _ clk is within a preset deadband. When the phase difference is within the dead band, the dead band circuit 104 may complete the first phase-locked operation along with other circuits of the auxiliary PLL circuit 20a, and may deactivate the auxiliary PLL circuit 20 a. When the phase difference is outside the dead zone, the dead zone circuit 104 may supply the detection result received from the phase frequency detector 103 to the charge pump 105. Based on the detection result, the charge pump 105 may generate the control voltage signal Vctrl and may supply the control voltage signal Vctrl to the VCO 101. As described above, the first phase-lock operation may be repeated using the frequency divider 102, the phase frequency detector 103, the dead zone circuit 104, and the charge pump 105 until the phase difference between the reference clock signal Ref _ clk and the divided clock DIV _ clk falls within the dead zone. Subsequently, to fine phase-lock of the output clock signal VCO _ clk, the clock generator 100 may perform a second phase-locking operation using the sub-sampling PLL circuit.

For example, VCO101 may provide an output clock signal VCO _ clk (and thus may be referred to herein as a feedback signal) phase-locked by the first phase-locked operation to sampler 107 in a feedback path. Sampler 107 may receive each of output clock signal VCO _ clk and reference clock signal Ref _ clk, and may generate a sampled voltage signal V _ sam by sampling output clock signal VCO _ clk based on reference clock signal Ref _ clk. Although fig. 3A shows the sampler 107 receiving the reference clock signal Ref _ clk from the DTC113A, the inventive concept is not limited thereto and the reference clock signal Ref _ clk may be received through another path. Sampler 107 may be referred to as a sub-sampling phase detector. The transconductance circuit 108 may receive the sampled voltage signal V _ sam, may convert the sampled voltage signal V _ sam into a sampled current signal I _ sam based on the pulse signal Pul received from the pulse generator 109, and may output the sampled current signal I _ sam to the loop filter 106. The loop filter 106 may generate the control voltage signal Vctrl by filtering the sampled current signal I _ sam. The pulse generator 109 may receive the selection reference clock signal Ref _ clk _ sel from the DTC113a, and may generate the pulse signal Pul based on the selection reference clock signal Ref _ clk _ sel. A detailed example configuration of the pulse generator 109 is described below with reference to fig. 4, and an operation of generating the selection reference clock signal Ref _ clk _ sel will be described below.

The voltage controlled delay line 110 may receive the output clock signal VCO _ clk from the VCO101 and output the following based on the output clock signal VCO _ clk: (i) a first delayed output clock signal VCO _ clk _ Φ 1 that is the same as the output clock signal VCO _ clk (thereby effectively routing the output clock signal VCO _ clk therethrough), and (ii) a second delayed output clock signal VCO _ clk _ Φ n having a particular phase difference Φ n- Φ 1 relative to the first delayed output clock signal VCO _ clk _ Φ 1. The voltage controlled delay line 110 may include a plurality of first delay elements connected in series, and the second delayed output clock signal VCO _ clk _ Φ n may be a signal generated by sequentially passing the output clock signal VCO _ clk through all of the plurality of first delay elements.

The DLL circuit 111 may perform a delay locking operation using the first and second delayed output clock signals VCO _ clk _ Φ 1 and VCO _ clk _ Φ n received from the voltage-controlled delay line 110, and thus may generate delay information VDLL on the output clock signal VCO _ clk. For example, when the number of first delay elements of the voltage controlled delay line 110 is "K", the delay information VDLL may include information for controlling each of the first delay elements to delay the signal by up to (Φ n- Φ 1)/K degrees. The delay information VDLL may be a bias voltage applied to each of the plurality of first delay elements of the voltage controlled delay line 110. For example, when the second delayed output clock signal VCO _ clk _ Φ n has a phase difference of 360 degrees with respect to the first delayed output clock signal VCO _ clk _ Φ 1, and the number of first delay elements of the voltage controlled delay line 110 is 32, the delay information may include information for controlling each of the first delay elements to delay the signal up to 11.25 degrees (a delay of time corresponds to a phase difference of 11.25 degrees).

The DLL circuit 111 can provide delay information VDLL to the replica voltage controlled delay line 112. The replica voltage controlled delay line 112, which is a replica of the voltage controlled delay line 16, may include a plurality of second delay elements having the same configuration or characteristics as the plurality of first delay elements included in the voltage controlled delay line 110. The delay information VDLL received from the DLL circuit 111 can be applied to the replica voltage controlled delay line 112. The replica voltage controlled delay line 112 may receive a reference clock signal Ref _ clk and generate a plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n based on the reference clock signal Ref _ clk; and may output a plurality of delayed reference clock signals Ref _ clk _ Φ 1 through Ref _ clk _ Φ n to the DTC113 a. The delay time cells in the replica voltage controlled delay line 112 that are applied with the delay information VDLL can be the same as or similar to the delay time cells in the voltage controlled delay line 110. For example, when it is assumed that the delay time cell of the voltage controlled delay line 110 is a delay time corresponding to a phase difference of 11.25 degrees with respect to the output clock signal VCO _ clk, the delay time cell in the replica voltage controlled delay line 112 to which the delay information VDLL is applied may be the same as or similar to a delay time corresponding to a phase difference of 11.25 degrees with respect to the output clock signal VCO _ clk. In this regard, the nth delayed reference clock signal Ref _ clk _ Φ n generated by delaying the reference clock signal Ref _ clk the longest through the replica voltage controlled delay line 112 may be delayed from the reference clock signal Ref _ clk by a delay time corresponding to a phase difference of 360 degrees with respect to the output clock signal VCO _ clk.

The DTC113a may generate a selection reference clock signal Ref _ clk _ sel from a plurality of delay reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n output from the replica voltage-controlled delay line 112 based on a Frequency Coarse Value (FCV) and a Frequency Fine Value (FFV). For example, the FCV and FFV may be bit data, and when it is assumed that the FCV and FFV are a-bit data and B-bit data, respectively, the DTC113a may generate the selection reference clock signal Ref _ clk _ sel in [ equation 1] for the fractional division based phase locking operation.

The FCV, FFV, and frequency division information DIV _ N described below are external input signals from the outside that are applied to determine the frequency of the PLL itself, and may be adjusted to allow the PLL to cover a wide band.

[ equation 1]

In [ equation 1]]In (F)_{VCO_clk}Is the frequency of the output clock signal VCO _ clk, F_{Ref_clk}Refers to the frequency of the reference clock signal Ref _ clk, and N refers to a specific integer division ratio. For example, N may correspond to an integer divide ratio of divider 102. F_{VCO_clk}And F_{Ref_clk}The target fractional division ratio may be achieved by selecting the reference clock signal Ref _ clk _ sel generated based on the FCV and FFV. For example, the integer divide ratio may be determined by adjusting N for a PLL having a target fractional divide ratio, and the fractional divide ratio may be determined by adjusting FCV (a-bit data) and FFV (B-bit data).

Referring to fig. 3B, the DTC 113B according to the embodiment may also receive division information DIV _ N indicating an integer division ratio N of the divider 102, and thus may provide a division ratio control signal DIV _ CS to the divider 102 to perform a division operation at a fractional division ratio close to a target fractional division ratio. The DTC113 b may supply the division ratio control signal DIV _ CS to the frequency divider 102 during the first phase-lock operation using the auxiliary PLL circuit 20a, and the frequency divider 102 may be implemented in a configuration capable of changing the division ratio based on the division ratio control signal DIV _ CS.

Although fig. 3A and 3B illustrate the charge pump 105 and the transconductance circuit 108 as separate configurations, this is merely an embodiment, and thus the inventive concept is not limited thereto, and the transconductance circuit 108 of the clock generator 100 may replace the charge pump 105.

Fig. 4 is a circuit diagram of the transconductance circuit 108 of fig. 3A or 3B, according to an embodiment.

Referring to fig. 4, the transconductance circuit 108 may include first and second current sources IS1 and IS2 and first and second switch circuits SW1 and SW 2. The first current source IS1 may generate a positive current signal by converting the positive sampled voltage signal V _ samP received from the sampler 107. The second current source IS2 may generate a negative current signal by converting the negative sampling voltage signal V _ samN received from the sampler 107. The first and second switch circuits SW1 and SW2 may perform a switching operation in response to the pulse signal pul by receiving the pulse signal pul from the pulse generator 109. Thus, the transconductance circuit 108 may generate the sampled current signal I _ sam and output the sampled current signal I _ sam to the loop filter 106. For example, the sampled current signal I _ sam of the transconductance circuit 108 may be determined by a positive current signal amplitude of the first current source IS1, a negative current signal amplitude of the second current source IS2, and a duty cycle of the pulse signal pul. For example, when assuming that the duty ratio of the pulse signal pul IS 20%, the amplitude of the sampled current signal I _ sam may be up to 20% of the amplitude of the positive current signal of the first current source IS 1.

Fig. 5 is a flow chart for describing a method of performing a fractional division based sub-sampling PLL of a PLL circuit according to an embodiment.

Referring to fig. 5, the PLL circuit may obtain delay information on an output clock signal from the VCO by using a voltage controlled delay line in operation S200. In operation S210, the PLL circuit may apply delay information to the replica voltage controlled delay line. In operation S220, the PLL circuit may generate a selection reference clock signal from a plurality of delayed reference clock signals generated by the replica voltage-controlled delay line. In operation S230, the PLL circuit may perform a fractional division based phase locking operation by performing a sub-sampling PLL using the selection reference clock signal.

Fig. 6 is a timing diagram for describing the delayed output clock signal VCO _ clk _ D that has passed through the voltage controlled delay line and the delayed reference clock signal Ref _ clk _ D that has passed through the replica voltage controlled delay line according to an embodiment. Hereinafter, for ease of understanding, description will be made with reference to fig. 3A.

Referring to fig. 6, as described above, the voltage controlled delay line 110 may include a plurality of first delay elements, and as the output clock signal VCO _ clk sequentially passes through the plurality of first delay elements, the output clock signal VCO _ clk may be gradually delayed to a first time t1 (or a first phase Φ 1), a second time t2 (or a second phase Φ 2), a third time t3 (or a third phase Φ 3), … …, an (m-1) th time t (m-1) (or an (m-1) th phase Φ (m-1)), an mth time tm (or an mth phase Φ m), and the like. As shown in fig. 3A, the voltage controlled delay line 110 may be configured to output the finally delayed second delayed output clock signal VCO _ clk _ Φ n and the first delayed output clock signal VCO _ clk _ Φ 1 having the same phase as the output clock signal VCO _ clk to the DLL circuit 111. The delay information VDLL generated by the DLL circuit 111 may be used to control the replica voltage controlled delay line 112 to gradually delay the reference clock signal Ref _ clk by up to the same delay time as the voltage controlled delay line 110.

The replica voltage controlled delay line 112 may include a plurality of second delay elements, and as the delay information VDLL is applied to the plurality of second delay elements and the reference clock signal Ref _ clk sequentially passes through the plurality of second delay elements, the reference clock signal Ref _ clk may be gradually delayed to a first time t1, a second time t2, a third time t3, … …, an (m-1) th time t (m-1), an mth time tm, and the like. The replica voltage controlled delay line 112 may be configured to output a plurality of delayed reference clock signals Ref _ clk _ Φ 1 through Ref _ clk _ Φ n. As described above, as the delay information VDLL is applied to the replica voltage controlled delay line 112, the reference clock signal Ref _ clk may be sequentially delayed by up to a more fragmented delay time. Therefore, the resolution of selecting the phase of the reference clock signal can be improved, and further, the rise in circuit complexity does not increase.

Fig. 7 is a block diagram for describing the operation of the DLL circuit 111a according to the embodiment. The DLL circuit 111a of fig. 7 may include a phase frequency detector 111a _1 and a charge pump 111a _ 2. The voltage controlled delay line 110a may include a plurality of first delay elements D11-Dn 1. The replica voltage controlled delay line 112a may include a plurality of second delay elements D12-Dn 2. The replica voltage controlled delay line 112a, which is a replica of the voltage controlled delay line 110a, may include a plurality of second delay elements D12 to Dn2, the plurality of second delay elements D12 to Dn2 having the same configuration or characteristics as the plurality of first delay elements D11 to Dn1 included in the voltage controlled delay line 110 a. For example, the number of the second delay elements D12 to Dn2 may be the same as the number of the first delay elements D11 to Dn 1.

The voltage controlled delay line 110a may receive the first delayed output clock signal VCO _ clk _ Φ 1 and may output the second delayed output clock signal VCO _ clk _ Φ n delayed by the plurality of first delay elements D11 to Dn1 to the DLL circuit 111 a. For example, the first delayed output clock signal VCO _ clk _ Φ 1 may be the same signal as the output clock signal output from the VCO, and the second delayed output clock signal VCO _ clk _ Φ n may have a certain phase difference (e.g., 360 degrees) with respect to the first delayed output clock signal VCO _ clk _ Φ 1. The phase frequency detector 111a _1 may receive the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n, and may provide the detection result DR to the charge pump CP by detecting a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n. Based on the detection result DR, the charge pump CP may adjust delay information (or bias voltage) VDLL and provide the delay information VDLL to the plurality of first delay elements D11 to Dn 1. The DLL circuit 111a may repeat the above-described delay locking operation until the phases of the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n are identical to each other.

The DLL circuit 111a may provide delay information VDLL generated due to the repeated delay locking operation to the plurality of second delay elements D12 to Dn2 that replicate the voltage controlled delay line 112 a. The replica voltage controlled delay line 112a may delay the received reference clock signal Ref _ clk step by step and may output each of a plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n. The plurality of delayed reference clock signals Ref _ clk _ Φ 1 through Ref _ clk _ Φ n may be used to generate a select reference clock signal required for fractional division based phase lock operation using a sub-sampling PLL.

Fig. 8A is a block diagram of a DLL circuit 111B according to an embodiment, and fig. 8B is a graph for describing an operation of the DLL circuit 111B of fig. 8A.

Referring to fig. 8A, the DLL circuit 111b may include a first switch SW1, a second switch SW2, a phase frequency detector 111b _1, a charge pump 111b _2, a lock detector 111b _3, and a state machine 111b _ 4. Before performing the delay locking operation using the charge pump 111b _2, the DLL circuit 111b may adjust the delay of the second delayed output clock signal VCO _ clk _ Φ n to fall within a certain locking range, so that harmonic locking may be prevented. For example, the phase frequency detector 111b _1 may receive the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n from the voltage controlled delay line 110, and may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n and provide the first detection result DR1 to the lock detector 111b _ 3. The lock detector 111b _3 may be activated in response to the first activation signal EN1, may detect whether the phase of the second delayed output clock signal VCO _ clk _ Φ n falls within a certain lock range based on the first detection result DR1, and may provide the lock detection result LDR to the state machine 111b _ 4. Based on the lock detection result LDR, the state machine 111b _4 can provide the delay control signal DL to the voltage controlled delay line 110. The state machine 111b _4 may also generate a second activation signal EN2 based on the lock detection result LDR and provide the second activation signal EN2 to the first switch SW1 and the second switch SW 2.

As an example, when the phase of the second delayed output clock signal VCO _ clk _ Φ n does not fall within a specific locking range, the state machine 111b _4 may generate the second activation signal EN2 having a high level, and may generate a new delay control signal DL for adjusting the delay of the second delayed output clock signal VCO _ clk _ Φ n differently from before. The phase frequency detector 111b _1, the lock detector 111b _3, and the state machine 111b _4 may repeat the above operations until the phase of the second delayed output clock signal VCO _ clk _ Φ n falls within a certain lock range.

As another example, when the phase of the second delayed output clock signal VCO _ clk _ Φ n falls within a certain locking range, the state machine 111b _4 may generate the second activation signal EN2 having a low level and may stop the operation of adjusting the delay of the second delayed output clock signal VCO _ clk _ Φ n. Subsequently, the phase frequency detector 111b _1 may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n, and provide the second detection result DR2 to the charge pump 111b _ 2. Based on the second detection result DR2, the charge pump 111b _2 may generate delay information VDLL.

With further reference to fig. 8B, during the intervals "t 0" to "t 1", the state machine 111B _4 may generate the second activation signal EN2 having a high level and the delay control signal DL having a value "D1". In this regard, the phase frequency detector 111b _1 may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the second delayed output clock signal VCO _ clk _ Φ n, and provide the first detection result DR1 to the lock detector 111b _ 3. Based on the first detection result DR1, the lock detector 111b _3 may detect that the phase of the second delayed output clock signal VCO _ clk _ Φ n does not fall within the lock range, and may provide a lock detection result LDR to the state machine 111b _ 4. During the intervals "t 1" to "t 2", the state machine 111b _4 may generate the second activation signal EN2 having a high level and the delay control signal DL having a value "D2". In this regard, the phase frequency detector 111b _1 may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the delayed adjusted second delayed output clock signal VCO _ clk _ Φ n, and provide the first detection result DR1 to the lock detector 111b _ 3. Based on the first detection result DR1, the lock detector 111b _3 may detect that the phase of the second delayed output clock signal VCO _ clk _ Φ n does not fall within the lock range, and may provide a lock detection result LDR to the state machine 111b _ 4. During the intervals "t 2" to "t 3", the state machine 111b _4 may generate the second activation signal EN2 having a high level and the delay control signal DL having a value "D3". The phase frequency detector 111b _1 may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the delayed re-adjusted second delayed output clock signal VCO _ clk _ Φ n, and provide the first detection result DR1 to the lock detector 111b _ 3. Based on the first detection result DR1, the lock detector 111b _3 may detect that the phase of the second delayed output clock signal VCO _ clk _ Φ n does not fall within the lock range, and may provide a lock detection result LDR to the state machine 111b _ 4. During the intervals "t 3" to "t 4", the state machine 111b _4 may generate the second activation signal EN2 having a high level at the beginning and the delay control signal DL having a value "D4". The phase frequency detector 111b _1 may detect a phase difference between the first delayed output clock signal VCO _ clk _ Φ 1 and the delayed re-adjusted second delayed output clock signal VCO _ clk _ Φ n, and provide the first detection result DR1 to the lock detector 111b _ 3. Based on the first detection result DR1, the lock detector 111b _3 may detect that the phase of the second delayed output clock signal VCO _ clk _ Φ n falls within the lock range, and may provide a lock detection result LDR to the state machine 111b _ 4. The state machine 111b _4 may generate the second activation signal EN2 transitioning to a low level after a certain time from "t 3", and in response to the second activation signal EN2 having a low level, the DLL circuit 111b may perform a delay locking operation for generating the delay information VDLL.

Fig. 9 and 10 are detailed block diagrams of DTCs 113a according to embodiments.

Referring to fig. 9, the DTC113a may include a delta sigma modulator 113a _1, a frequency state machine 113a _2, a multiplexer 113a _3, and a fine time control circuit 113a _ 4.

The delta sigma modulator 113a _1 may receive the FFV and may generate a Digital Sequence (DS) based on the FFV and provide the DS to the frequency state machine 113a _ 2. The FFV may be used to specify a desired frequency synthesis ratio to perform a phase-lock operation according to a target fractional division ratio. The delta-sigma modulator 113a _1 may generate the DS at the same time-average ratio corresponding to the FFV.

Frequency state machine 113a _2 may receive DS and FCV, and may generate a Phase Control Signal (PCS) for controlling the phase of select reference clock signal Ref _ clk _ sel based on DS and FCV. Frequency state machine 113a _2 may provide the Most Significant Bit (MSB) portion of the PCS to multiplexer 113a _3_MSB(hereinafter, referred to as a first phase control signal), and a Least Significant Bit (LSB) portion of the PCS may be provided to the fine time control circuit 113a _4_LSB(hereinafter referred to as a second phase control signal).

The multiplexer 113a _3 may receive a plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n, and may be based on the first phase control signal PCS_MSBOne of the plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n is selected, and the selected delayed reference clock signal Ref _ clk _ Φ m is supplied to the fine time control circuit 113a _ 4. In this regard, the first phase control signal PCS may be implemented with bit data matched to the number of the plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n_MSB. For example, when the number of the plurality of delayed reference clock signals Ref _ clk _ Φ 1 to Ref _ clk _ Φ n is 32, the first phase control signal PCS may be implemented with 5-bit data_MSB。

The fine time control circuit 113a _4 may receive the selected delayed reference clock signal Ref _ clk _ Φ m and the second phase control signal PCS_LSBAnd may be based on the second phase control signal PCS_LSBThe selection reference clock signal Ref _ clk _ sel is generated by finely adjusting the delay time (or phase) of the selected delay reference clock signal Ref _ clk _ Φ m. The delay adjustment range of the selected delayed reference clock signal Ref _ clk _ Φ m adjusted by the fine time control circuit 113a _4 may be limited to the plurality of delayed reference clock signals Ref _ clk _ Φ 1 to RefClk _ Φ n. For example, when the delay time between the first delayed reference clock signal Ref _ clk _ Φ 1 and the second delayed reference clock signal Ref _ clk _ Φ 2 is "5", the delay adjustment range may be limited to "5".

Timing problems may occur in the frequency state machine 113a _2 due to the continuous update of the PCS. Therefore, to solve the above-described problem, the delta-sigma modulator 113a _1 may be synchronized with the selection reference clock signal Ref _ clk _ sel output from the fine time control circuit 113a _4 to generate the DS, and the frequency state machine 113a _2 may be synchronized with the nth delayed reference clock signal Ref _ clk _ Φ n to generate the PCS.

With further reference to fig. 10, the DTC113 b may include a delta sigma modulator 113b _1, a frequency state machine 113b _2, a multiplexer 113b _3, and a fine time control circuit 113b _ 4. Hereinafter, the frequency state machine 113b _2 that also performs additional operations compared to the frequency state machine 113a _2 of fig. 9 will be mainly described.

The frequency state machine 113b _2 may also receive frequency division information DIV _ N indicating an integer division ratio of the frequency divider 102 (of fig. 3A) in the auxiliary PLL circuit, and thus may generate a division ratio control signal DIV _ CS for controlling the frequency divider 102 (of fig. 3A) to perform a frequency division operation at a fractional division ratio that approximates the target fractional division ratio. For example, during a first phase-lock operation using the auxiliary PLL circuit, frequency state machine 113b _2 may generate a division ratio control signal DIV _ CS and provide the division ratio control signal DIV _ CS to divider 102 (of fig. 3A). In this regard, the frequency divider 102 (of fig. 3A) may include a configuration capable of changing the frequency division ratio based on the frequency division ratio control signal DIV _ CS.

Fig. 11 is a block diagram of a wireless communication device 1000 according to an embodiment. The wireless communication device 1000 may include a digital signal processor 1100, a DAC 1200, an ADC 1300, a Radio Frequency Integrated Circuit (RFIC)1400, a front end module 1500, and an antenna 1600. The digital signal processor 1100 may process signals including information to be transmitted or received according to a set communication scheme. For example, the digital signal processor 1100 may process signals according to a communication scheme such as Orthogonal Frequency Division Multiplexing (OFDM), Orthogonal Frequency Division Multiple Access (OFDMA), Wideband Code Division Multiple Access (WCDMA), or high speed packet access + (HSPA +).

The DAC 1200 may convert a digital signal including information to be transmitted into an analog signal and may provide the converted transmission signal to the RFIC 1400. The ADC 1300 may convert an analog signal received from the RFIC 1400 into a digital signal, and may provide the converted digital signal to the digital signal processor 1100.

RFIC 1400 may include a first mixer 1410, a second mixer 1420, and a PLL circuit 1430. The RFIC 1400 may generate a Radio Frequency (RF) signal by up-converting the frequency of a transmission signal in a baseband received from the DAC 1200 using the first mixer 1410 and the PLL 1430. The RFIC 1400 may generate a baseband signal by down-converting the frequency of a reception signal in an RF band received from the front end module 1500 using the second mixer 1420 and the PLL 1430. The embodiments described above with reference to fig. 1 to 10 may be entirely applied to the PLL 1430.

Front-end module 1500 may include amplifiers, duplexers, and the like. The front end module 1500 may amplify RF transmission signals provided from the RFIC 1400 and may transmit the amplified signals through the antenna 1600. In some embodiments, wireless communication device 1000 may include multiple antennas 1600, and front-end module 1500 may separate the RF transmit signals for each frequency band and provide the separated RF transmit signals to its corresponding antenna 1600.

Fig. 12 is a schematic diagram illustrating a communication device including a clock generator for performing a phase-locked operation on a clock according to an embodiment.

Referring to fig. 12, according to an embodiment, a home appliance 2100, a home appliance 2120, an entertainment apparatus 2140, and an Access Point (AP)2200 may each include a clock generator for performing a phase-locked operation on a clock. In some embodiments, the home appliance 2100, home appliance 2120, entertainment device 2140, and AP 2200 may configure an internet of things (IoT) network system. The communication device shown in fig. 12 is merely an example, and it will be understood that other communication devices not shown in fig. 12 may also include a wireless communication device according to embodiments.

Fig. 13 is a block diagram of an IoT device 3000 according to an embodiment.

IoT device 3000 may include application processor 3100, transceiver 3200, memory

3300. A display 3400, a sensor 3500, and an input/output (I/O) device 3600.

IoT device 3000 may communicate with external entities through transceiver 3200. The transceiver 3200 may be a modem communication interface accessible to, for example, a wired Local Area Network (LAN), a wireless short-range communication interface (e.g., bluetooth, wireless fidelity (Wi-Fi), and Zigbee), Power Line Communication (PLC), or a mobile cellular network (e.g., third generation (3G), Long Term Evolution (LTE), etc.). The transceiver 3200 may comprise a clock generator according to the above embodiments.

Application processor 3100 may control the overall operation of IoT device 3000 and the operation of the configuration of IoT device 3000. The application processor 3100 may perform various operations. In some embodiments, the application processor 3100 may include a single core or may include multiple cores.

The sensor 3500 may be, for example, an image sensor for sensing an image. The sensor 3500 may be connected to the application processor 3100 and may transmit the generated image information to the application processor 3100. Sensor 3500 may be a biosensor for sensing biometric information. Sensor 3500 may be any sensor, for example, an illuminance sensor, an acoustic sensor, or an acceleration sensor.

The display 3400 may display internal state information of the IoT device 3000. The display 3400 may include a touch sensor (not shown). In addition, the display 3400 may include input or output functions as well as the appearance of a user interface. The user may control the IoT device 3000 through a touch sensor and a user interface.

The input/output device 3600 may include an input unit such as a touch panel, a keyboard, input buttons, and the like, and an output unit such as a display, a speaker, and the like. Memory 3300 may store control instruction code, control data, or user data for controlling IoT device 3000. The memory 3300 can include at least one of volatile memory or nonvolatile memory.

The IoT device 3000 may further include a power supply unit including a battery for internal power supply or receiving power supply from the outside. Additionally, IoT device 3000 may also include a storage device. The storage device may be a non-volatile medium such as a Hard Disk Drive (HDD), a Solid State Disk (SSD), an embedded multimedia card (eMMC), or a universal flash storage device (UFS). The storage device may store user information provided through the input/output device 3600 and various pieces of sensing information collected through the sensor 3500.

The output clock signals may be used for at least some of the above-described components of IoT device 3000, e.g., application processor 3100, transceiver 3200, memory 3300, display 3400, sensor 3500, and input/output device 3600, and may be generated by a clock generator according to embodiments of the inventive concept (e.g., those embodiments described above in connection with fig. 1-10).

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.