阅读说明：本技术 一种肖特基二极管的制备方法 (Preparation method of Schottky diode ) 是由 左瑜 于 2020-12-14 设计创作，主要内容包括：本发明公开了一种肖特基二极管的制备方法,包括选取Si衬底；在Si衬底的上表面形成Ge缓冲层；在Ge缓冲层的上表面形成n～+DR-GeSn层；在n～+DR-GeSn层的上表面形成n～-DR-GeSn层；在n～-DR-GeSn层的上表面形成<100>晶向的Ge帽层；刻蚀至n～+DR-GeSn层的上表面形成台阶结构；在台阶结构中的Ge帽层的上表面形成第一电极；在台阶结构中的n～+DR-GeSn层的上表面形成第二电极。本方法通过Sn合金化致晶向消除技术提高电子迁移率,选用<100>晶向Ge帽层增大金半接触区域半导体电子亲和能,能够提高弱能量密度下SBD的整流效率。(The invention discloses a preparation method of a Schottky diode, which comprises the steps of selecting a Si substrate; forming a Ge buffer layer on the upper surface of the Si substrate; forming n on the upper surface of the Ge buffer layer + A DR-GeSn layer; at n + N is formed on the upper surface of the DR-GeSn layer ‑ A DR-GeSn layer; at n ‑ Formation of the upper surface of the DR-GeSn layer<100>A crystalline oriented Ge cap layer; etching to n + A step structure is formed on the upper surface of the DR-GeSn layer; forming a first electrode on the upper surface of the Ge cap layer in the step structure; n in a stepped structure + The upper surface of the DR-GeSn layer forms a second electrode. The method improves electron mobility by Sn alloying induced crystal orientation elimination technology, and selects<100>The crystal orientation Ge cap layer increases the electron affinity of the semiconductor in the gold-semiconductor contact area, and can improve the rectification efficiency of the SBD under weak energy density.)

1. A preparation method of a Schottky diode is applied to 2.45GHz weak energy density collection and is characterized by comprising the following steps:

selecting a Si substrate;

forming a Ge buffer layer on the upper surface of the Si substrate;

forming n on the upper surface of the Ge buffer layer⁺A DR-GeSn layer;

at said n⁺N is formed on the upper surface of the DR-GeSn layer^-A DR-GeSn layer;

at said n^-Formation of the upper surface of the DR-GeSn layer<100>A crystalline oriented Ge cap layer;

etching to the n⁺A step structure is formed on the upper surface of the DR-GeSn layer;

forming a first electrode on the upper surface of the Ge cap layer in the step structure;

n in the step structure⁺The upper surface of the DR-GeSn layer forms a second electrode.

2. The method of claim 1, wherein forming a Ge buffer layer on the upper surface of the Si substrate comprises:

growing a first Ge layer with the thickness of 100-200nm on the upper surface of the Si substrate at the temperature of 275-325 ℃ by using an RPCVD process;

generating a second Ge layer with the thickness of 300-400nm on the upper surface of the first Ge layer at the temperature of 500-600 ℃ by using an RPCVD process; wherein the Ge buffer layer comprises the first Ge layer and the second Ge layer;

correspondingly, n is formed on the upper surface of the Ge buffer layer⁺A DR-GeSn layer comprising:

forming n on the upper surface of the second Ge layer⁺And a DR-GeSn layer.

3. The method of claim 2, wherein said forming n on an upper surface of said second Ge layer⁺A DR-GeSn layer comprising:

using RPCVD process at 300 deg.C with SnD₄And Ge₂H₆As a gas source, in H₂Growing a 500-GeSn layer on the upper surface of the second Ge layer as a first DR-GeSn layer under the atmosphere;

injecting P ions into the first DR-GeSn layer at 400-500 ℃ to form a doping concentration of 1 multiplied by 10²⁰cm^-3N of (A) to (B)⁺And a DR-GeSn layer.

4. The method of claim 3, wherein the Sn is present in the first DR-GeSn layer in a proportion of 10%.

5. The method of claim 1, wherein said n is a positive integer⁺N is formed on the upper surface of the DR-GeSn layer^-A DR-GeSn layer comprising:

using RPCVD process at 300 deg.C with SnD₄And Ge₂H₆As a gas source, in H₂Under the atmosphere, at the n⁺A DR-GeSn layer with the thickness of 700-800nm is grown on the upper surface of the DR-GeSn layer and is used as a second DR-GeSn layer;

injecting P ions into the second DR-GeSn layer at 400-500 ℃ to form a doping concentration of 3 multiplied by 10¹⁷cm^-3N of (A) to (B)^-And a DR-GeSn layer.

6. The method of claim 5, wherein the Sn is present in the second DR-GeSn layer in a proportion of 10%.

7. The method of claim 1, wherein said n is a positive integer^-Formation of the upper surface of the DR-GeSn layer<100>A crystalline Ge cap layer comprising:

using an RPCVD process at a temperature of 300 ℃ at said n^-The upper surface of the DR-GeSn layer is grown to a thickness of 10nm<100>A crystalline Ge cap layer.

8. The method of claim 1, wherein the etching is to the n⁺The upper surface of DR-GeSn layer forms a step structure, including:

coating a photoresist layer on the upper surface of the Ge cap layer;

reserving the photoresist layer of the first area on the upper surface of the Ge cap layer;

etching the area of the upper surface of the Ge cap layer except the first area by using a plasma etching process under the gas environment of CF4 and SF6 until the upper surface of the n + DR-GeSn layer is etched to form a step structure;

and removing the photoresist layer on the surface of the first region.

9. The method of claim 1, wherein forming a first electrode on an upper surface of the Ge cap layer in the stepped structure comprises:

and depositing metal W with the thickness of 20nm on the upper surface of the Ge cap layer in the step structure by using a molecular beam evaporation process, and etching the metal W in the first designated area by using an etching process to form the first electrode.

10. The method of claim 1, wherein n in the stepped structure⁺The upper surface of the DR-GeSn layer forms a second electrode, which comprises:

n in the step structure by molecular beam evaporation⁺And depositing metal Al with the thickness of 20nm on the upper surface of the DR-GeSn layer, and etching the metal Al in the second designated area by using an etching process to form a second electrode.

Technical Field

The invention belongs to the field of semiconductors, and particularly relates to a preparation method of a Schottky diode.

Background

The emergence of wireless devices such as smart phones, Wi-Fi devices, communication base stations, radio towers, etc., brings great convenience to human life, and these wireless devices transmit information to each other by emitting radio waves, and most of energy is wasted due to attenuation in the environment except for transmitted radio signals. According to the environmental radio frequency energy distribution evaluation of China, 2.45GHz (frequency range of 2.38 GHz-2.45 GHz) radio frequency signals are the main radio frequency signal sources in the environment, but the measured environmental radio frequency power density is low, and the numerical value is less than-20 dBm. If the energy can be utilized and non-contact wireless power supply is realized, the limitation of a transmission line is broken through, a good solution is provided for a large number of low-power-consumption devices to operate without power supply of a battery, and the wireless power supply device has great application potential.

The microwave wireless energy collection system can capture radio frequency signals in the environment through a microwave receiving antenna, a rectification circuit in the system utilizes a core element Schottky diode (SBD) to rectify the energy of the radio frequency signals and supply direct current energy to a receiving load, and the system is an ideal system for realizing the application. Research shows that how to improve the rectification efficiency is a key technology for realizing energy collection aiming at the weak energy density of 2.45 GHz. As is known in the art, a schottky diode is used as a core device in a rectifying circuit, and the performance of the schottky diode directly determines the upper limit of the rectifying efficiency of the microwave wireless energy collecting system.

At present, aiming at the weak energy density of 2.45GHz, the rectification efficiency of the HSMS-2850Ge semiconductor Schottky diode based on Agilent is the highest, but under the condition of the power density of-20 dBm, the rectification efficiency is still less than 10%. At such low rectification efficiency, commercial applications of 2.45GHz weak energy density collection cannot be achieved at all.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a schottky diode. The technical problem to be solved by the invention is realized by the following technical scheme:

a preparation method of a Schottky diode is applied to 2.45GHz weak energy density collection and comprises the following steps:

selecting a Si substrate;

forming a Ge buffer layer on the upper surface of the Si substrate;

forming n on the upper surface of the Ge buffer layer⁺A DR-GeSn layer;

at said n⁺N is formed on the upper surface of the DR-GeSn layer^-A DR-GeSn layer;

at the placeN is^-Formation of the upper surface of the DR-GeSn layer<100>A crystalline oriented Ge cap layer;

etching to the n⁺A step structure is formed on the upper surface of the DR-GeSn layer;

forming a first electrode on the upper surface of the Ge cap layer in the step structure;

n in the step structure⁺The upper surface of the DR-GeSn layer forms a second electrode.

In an embodiment of the present invention, the forming a Ge buffer layer on the upper surface of the Si substrate includes:

growing a first Ge layer with the thickness of 100-200nm on the upper surface of the Si substrate at the temperature of 275-325 ℃ by using an RPCVD process;

generating a second Ge layer with the thickness of 300-400nm on the upper surface of the first Ge layer at the temperature of 500-600 ℃ by using an RPCVD process; wherein the Ge buffer layer comprises the first Ge layer and the second Ge layer;

correspondingly, n is formed on the upper surface of the Ge buffer layer⁺A DR-GeSn layer comprising:

forming n on the upper surface of the second Ge layer⁺And a DR-GeSn layer.

In one embodiment of the present invention, said forming n on the upper surface of said second Ge layer⁺A DR-GeSn layer comprising:

using RPCVD process at 300 deg.C with SnD₄And Ge₂H₆As a gas source, in H₂Growing a 500-GeSn layer on the upper surface of the second Ge layer as a first DR-GeSn layer under the atmosphere;

injecting P ions into the first DR-GeSn layer at 400-500 ℃ to form a doping concentration of 1 multiplied by 10²⁰cm^-3N of (A) to (B)⁺And a DR-GeSn layer.

In one embodiment of the present invention, in the first DR-GeSn layer, the Sn ratio is 10%.

In one embodiment of the present invention, said n is⁺N is formed on the upper surface of the DR-GeSn layer^-A DR-GeSn layer comprising:

using RPCVD process at 300 deg.C with SnD₄And Ge₂H₆As a gas source, in H₂Under the atmosphere, at the n⁺A DR-GeSn layer with the thickness of 700-800nm is grown on the upper surface of the DR-GeSn layer and is used as a second DR-GeSn layer;

injecting P ions into the second DR-GeSn layer at 400-500 ℃ to form a doping concentration of 3 multiplied by 10¹⁷cm^-3N of (A) to (B)^-And a DR-GeSn layer.

In one embodiment of the present invention, the ratio of Sn in the second DR-GeSn layer is 10%.

In one embodiment of the present invention, said n is^-Formation of the upper surface of the DR-GeSn layer<100>A crystalline Ge cap layer comprising:

using an RPCVD process at a temperature of 300 ℃ at said n^-The upper surface of the DR-GeSn layer is grown to a thickness of 10nm<100>A crystalline Ge cap layer.

In one embodiment of the invention, the etching is to the n⁺The upper surface of DR-GeSn layer forms a step structure, including:

coating a photoresist layer on the upper surface of the Ge cap layer;

reserving the photoresist layer of the first area on the upper surface of the Ge cap layer;

etching the area of the upper surface of the Ge cap layer except the first area by using a plasma etching process under the gas environment of CF4 and SF6 until the upper surface of the n + DR-GeSn layer is etched to form a step structure;

and removing the photoresist layer on the surface of the first region.

In one embodiment of the present invention, the forming a first electrode on the upper surface of the Ge cap layer in the step structure includes:

and depositing metal W with the thickness of 20nm on the upper surface of the Ge cap layer in the step structure by using a molecular beam evaporation process, and etching the metal W in the first designated area by using an etching process to form the first electrode.

In one embodiment of the present invention, the step structure is formed of a plurality of stepsN of (A) to (B)⁺The upper surface of the DR-GeSn layer forms a second electrode, which comprises:

n in the step structure by molecular beam evaporation⁺And depositing metal Al with the thickness of 20nm on the upper surface of the DR-GeSn layer, and etching the metal Al in the second designated area by using an etching process to form a second electrode.

Compared with the prior art, in the embodiment of the invention, the Sn alloying crystal orientation eliminating technology is adopted in the body region of the SBD semiconductor except the gold half-contact region, and compared with a pure Ge semiconductor, the electron mobility of the obtained GeSn alloy semiconductor is greatly improved, so that the series resistance can be reduced, and the rectification efficiency is improved; meanwhile, a <100> crystal orientation Ge semiconductor is introduced to serve as a Ge cap layer to form a gold half contact with the metal, so that the electron affinity of the semiconductor in the gold half contact area is increased, and the rectification efficiency of the SBD under weak energy density can be improved. Therefore, when the Schottky diode provided by the embodiment of the invention is applied to a rectifying circuit of a 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collecting application in the weak energy density environment is realized.

In addition, the cathode is arranged at n⁺DR-GeSn layer capable of avoiding n⁺The performance degradation of the device is caused by the interface difference between the DR-GeSn and the Si substrate. The preparation method of the Schottky diode is prepared on the Si substrate, and has the advantage of low device process cost.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a flow chart of a method for manufacturing a schottky diode according to an embodiment of the present invention;

fig. 2a to fig. 2n are schematic diagrams illustrating a method for manufacturing a schottky diode according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a schottky diode according to an embodiment of the present invention, which is applied to 2.45GHz weak energy density collection, and as shown in fig. 1, the method for manufacturing a schottky diode according to an embodiment of the present invention includes the following steps:

s101, selecting a Si substrate;

s102, forming a Ge buffer layer on the upper surface of the Si substrate;

s103, forming n on the upper surface of the Ge buffer layer⁺A DR-GeSn layer;

s104, in the n⁺N is formed on the upper surface of the DR-GeSn layer^-A DR-GeSn layer;

s105, in the n^-Formation of the upper surface of the DR-GeSn layer<100>A crystalline oriented Ge cap layer;

s106, etching to the n⁺A step structure is formed on the upper surface of the DR-GeSn layer;

s107, forming a first electrode on the upper surface of the Ge cap layer in the step structure;

s108, n in the step structure⁺The upper surface of the DR-GeSn layer forms a second electrode.

The following is specifically set forth:

the embodiment of the invention adopts Sn alloying induced crystal orientation elimination technology, and specifically, n is⁺DR-GeSn layers 004 and n^-The DR-GeSn layer 005 is a GeSn alloy layer, where DR represents Direct band gap relaxation (Direct band gap relaxation). The inventor researches and discovers that the Ge semiconductor material can be modified by adding Sn into Ge for alloying, so that the Ge can be converted from an indirect bandgap semiconductor into a direct bandgap semiconductor, and an energy surface such as Ge electronic population can be converted from an anisotropic L energy valley into an isotropic gamma energy valley. The electron mobility of the alloyed GeSn semiconductor can be improved to more than twice of that of the Ge semiconductor. Specifically, after Sn is alloyed, the electron mobility in any crystal orientation direction can be improved<110>2 to 3 times of the electron mobility of Ge in the crystal orientation (<110>The electron mobility of the crystal orientation Ge is larger than that of the crystal orientation Ge<100>Crystal orientation Ge and<111>electron mobility of Ge in crystal orientation). The improvement of the electron mobility can reduce the series resistance of the SBD, thereby improving the rectification efficiency, therefore, the inventionCompared with a pure Ge semiconductor, the rectification efficiency of the SBD can be improved by the Sn alloying crystal orientation eliminating technology.

In the embodiment of the present invention, the Ge cap layer 006 has a <100> crystal orientation and an electron affinity of the <100> crystal orientation Ge of 4.272eV, which is significantly greater than the electron affinity 4.163eV of the <110> crystal orientation Ge commonly used in the industry. The inventor finds that the increase of the electron affinity of the semiconductor can improve the zero-bias current responsivity, thereby improving the rectification efficiency of the SBD under weak energy density. Therefore, in the embodiment of the present invention, the Ge cap layer 006 is disposed in gold-half contact with the metal, and the Ge cap layer 006 is selected to have a <100> crystal orientation, so that the rectification efficiency of the SBD under the weak energy density of 2.45GHz can be improved. The specific principles related to this section are described later in connection with the inventive concept.

In the embodiment of the invention, the higher part of the step structure comprises the n from bottom to top⁺DR-GeSn layer, said n^-A DR-GeSn layer and the Ge cap layer, the lower part of the step structure including the n⁺A DR-GeSn layer; the first electrode is an anode and is positioned on the upper surface of the Ge cap layer at the higher part, the second electrode is a cathode, and the n at the lower part⁺And the upper surface of the DR-GeSn layer. The cathode is arranged at n⁺DR-GeSn layer capable of avoiding n⁺The performance degradation of the device is caused by the interface difference between the DR-GeSn and the Si substrate.

The embodiment of the invention provides a preparation method of a Schottky diode. By adopting Sn alloying crystal orientation elimination technology in the body region of the SBD semiconductor except the gold half-contact region, compared with a pure Ge semiconductor, the electron mobility of the obtained GeSn alloy semiconductor is greatly improved, so that the series resistance can be reduced, and the rectification efficiency is improved; meanwhile, a <100> crystal orientation Ge semiconductor is introduced to serve as a Ge cap layer to form a gold half contact with the metal, so that the electron affinity of the semiconductor in the gold half contact area is increased, and the rectification efficiency of the SBD under weak energy density can be improved. Therefore, when the Schottky diode provided by the embodiment of the invention is applied to a rectifying circuit of a 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collecting application in the weak energy density environment is realized.

In addition, the cathode is arranged at n⁺DR-GeSn layer capable of avoiding n⁺The performance degradation of the device is caused by the interface difference between the DR-GeSn and the Si substrate. The preparation method of the Schottky diode is prepared on the Si substrate, and has the advantage of low device process cost.

The following provides a detailed description of the preparation process of the examples of the present invention.

Referring to fig. 2a to 2n, fig. 2a to 2n are schematic diagrams illustrating a method for manufacturing a schottky diode according to an embodiment of the present invention. The steps and detailed parameters of the preparation method described above are specifically described in this section. The method specifically comprises the following steps:

s201, selecting a Si substrate 001; as shown in fig. 2 a;

in the embodiment of the invention, the Si substrate is selected because of its low cost and easy peeling property, which can ensure the efficiency and yield of the schottky diode produced subsequently. Specifically, Si with a <100> crystal orientation is selected as the Si substrate 001, so that a Ge material with a <100> crystal orientation can be grown subsequently.

S202, cleaning; using dilute hydrofluoric acid and deionized water to circularly clean the surface of the Si substrate 001 so as to remove impurities;

s203, growing a first Ge layer 002 on the upper surface of the Si substrate 001; as shown in fig. 2b, a first Ge layer 002 with a thickness of 100-200nm is grown on the upper surface of the Si substrate 001 by using an RPCVD process at a temperature of 275-325 ℃; as will be appreciated by those skilled in the art, the first Ge layer 002 is prepared using a low temperature process;

s204, growing a second Ge layer 003 on the upper surface of the first Ge layer 002; as shown in fig. 2c, a second Ge layer 003 with a thickness of 300-; it will be understood by those skilled in the art that the second Ge layer 003 is fabricated using a high temperature process.

The first Ge layer and the second Ge layer form a Ge buffer layer, and the Ge buffer layer is prepared on the Si substrate by adopting a high-low temperature two-step method, so that the problem of lattice mismatch among silicon and germanium can be solved, mismatch dislocation is reduced, a flat surface is obtained, the processing technology difficulty of a device is reduced, the technology cost of the device is reduced, and the subsequent growth of a high-quality germanium tin layer is facilitated. Meanwhile, tensile stress can be generated in the Ge layer in the process, so that the direct band gap of Ge is reduced, the absorption coefficient is enhanced, and the preparation of the high-performance Schottky diode is facilitated.

S205, annealing; adopting a cyclic annealing process to carry out 4 times of cyclic annealing at the temperature of 700-900 ℃;

s206, growing a first DR-GeSn layer 0041; as shown in FIG. 2d, the RPCVD process is used to control the temperature of the wafer at 300 deg.C with SnD₄(stanndeuteroalkane) and Ge₂H₆(digermane) as a gas source in H₂Growing a 500-700nm DR-GeSn layer on the second Ge layer 003 as a first DR-GeSn layer 0041 under the atmosphere;

as described above, by the Sn alloying crystallographic direction elimination technique in Ge, the energy plane anisotropy L energy valley such as Ge electron population can be converted into the isotropic Γ energy valley, and the electron mobility of the alloyed Ge semiconductor can be greatly improved compared with the electron mobility of a pure Ge semiconductor. And the improvement of electron mobility can reduce the series resistance of the SBD, and the reduction of the series resistance of the SBD can improve the rectification efficiency. Therefore, compared with a pure Ge semiconductor, the rectification efficiency of the SBD can be improved by the Sn alloying induced crystal orientation elimination technology.

S207, preparation n⁺DR-GeSn layer 004; as shown in FIG. 2e, P ions are implanted into the first DR-GeSn layer 0041 at 400 to 500 ℃ to form a dopant concentration of 1 × 10²⁰cm^-3N of (A) to (B)⁺A DR-GeSn layer 004, wherein the implantation time of the P ions is 200s, and the implantation energy is 30 keV; n is⁺The DR-GeSn layer 004 adopts high doping concentration so as to facilitate the subsequent preparation of ohmic contact on the DR-GeSn layer;

s208, annealing; annealing the whole material at 600 ℃ for 30 minutes in a nitrogen atmosphere;

s209, growing a second DR-GeSn layer 0051; as shown in fig. 2f, using RPCVD process at 300 deg.cAt a temperature of SnD₄And Ge₂H₆As a gas source, in H₂Under the atmosphere, at the n⁺A700-800 nm DR-GeSn layer is grown on the DR-GeSn layer 004 to serve as a second DR-GeSn layer 0051, in the step, the electron mobility is improved by utilizing a Sn alloying induced crystal orientation elimination technology to reduce the series resistance of the SBD, and therefore the purpose of improving the rectification efficiency is achieved.

In a preferred embodiment, the ratio of Sn in the first DR-GeSn layer 0041 and the second DR-GeSn layer 0051 is 10%. This ratio is highly process implementable and is sufficient to change the alloy after doping with Sn from an indirect bandgap to a direct bandgap.

S210, preparation n^-A DR-GeSn layer 005, as shown in FIG. 2g, implanting P ions into the second DR-GeSn layer 0051 at 400-500 deg.C to form a dopant concentration of 3 × 10¹⁷cm^-3N of (A) to (B)^-A DR-GeSn layer 005 in which the P ions are implanted for 200s and the implantation energy is 30 keV; n is^-The DR-GeSn layer 005 employs a low doping concentration to facilitate subsequent fabrication of schottky contacts thereon.

S211, annealing; annealing the whole material at 600 ℃ for 30 minutes in a nitrogen atmosphere;

s212, growing<100>A crystalline Ge cap layer 006; as shown in fig. 2h, using RPCVD process at 300 deg.c temperature at said n^-Growth of upper surface of DR-GeSn layer 005<100>A crystalline Ge cap layer 006;

in a preferred embodiment, the thickness of the Ge cap layer 006 is 10 nm. The thickness is selected by comprehensively considering two factors of process realization and device performance requirements. This is because the inventors have discovered that a 10nm Ge cap layer has been found to improve the rectifying efficiency of SBD at weak energy densities and in turn facilitate cost control.

S213, cleaning; the Ge cap layer 006 is cyclically cleaned by using dilute hydrofluoric acid and deionized water to remove impurities;

s214, coating a photoresist layer 009; as shown in fig. 2i, a photoresist layer 009 is coated on the surface of the Ge cap layer 006;

s215, determining a first area on the surface of the photoresist layer 009, and exposing the photoresist layer 009 except the first area by using a photoetching process; the first region may be a region near one end of the photoresist layer 009; for example, the first region may be a left half region of the photoresist layer 009;

s216, cleaning by using the photoresist sol, and removing the photoresist layer 009 outside the first region, as shown in FIG. 2 j;

s217, etching the step structure; as shown in FIG. 2k, at CF₄And SF₆Etching the region of the upper surface of the Ge cap layer 006 except the first region by using a plasma etching process in a gas environment until the etching reaches the n⁺A step structure is formed on the upper surface of the DR-GeSn layer 004;

s218, removing the photoresist layer 009 on the surface of the first region, and removing the remaining photoresist layer 009 as shown in FIG. 2 l; it is understood that, after this step, the upper surface of the step structure is the Ge cap layer 006, and the lower surface thereof is the n⁺DR-GeSn layer 004.

S219, preparing a first electrode 007; as shown in fig. 2m, a metal W with a thickness of 20nm is deposited on the surface of the Ge cap layer 006 in the step structure by using a molecular beam evaporation process, and the metal W in the first designated area is etched by using an etching process to form a first electrode 007; wherein the first electrode 007 is an anode; the first designated region may be a certain region at both ends of the metal W;

s220, preparing a second electrode 008; as shown in fig. 2n, using a molecular beam evaporation process, at said n of said step structure⁺Depositing metal Al with the thickness of 20nm on the upper surface of the DR-GeSn layer 004, and etching away the metal Al in a second designated area by utilizing an etching process to form a second electrode 008, wherein the second electrode 008 is a cathode; the second designated area may be the metal Al close to the n^-A certain region at one end of the DR-GeSn layer 005.

Through the above process steps, the structure of the prepared schottky diode based on the crystal orientation optimization technology and Sn alloying is shown in fig. 2 n. The method specifically comprises the following steps:

a Si substrate 001; first, theA Ge layer 002; a second Ge layer 003; n is⁺DR-GeSn layer 004; n is^-A DR-GeSn layer 005;<100>a crystalline Ge cap layer 006; a first electrode 007; and a second electrode 008.

In the embodiment of the invention, the Sn alloying induced crystal orientation elimination technology is adopted in the body region of the SBD semiconductor except the gold half-contact region, compared with a pure Ge semiconductor, the electron mobility of the obtained GeSn alloy semiconductor is greatly improved, so that the series resistance can be reduced, and the rectification efficiency is improved; meanwhile, a <100> crystal orientation Ge semiconductor is introduced to serve as a Ge cap layer to form a gold half contact with the metal, so that the electron affinity of the semiconductor in the gold half contact area is increased, and the rectification efficiency of the SBD under weak energy density can be improved. Therefore, when the Schottky diode provided by the embodiment of the invention is applied to a rectifying circuit of a 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collecting application in the weak energy density environment is realized.

In addition, the cathode is arranged at n⁺DR-GeSn layer capable of avoiding n⁺The performance degradation of the device is caused by the interface difference between the DR-GeSn and the Si substrate. The Schottky diode preparation process based on the crystal orientation optimization technology and Sn alloying is realized on the Si substrate, and has the advantage of low device process cost.

To facilitate an understanding of the structure and benefits of the schottky diode based on the crystal orientation optimization technique and Sn alloying, which are generated by the processes of the embodiments of the present invention, the inventive concepts of the inventors are briefly introduced herein and the foregoing principles are explained.

The inventor researches the rectification efficiency, and the formula of the rectification efficiency is as follows:

in the formula (1), P_DCCorresponding power, P, of the direct current output after rectification_RFFor the power of the radio-frequency signal in the environment of the input before rectification, eta_MTo match efficiency, η_pIs the efficiency, η, related to parasitic parameters₀Is thatConversion efficiency, η, in non-linear devices_{DC_transfer}Is the efficiency with which direct current is transferred from the circuit to the load.

In the formula (1), the first and second groups,

q is a quality factor, Q_CTo match the quality factors of network elements, to make the matching efficiency eta_MMaximum, usually Q<<Q_C。

In the formula (1), the first and second groups,

R_jis junction resistance, R_sIs a series resistance, C_jIs the junction capacitance and f is the frequency.

In the formula (1), the first and second groups,

P_inis the power that is going into the rectifier,is zero-bias current responsivity, R_LIs a load resistance.

In the formula (1), the first and second groups,

therefore, the expression of the rectification efficiency η obtained by integrating the expressions (1), (2), (3), (4) and (5) is:

where ω is 2 · pi · f.

As can be seen from equation (6), the junction capacitance C is reduced at high frequencies_jSeries resistance R_sJunction resistance R_jThe rectification efficiency can be improved. Meanwhile, the zero bias current responsivity of the device is increasedRectification efficiency can also be improved.

Thus, in one aspect, the inventors contemplate reducing the junction capacitance C_jSeries resistance R_sJunction resistance R_jThe angle of (2) improves the rectification efficiency of the SBD at weak energy density. On the other hand, the inventors expect the zero-bias current responsivity of the device to be increasedAnd the rectification efficiency of the SBD under the weak energy density is improved.

Thus, the inventors further demonstrated zero-bias current responsivity to SBDThe formula of zero-bias current responsivity is shown in the following formula (7):

wherein i⁽¹⁾(V) and i⁽²⁾(V) are the first and second derivative functions of current versus voltage, respectively. The current formula is shown below (8) (considering the effects of mirror force and tunneling):

the first derivative function and the second derivative function of the current versus the voltage obtained from equation (8) are expressed by the following equations (9) and (10), respectively:

substituting (9) and (10) into equation (7), the SBD zero-bias current responsivityComprises the following steps:

in the formula (11), the reaction mixture is,other symbolic physical meanings are described in the literature "semiconductor device physics". Since the correction term in equation (11), i.e., the third term, is either positive or zero-biasedSmall, so SBD zero-bias current responsivity can be simplified to equation (12):

as can be seen from equation (12), the SBD zero-bias current responsivity is mainly determined by the SBD ideality factor n. The smaller the value of n, the zero-bias current responsivityThe larger the rectification efficiency of the SBD.

Where the ideality factor n is the first partial derivative of the voltage V with respect to the current J, and is expressed as:

since the slope of the lnI-V curve can be characterized asThus, the formula (13) shows that the steeper the slope of the lnI-V curve, i.e., the slopeThe larger, theThe smaller the n value is, the larger the zero-bias current responsivity of the SBD is, and the larger the rectification efficiency of the SBD is. That is, increaseThe zero-bias current responsivity can be improved, and the circuit rectification efficiency under weak energy density can be improved. It is to be emphasized here that the value of n in equation (13) is not an ideal factor extracted from the normal operating state of the SBD I-V curve, but an ideal factor extracted from the weak energy rectification region.

The inventor researches and discovers that the slope of an lnI-V curve of an SBD weak energy rectification areaAnd effective physical constantsBarrier height phi of metal side_nsClosely related, see the following formula (14), wherein ∈ indicates a proportional relationship.

As can be seen from the formula (14) Phi_nsThe exponential term in equation (14) is understood to decrease φ_nsCan be remarkably increasedThus, the inventors aimed at_nsFurther studies found that:

φ_ns＝W_m-χ (15)

wherein, W_mChi is the metal work function and the semiconductor electron affinity. From the formula (15), W is reduced_mOr increasing χ may decrease φ_nsThereby realizing the zero bias current responsivity under the condition of increasing the weak energy densityThe purpose of improving the SBD rectification efficiency under weak energy density.

Specifically, in the Schottky diode based on the crystal orientation optimization technology and Sn alloying, on one hand, a <100> crystal orientation Ge semiconductor is introduced as a Ge cap layer to form gold-half contact with metal, and compared with a <110> crystal orientation Ge semiconductor commonly used in the industry, the <100> crystal orientation Ge semiconductor can increase the electron affinity of the semiconductor in the gold-half contact area so as to improve the zero bias current responsivity of the SBD and improve the rectification efficiency of the SBD under the condition of weak energy density; on the other hand, in the body region of the SBD semiconductor except the gold half-contact region, an energy surface such as Ge electronic population is converted into an isotropic gamma energy valley from an anisotropic L energy valley through a Sn alloying (preferably 10% Sn) crystal orientation elimination technology, compared with a pure Ge semiconductor, the electron mobility of the obtained GeSn alloy semiconductor is greatly improved compared with that of a pure Ge semiconductor material, the SBD series resistance can be effectively reduced, and the rectification efficiency of the device is improved. Therefore, under the combined action of the two aspects, when the schottky diode provided by the embodiment of the invention is applied to a rectifying circuit of a 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collecting application under the weak energy density environment is realized.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.