Method of manufacturing semiconductor device and semiconductor device
阅读说明：本技术 制造半导体器件的方法和半导体器件 (Method of manufacturing semiconductor device and semiconductor device ) 是由 张筱君 沈冠杰 于 2020-04-14 设计创作，主要内容包括：在制造包括Fin FET的半导体器件的方法中,形成鳍结构,鳍结构具有由SiGe制成的上部鳍结构和由与上部鳍结构不同的材料制成的底部鳍结构,在鳍结构上方形成覆盖层,对由覆盖层覆盖的鳍结构执行热操作,以及在上部鳍结构的源极/漏极区域中形成源极/漏极外延层。热操作改变上部鳍结构中的锗分布。本发明的实施例还涉及半导体器件。(In a method of fabricating a semiconductor device including a Fin FET, a Fin structure is formed having an upper Fin structure made of SiGe and a bottom Fin structure made of a different material from the upper Fin structure, a capping layer is formed over the Fin structure, a thermal operation is performed on the Fin structure covered by the capping layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper Fin structure. The thermal operation changes the germanium profile in the upper fin structure. Embodiments of the invention also relate to semiconductor devices.)
1. A method of fabricating a semiconductor device comprising a Fin field effect transistor (Fin FET), the method comprising:
forming a fin structure having an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure;
forming a capping layer over the fin structure;
performing a thermal operation on the fin structure covered by the capping layer; and
forming a source/drain epitaxial layer in a source/drain region of the upper fin structure,
wherein the thermal operation alters a germanium profile in the upper fin structure.
2. The method of claim 1, wherein the thermal operation is performed prior to forming the source/drain epitaxial layer.
3. The method of claim 1, wherein the thermal operation is fusion laser annealing.
4. The method of claim 3, wherein the melting laser anneal melts the upper fin structure and then recrystallizes the upper fin structure to have a different germanium profile than before the melting laser anneal is performed.
5. The method of claim 1, wherein the Ge concentration of the upper fin structure prior to the thermal operation is in a range from 15% to 30% in atomic percent.
6. The method of claim 1, wherein after the thermal operation, a concentration of Ge at or near a surface of the upper fin structure is higher than a concentration of Ge at a center of the upper fin structure.
7. The method of claim 6, wherein the Ge concentration has a peak at a depth in a range of 1nm to 5nm from a surface of the upper fin structure.
8. The method of claim 6, wherein a difference between a highest Ge concentration and a lowest Ge concentration in the upper fin structure is in a range of 5 to 35 percentage points.
9. A method of fabricating a semiconductor device comprising a fin field effect transistor, the method comprising:
forming a fin structure having an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure;
forming a liner layer over the fin structure;
forming a layer of insulating material over the pad layer;
recessing the insulating material layer and the liner layer to expose an upper portion of the upper fin structure;
forming a capping layer over the exposed upper portion of the upper fin structure;
performing a thermal operation on the fin structure with the capping layer; and
forming a source/drain epitaxial layer in a source/drain region of the upper fin structure,
wherein the thermal operation alters a germanium profile in the upper fin structure.
10. A semiconductor device, comprising:
a fin structure having a channel region and source/drain regions;
a gate structure comprising a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and
a source/drain epitaxial layer formed in the source/drain region,
wherein the channel region comprises SiGe having a non-uniform Ge concentration such that the Ge concentration at or near a surface of the fin structure is higher than the Ge concentration at a center of the fin structure.
Technical Field
Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device.
Background
As the semiconductor industry moves toward nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from fabrication and design issues have led to the development of three-dimensional designs, such as Fin field effect transistors (Fin FETs), and the use of metal gate structures with high-k (dielectric constant) materials. The metal gate structure is typically fabricated by using a gate replacement technique, and the source and drain are formed by using an epitaxial growth method.
Disclosure of Invention
An embodiment of the present invention provides a method of manufacturing a semiconductor device including a Fin field effect transistor (Fin FET), the method including: forming a fin structure having an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure; forming a capping layer over the fin structure; performing a thermal operation on the fin structure covered by the capping layer; and forming a source/drain epitaxial layer in a source/drain region of the upper fin structure, wherein the thermal operation alters a germanium profile in the upper fin structure.
Another embodiment of the present invention provides a method of manufacturing a semiconductor device including a fin field effect transistor, the method including: forming a fin structure having an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure; forming a liner layer over the fin structure; forming a layer of insulating material over the pad layer; recessing the insulating material layer and the liner layer to expose an upper portion of the upper fin structure; forming a capping layer over the exposed upper portion of the upper fin structure; performing a thermal operation on the fin structure with the capping layer; and forming a source/drain epitaxial layer in a source/drain region of the upper fin structure, wherein the thermal operation alters a germanium profile in the upper fin structure.
Still another embodiment of the present invention provides a semiconductor device including: a fin structure having a channel region and source/drain regions; a gate structure comprising a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and a source/drain epitaxial layer formed in the source/drain region, wherein the channel region comprises SiGe having a non-uniform Ge concentration such that the Ge concentration at or near the surface of the fin structure is higher than the Ge concentration at the center of the fin structure.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Figure 1 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 2 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 3 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 4 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 5 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 6 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation in accordance with an embodiment of the present invention.
Figure 7 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 8 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Fig. 9A and 9B illustrate cross-sectional views of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Fig. 10A and 10B illustrate cross-sectional views of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Fig. 11A and 11B illustrate cross-sectional views of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Fig. 12 shows an element analysis result in the depth direction according to an embodiment of the present invention.
FIG. 13 illustrates simulated elemental analysis in the depth direction according to an embodiment of the invention.
Figure 14 shows an energy band diagram according to an embodiment of the invention.
Figure 15 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 16 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 17 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 18 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 19 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 20 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 21 illustrates a cross-sectional view of one of the various stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 22 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 23 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Figure 24 illustrates a cross-sectional view of one of the stages of a sequential semiconductor device fabrication operation, in accordance with an embodiment of the present invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired properties of the device. Further, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various components may be arbitrarily drawn in different scales for simplicity and clarity. In the drawings, some layers/components may be omitted for simplicity.
Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such. In addition, the term "made of … …" may mean "including" or "consisting of … …". Further, in the following manufacturing processes, there may be one or more additional operations between the operations described, and the order of the operations may be changed. In the present invention, the phrase "one of A, B and C" means "A, B and/or C" (A, B, C, A and B, A and C, B and C or A, B and C), and does not denote one element from a, one element from B, and one element from C unless otherwise specified. Throughout the disclosure, source and drain are used interchangeably, and source/drain refers to one or both of the source and drain. In the following embodiments, materials, configurations, dimensions, processes, and/or operations described with respect to one embodiment (e.g., one or more figures) may be employed in other embodiments and detailed descriptions thereof may be omitted.
The disclosed embodiments relate to a semiconductor device and a method of fabricating the same, and more particularly, to a channel region of a Fin field effect transistor (Fin FET). Embodiments such as those disclosed herein are generally applicable not only to Fin FETs, but also to other FETs.
Silicon germanium (SiGe) is one of the semiconductor materials suitable for the channel region of a p-type FET because its carrier mobility is higher than Si. Although the high Ge concentration in the channel region increases carrier (hole) mobility, the high Ge concentration channel will suffer more severe current leakage, e.g., sub-threshold current leakage, due to less gate control at the center of the fin structure.
In the present invention, the SiGe channel region has a non-uniform Ge concentration. In particular, the SiGe fin channel of the FinFET has a higher Ge concentration near the surface of the fin structure than at the center of the fin structure. With such a SiGe fin structure, on-state current can be enhanced by higher carrier mobility and lower threshold voltage Vt due to higher Ge concentration at the surface region of the fin structure, while current leakage at the sub-threshold region is suppressed due to lower Ge concentration at the central region of the fin structure.
Fig. 1-11B show exemplary cross-sectional views of various stages for fabricating a Fin FET device, according to one embodiment of the invention. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 1-11B, and that some of the operations described below may be replaced or eliminated with respect to other embodiments of the method. The order of operations/processes may be interchanged. Unless otherwise specified, the semiconductor layer and the substrate are crystalline.
As shown in fig. 1, a substrate 10 is provided. The substrate 10 is, for example, a p-type silicon substrate, and has an impurity concentration of about 1 × 1015cm-3To about 1X 1016cm-3Within the range of (1). In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration of about 1 × 1015cm-3To about 1X 1016cm-3Within the range of (1). The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).
As shown in FIG. 2, Si is epitaxially formed on a substrate 101-xGexAnd (c) a layer 15. In some embodiments, a portion or the entire surface of the substrate is etched (patterned), and then Si is epitaxially formed on the etched surface of the substrate 101-xGexAnd (c) a layer 15. In some embodiments, the germanium concentration x is in the range of about 0.1 to about 0.3 in some embodiments, and in the range of about 0.15 to about 0.25 in other embodiments. When the Ge concentration exceeds 0.3, interface defects (Dit defects) and/or swing defects may increase, and when the Ge concentration is lower than 0.1, high mobility germanium (low mobility) cannot be obtained.
The SiGe layer 15 may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), or any other suitable epitaxial growth process. In some embodiments, by using a substance such as SiH4、Si2H6Or SiCl2H2And a Si-containing gas such as GeH4、Ge2H6Or GeCl2H2The SiGe layer 15 is grown at a temperature of about 600 to 800 c and a pressure of about 80 to 150 torr. In some embodiments, in-situ doping is performed. In some embodiments, the thickness of the SiGe layer 15 is in the range of about 20nm to about 100nm, and in other embodiments in the range of about 40nm to 80 nm. In some embodiments, one or more SiGe layers having a lower Ge concentration are epitaxially formed as buffer layers on the substrate 10 prior to forming the SiGe layer 15. In some embodiments, the SiGe layer 15 further comprises Sn. The Ge concentration in the SiGe layer 15 is substantially uniform.
As shown in fig. 3, one or more fin structures 20 are formed. The fin structure 20 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithography and self-aligned processes, allowing creation of patterns with, for example, pitches smaller than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the fin structure. Multiple patterning processes combined with photolithography and self-aligned processes typically result in the formation of a pair of fin structures. In fig. 3, one fin structure 20 is shown. However, the number of fin structures is not limited to one for one FET. In some embodiments, two, three, four, or more fin structures are formed for one FET. In some embodiments, one or more dummy fin structures are formed adjacent to the active fin structures 20.
In some embodiments, a portion of the substrate 10 is also etched to form a fin bottom structure, as shown in fig. 3. In other embodiments, the entire fin structure 20 is made of the SiGe layer 15. In some embodiments, the height H1 of the upper fin structure (SiGe layer 15) is in the range of about 20nm to about 100nm, and in other embodiments, in the range of about 40nm to about 80 nm. In some embodiments, the height H2 of the bottom fin structure (a portion of the substrate 10) is in the range of about 0nm to about 20nm, and in other embodiments, in the range of about 5nm to about 10 nm. In some embodiments, the width W1 of the fin structure 20 at the interface between the SiGe layer 15 and the bottom fin structure is in the range of about 10nm to about 50nm, and in other embodiments, in the range of about 15nm to about 30 nm.
Then, as shown in fig. 4, one or more liner layers 22 are formed to cover the fin structure 20. In some embodiments, fin liner layer 22 includes one or more layers of silicon oxide, silicon nitride, SiON, SiCN, and SiOCN or any other suitable material. In some embodiments, the fin liner layer 22 has a thickness in a range from about 10nm to about 20 nm. The fin liner layer 22 may be formed by using CVD (such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), low pressure CVD (lpcvd), and high density plasma CVD (hdpcvd)), Atomic Layer Deposition (ALD), and any other suitable film forming process. In some embodiments, the liner layer 22 is a single silicon nitride layer, and in other embodiments, the liner layer 22 is a double layer of silicon oxide and silicon nitride.
Subsequently, as shown in fig. 5, a fusion laser anneal operation 80 is performed to redistribute the germanium in the SiGe fin structure 20 to have a non-uniform Ge distribution. When laser light is irradiated to the SiGe fin structure through the fin liner layer 22, the irradiated portion of the SiGe fin structure is heated above its melting point and becomes a molten state, and after the laser light irradiation, the molten portion of the fin structure is recrystallized. During the recrystallization, the germanium tends to move to the surface of the fin structure, resulting in a surface region with a higher germanium concentration than the center of the fin structure.
In some embodiments, the energy of the laser is about 0.5J/cm2To about 5J/cm2And, in other embodiments, about 1.0J/cm2To about 2.0J/cm2Within the range of (1). In some embodiments, the laser irradiation time is in the range of 0.1 nanoseconds to 10 nanoseconds, and in other embodiments, in the range of about 0.5 nanoseconds to about 5 nanoseconds. In some embodiments, the SiGe fin structure 20 is heated above the melting point of SiGe. In some embodiments, the temperature of the heating is in the range from about 1200 ℃ to about 1400 ℃. In other embodiments, the temperature ranges from about 800 ℃ to about 1200 ℃. The setting of the laser annealing conditions depends on the germanium content in the fin structure. In some embodiments, the optimal or desired laser anneal energy is set to bring the SiGe fin close to the molten state so that the germanium can redistribute with regrowth, with the germanium distribution having a higher concentration at the fin surface and a lower concentration at the fin center. If the laser energy is too high outside the above range, the SiGe fin structure will be in a fully molten state, which should be avoided. If the energy is too low, the SiGe fin will not re-grow, which means that the germanium concentration will not change. In some embodiments, the fusion laser annealing operation 80 is performed in an inert gas environment (such as N)2Ar or He ambient).
As shown in fig. 6, after the fusion laser annealing operation 80, the insulating layer 30 is formed. As shown in fig. 6, the insulating layer 30 is formed as a thick layer such that the fin structure 20 is completely embedded in the thick layer.
The insulating material for insulating layer 30 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or low-k dielectric materials. The isolation insulating layer is formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material may be deposited instead of silicon oxide. As the name suggests, flowable dielectric materials can "flow" during deposition to fill gaps or spaces with high aspect ratios. Typically, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, a hydrogen nitrogen bond is added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, Methyl Silsesquioxane (MSQ), Hydrogen Silsesquioxane (HSQ), MSQ/HSQ, perhydrosilazane (TCPS), Perhydropolysilazane (PSZ), Tetraethylorthosilicate (TEOS), or silylamines such as Trisilylamine (TSA). These flowable silicon oxide materials are formed in a number of operations. After depositing the flowable film, the flowable film is cured and then annealed to remove undesirable elements to form silicon oxide. When the undesired elements are removed, the flowable film densifies and shrinks. The flowable film may be doped with boron and/or phosphorous.
In addition, as shown in FIG. 7, an annealing operation 35 is performed. In some embodiments, anneal operation 35 is included, such as at N2Rapid Thermal Annealing (RTA) using infrared light in an inert gas atmosphere of Ar or He. The temperature of the anneal operation 35 is lower than the temperature of the fusion laser anneal operation 80 to prevent further redistribution of germanium and is in the range of about 600 c to about 700 c. In some embodiments, the annealing time is in the range of about 1 second to 60 seconds. Other annealing operations may be utilized, such as plate baking.
As shown in fig. 8, after an anneal operation 35, insulating layer 30 is recessed to expose an upper portion of fin structure 20 to form isolation insulating layer 32. The fin liner layer 22 is also etched down as shown in fig. 8. The isolation insulating layer 32 may also be referred to as a "Shallow Trench Isolation (STI)" layer. In some embodiments, the layer of insulating material 30 is recessed to a level equal to or above the interface between the substrate 10 and the SiGe layer 15. In other embodiments, the layer of insulating material 30 is recessed to a level below the interface between the substrate 10 and the SiGe layer 15.
In some embodiments, the height H3 of the fin structure from the upper surface of the isolation insulating layer 32 is in the range of about 20nm to about 100nm, and in other embodiments in the range of about 40nm to about 80 nm. In some embodiments, the width W2 of the fin structure 20 at the level of the upper surface of the isolation insulating layer 32 is in the range of about 10nm to about 50nm, and in other embodiments in the range of about 15nm to about 30 nm.
As shown in fig. 9A and 9B, after the isolation insulating layer 32 is formed, a sacrificial gate structure 40 is formed over the fin structure 20. Fig. 9A is a sectional view along the gate extending direction (X), and fig. 9B is a sectional view along the source-drain direction (Y).
To fabricate the sacrificial gate structure 40, a dielectric layer and a polysilicon layer are formed over the isolation insulation layer 32 and the exposed fin structure 20, and then a patterning operation is performed to obtain a gate structure including a sacrificial gate electrode 44 made of polysilicon and a sacrificial gate dielectric layer 42. In some embodiments, the polysilicon layer is patterned by using a hard mask, and the hard mask remains on the sacrificial gate electrode 44 as the blanket insulating layer 46. The hard mask (covering insulating layer 46) includes one or more layers of insulating material. In some embodiments, the blanket insulating layer 46 comprises a silicon nitride layer formed over a silicon oxide layer. In other embodiments, the blanket insulating layer 46 comprises a silicon oxide layer formed over a silicon nitride layer. The insulating material for covering insulating layer 46 may be formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, sacrificial gate dielectric layer 42 comprises one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the thickness of the sacrificial gate dielectric layer 42 is in the range of about 2nm to about 20nm, and in other embodiments in the range of about 2nm to about 10 nm.
Furthermore, as shown in fig. 9B, gate sidewall spacers 48 are formed on the sidewalls of the sacrificial gate structure 40. The sidewall spacers 48 comprise one or more layers of insulating material, such as SiO2, SiN, SiON, SiOCN, or SiCN, formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. Low-k dielectric materials may be used as sidewall spacers. The sidewall spacers 48 are formed by forming a blanket layer of insulating material and performing an anisotropic etch. In one embodiment, the sidewall spacer layer is made of a silicon nitride based material, such as SiN, SiON, SiOCN, or SiCN.
Then, as shown in fig. 10A and 10B, an epitaxial source/drain structure 50 is formed. Fig. 10A is a sectional view along the gate extending direction (X), and fig. 10B is a sectional view along the source-drain direction (Y).
In some embodiments, source/drain structure 50 includes one or more epitaxial semiconductor layers formed in a recess formed in fin structure 20.
In some embodiments, the upper portion of the fin structure 20 is recessed by a dry and/or wet etching operation. In some embodiments, the upper portion of the fin structure 20 is recessed (etched) down to a level equal to or below the upper surface of the isolation insulating layer 32.
The epitaxial source/drain structures 50 are made of one or more layers of semiconductor material having a different lattice constant than the fin structure 20 (channel region). In some embodiments, SiGe or Ge is formed having a higher Ge concentration than the SiGe channel layer 15. An epitaxial source/drain structure 50 is epitaxially formed over an upper portion of the recessed fin structure. In some embodiments, epitaxial source/drain structures 50 are laterally grown and have a diamond shape due to the crystal orientation (e.g., (100) plane) of the substrate formed as fin structure 20.
Can be prepared by using SiH4、Si2H6Or SiCl2H2And/or Si-containing gas such as GeH4、Ge2H6Or GeCl2H2The source/drain epitaxial layer 50 is grown at a temperature of about 600 to 800 c and a pressure of about 80 to 150 torr.
In some embodiments, after the epitaxial source/drain structures 50 are formed, a silicide layer is formed over the epitaxial source/drain structures 50. A metal material, such as Ni, Ti, Ta, and/or W, is formed over the epitaxial source/drain structures 50 and an annealing operation is performed to form a silicide layer. In other embodiments, a silicide material, such as NiSi, TiSi, TaSi, and/or WSi, is formed over the epitaxial source/drain structures 50 and an annealing operation may be performed. The annealing operation is performed at a temperature lower than the temperature of the melting laser annealing operation 80 to prevent further redistribution of the germanium, and the temperature is in the range of about 250 c to about 850 c. The metal material or silicide material is formed by CVD or ALD. In some embodiments, the thickness of the silicide layer is in a range from about 4nm to about 10 nm. The metal material or silicide material formed over the isolation insulating layer 32 is selectively removed before or after the annealing operation. In some embodiments, the silicide layer is formed after the metal gate structure is formed.
Then, as illustrated in fig. 11A and 11B, a metal gate structure 100 is formed. Fig. 11A is a sectional view along the gate extending direction (X), and fig. 11B is a sectional view along the source-drain direction (Y).
After the epitaxial source/drain structures 50 are formed, one or more interlayer dielectric (ILD) layers 60 are formed over the epitaxial source/drain structures 50. In some embodiments, an Etch Stop Layer (ESL) is formed over the source/drain epitaxial layer 50 and the sidewall spacers 48 prior to forming the ILD layer. The ESL is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). Materials for the ILD layer 60 include compounds containing Si, O, C, and/or H such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the ILD layer 60.
After the ILD layer 60 is formed, a planarization operation, such as an etch back process and/or a Chemical Mechanical Polishing (CMP) process, is performed to expose an upper surface of the sacrificial gate electrode layer 44. Then, the sacrificial gate electrode layer 44 is removed, thereby forming a gate spacer. When the sacrificial gate electrode layer 44 is polysilicon and the ILD layer 60 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer. In addition, the sacrificial gate dielectric layer 42 is removed by an appropriate etching process.
A gate dielectric layer 102 is formed over the SiGe fin channel 15. In some embodiments, an interfacial layer (not shown) is formed over the SiGe channel 15. In some embodiments, the interfacial layer may comprise silicon oxide, silicon germanium oxide, or germanium oxide with a thickness of 0.2nm to 1.5 nm. In other embodiments, the thickness of the interfacial layer is in the range of about 0.5nm to about 1.0 nm.
The gate dielectric layer 102 includes one or more layers of dielectric material (such as silicon oxide, silicon nitride, or high-k dielectric material), other suitable dielectric materials, and/or combinations thereof. Examples of high-k dielectric materials include HfO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnia-alumina (HfO)2-Al2O3) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer is formed by, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high density plasma CVD (hdpcvd), or other suitable methods and/or combinations thereof. In some embodiments, the thickness of the gate dielectric layer 102 is in the range of about 1nm to about 10nm, and in other embodiments may be in the range of about 2nm to about 7 nm.
A metal gate electrode is formed over the gate dielectric layer. The metal gate electrode includes one or more work function adjusting layers 104 and a body metal gate electrode layer 106. The work function adjusting layer 104 is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC or a multilayer of two or more of these materials. For a p-channel Fin FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as work function adjusting layers. The body metal gate electrode layer 106 includes any suitable metal material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. After deposition of an appropriate material for the metal gate structure, a planarization operation, such as CMP, is performed.
It should be understood that the FinFET undergoes further CMOS processing to form various components such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like.
Fig. 12 shows an element analysis result using SIMS (secondary ion mass spectrometry) in the depth direction according to an embodiment of the present invention. The samples with the SiGe blanket layer on the Si layer were analyzed. The SiGe layer had a thickness of 30nm and a Ge concentration of 55 atomic% (Si)0.45Ge0.55). The two lines for the BSL show the Ge profile before the fusion laser annealing operation. The two lines of high E and low E show the Ge profile after a fusion laser annealing operation with two different energy conditions. The high E laser energy was 1.72J/cm2And the low E laser energy is 1.58J/cm2。
As shown in fig. 12, the germanium is almost uniformly distributed in the SiGe layer prior to the fusion laser annealing. After the fusion laser annealing operation, the Ge concentration is high near the surface of the SiGe layer and has a peak at about 2-4nm from the surface of the SiGe layer.
When the laser energy is high, the Ge concentration decreases monotonically from the peak to the center of the fin structure. When the laser energy is low, the Ge concentration decreases to a minimum and then increases again.
Fig. 13 shows simulated elemental analysis in the depth direction after Ge distribution. The Ge concentration before redistribution was 20 atomic%. The Ge concentration is about 5-15 atomic% at the surface of the fin structure and the peak concentration is about 30-40% at a depth of about 1-5nm from the surface.
The Ge concentration at the center (7.5nm depth) of the fin structure was about 20-25 atomic% when the fin width W2 (measured at the level of the isolation insulating layer (STI)) was 15 nm. When the fin width W2 was 30nm, the Ge concentration at the center (15nm depth) of the fin structure was about 15-20 atomic%. Comparing the high-energy laser annealing and the low-energy laser annealing, the low-energy laser annealing results in a steep slope from the peak toward the center of the fin structure, as compared with the case of the high-energy laser annealing. In some embodiments, the Ge concentration is graded as the germanium is redistributed by a thermal process, so there is no concentration step in the SiGe fin structure, or there are no multilayers with different compositions with interfaces observable, for example, by Transmission Electron Microscopy (TEM). The Ge profile shown in fig. 13 is substantially symmetrical along the X direction with respect to the center of the fin structure. Thus, when the entire fin structure is cut along the X direction, there are two peaks in the Ge profile.
In some embodiments, the difference between the highest Ge concentration and the lowest Ge concentration is in the range of about 5 to about 35 percentage points.
Fig. 14 shows a theoretical explanation of why higher Ge concentration near the surface of the fin structure (channel region) improves on-current and current leakage. As shown in fig. 14, current IDDepending on the energy band gap Eg and the mobility of the carriers of the semiconductor material constituting the channel region. Referring to the Si band diagram, the band diagram of FIG. 14 shows the surface area (Si)1-xGex) Energy band and central region (Si)1-yGey) X > y. In the fin surface region, since the band gap Eg is small and the carrier mobility is high, the on current can be increased. At the center of the fin structure, Δ Ev is small, and therefore, an inter-band tunneling current can be suppressed.
Fig. 15-20 show exemplary cross-sectional views of various stages for fabricating a Fin FET device, according to another embodiment of the invention. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 15-20, and that some of the operations described below may be replaced or eliminated with respect to further embodiments of the method. The order of operations/processes may be interchanged.
After the fin liner layer 22 is formed as shown in fig. 4, an insulating material layer 30 is formed without performing melting laser annealing as shown in fig. 15.
Similar to fig. 7, an annealing operation 35 is performed as shown in fig. 16. In some embodiments, anneal operation 35 is included, such as at N2RTA using infrared light in an inert gas atmosphere of Ar or He. The temperature of the annealing operation 35 is in the range of about 600 c to about 700 c. In some embodiments, the annealing time is in the range of about 1 second to 60 seconds. As shown in fig. 17, after an anneal operation 35, insulating layer 30 and fin liner layer 22 are recessed to expose an upper portion of fin structure 20 to form isolation insulating layer 32.
As shown in fig. 18, a capping layer 24 is then formed on the exposed SiGe fin structure 20 to recover the Dit defects. A capping layer is also formed on the upper surface of the isolation insulating layer 32. In some embodiments, the capping layer 24 comprises an epitaxial semiconductor layer, such as crystalline Si or SiGe having a lower Ge concentration than the SiGe fin structure. The epitaxial semiconductor layer is selectively formed by epitaxial growth. In some embodiments, the capping layer 24 is not formed on the insulating layer 32 because the capping layer 24 is selectively formed on the SiGe fin structure 20. In other embodiments, the capping layer is amorphous or polycrystalline silicon. In some embodiments, the thickness of the capping layer 24 is in the range of about 5nm to about 10 nm.
As shown in fig. 19, after forming the capping layer, a fusion laser anneal operation 80 is performed to redistribute germanium through the capping layer in the SiGe fin structure 20. In some embodiments, the energy of the laser is about 0.5J/cm2To about 5J/cm2And in other embodiments about 1.0J/cm2To about 2.0J/cm2Within the range of (1). In some embodiments, the laser irradiation time is in the range of 0.1 nanoseconds to 10 nanoseconds, and in other embodiments, in the range of about 0.5 nanoseconds to about 5 nanoseconds. In some embodiments, the SiGe fin structure 20 is heated above the melting point of SiGe. In some embodiments, the temperature of the heating is in the range from about 1200 ℃ to about 1400 ℃. In other embodiments, the temperature ranges from about 800 ℃ to about 1200 ℃. In some embodiments, the fusion laser annealing operation 80 is performed in an inert gas environment (such as N)2Ar or He ambient). The capping layer 24 may protect the SiGe fin structure 20 from undesired oxidation.
In some embodiments, the capping layer 24 is removed after the fusion laser annealing operation. In other embodiments, the cap layer 24 remains and serves as a portion of the channel. In some embodiments, germanium is moved into the cap layer 24, forming a surface SiGe layer 25 as shown in fig. 20. In some embodiments, the Ge concentration of the surface SiGe layer 25 is less than the peak Ge concentration. In other embodiments, the peak is located within the surface SiGe layer 25.
Thereafter, the operations explained with respect to fig. 9A to 11B are performed.
Fig. 21-24 show exemplary cross-sectional views of various stages for fabricating a Fin FET device, according to another embodiment of the invention. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 21-24, and that some of the operations described below may be replaced or eliminated with respect to further embodiments of the method. The order of operations/processes may be interchanged.
As shown in fig. 21, after the fin liner layer 22 is formed as shown in fig. 4, the insulating material layer 30 is formed without performing melting laser annealing.
Similar to fig. 7, an annealing operation 35 is performed as shown in fig. 22. In some embodiments, anneal operation 35 is included, such as at N2RTA using infrared light in an inert gas atmosphere of Ar or He. The temperature of the annealing operation 35 is in the range of about 600 c to about 700 c. In some embodiments, the annealing time is in the range of about 1 second to 60 seconds.
Subsequently, as shown in fig. 23, a fusion laser anneal operation 80 is performed to redistribute the germanium in the SiGe fin structure 20 through the insulating layer 30 and the liner layer 22. In some embodiments, the energy of the laser is about 0.5J/cm2To about 5J/cm2And in other embodiments about 1.0J/cm2To about 2.0J/cm2Within the range of (1). In some embodiments, the laser irradiation time is in the range of 0.1 nanoseconds to 10 nanoseconds, and in other embodiments, in the range of about 0.5 nanoseconds to about 5 nanoseconds. In some embodiments, the SiGe fin structure 20 is heated above the melting point of SiGe. In some embodiments, the temperature of the heating is in the range from about 1200 ℃ to about 1400 ℃. In other embodiments, the temperature ranges from about 800 ℃ to about 1200 ℃. In some embodiments, the fusion laser annealing operation 80 is performed in an inert gas environment (such as N)2Ar or He ambient). When the liner layer 22 is made of silicon nitride, the liner layer 22 may protect the SiGe fin structure 20 from undesired oxidation.
As shown in fig. 24, after anneal operation 80, insulating layer 30 and fin liner layer 22 are recessed to expose an upper portion of fin structure 20 to form isolation insulating layer 32. Thereafter, the operations explained with respect to fig. 9A to 11B are performed.
In the present invention, the channel region of the FinFET is made of SiGe with a non-uniform germanium distribution. In particular, the Ge concentration at or near the surface of the SiGe fin structure is higher than the Ge concentration at the center of the fin structure. With such a SiGe fin structure, on-state current can be enhanced by higher carrier mobility and lower threshold voltage Vt due to higher Ge concentration at the surface region of the fin structure, while current leakage at the sub-threshold region is suppressed due to lower Ge concentration at the central region of the fin structure.
It is to be understood that not all advantages need be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.
According to an aspect of the present invention, in a method of manufacturing a semiconductor device including a Fin FET, a Fin structure is formed having an upper Fin structure made of SiGe and a bottom Fin structure made of a different material from the upper Fin structure, a capping layer is formed over the Fin structure, a thermal operation is performed on the Fin structure covered by the capping layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper Fin structure. The thermal operation changes the germanium profile in the upper fin structure. In one or more of the foregoing and following embodiments, the thermal operation is performed prior to forming the source/drain epitaxial layer. In one or more of the foregoing and following embodiments, the thermal operation is fusion laser annealing. In one or more of the foregoing and following embodiments, the melting laser anneal causes the upper fin structure to melt and then recrystallize, with a germanium profile that is different from the germanium profile prior to performing the melting laser anneal. In one or more of the foregoing and following embodiments, the Ge concentration of the upper fin structure prior to the thermal operation is in a range from 15 atomic% to 30 atomic%. In one or more of the foregoing and following embodiments, after the thermal operation, a Ge concentration at or near a surface of the upper fin structure is higher than a Ge concentration at a center of the upper fin structure. In one or more of the foregoing and following embodiments, the Ge concentration has a peak at a depth in a range of 1nm to 5nm from a surface of the upper fin structure. In one or more of the foregoing and following embodiments, a difference between a highest Ge concentration and a lowest Ge concentration in the upper fin structure is in a range of 5 to 35 percentage points. In one or more of the foregoing and following embodiments, the capping layer is made of silicon nitride. In one or more of the foregoing and following embodiments, the cap layer is an epitaxial semiconductor layer. In one or more of the foregoing and following embodiments, the cover layer includes two or more layers of insulating material. In one or more of the foregoing and following embodiments, the capping layer is at least partially removed after the thermal operation.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device including a Fin FET, a Fin structure is formed having an upper Fin structure made of SiGe and a bottom Fin structure made of a material different from the upper Fin structure, a liner layer is formed over the Fin structure, an insulating material layer is formed over the liner layer, the insulating material layer and the liner layer are recessed to expose an upper portion of the upper Fin structure, a capping layer is formed over the exposed upper portion of the upper Fin structure, a thermal operation is performed on the Fin structure having the capping layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper Fin structure. The thermal operation changes the germanium profile in the upper fin structure. In one or more of the foregoing and following embodiments, the Ge concentration of the upper fin structure prior to the thermal operation is in a range from 15 atomic% to 30 atomic%. In one or more of the foregoing and following embodiments, the capping layer is an epitaxially formed Si layer or an epitaxially formed SiGe having a lower Ge concentration than the upper fin structure prior to thermal operation. In one or more of the foregoing and following embodiments, the thickness of the capping layer is in a range of 5nm to 10 nm. In one or more of the foregoing and following embodiments, the thermal operation is fusion laser annealing. In one or more of the foregoing and following examples, the energy of the fusion laser anneal is at 1.0J/cm2To 2.0J/cm2Within the range of (1). In one or more of the foregoing and following embodiments, a duration of the fusion laser anneal is in a range of 0.5 nanoseconds to 5 nanoseconds.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device including a Fin FET, a Fin structure is formed having an upper Fin structure made of SiGe and a bottom Fin structure made of a material different from the upper Fin structure, a liner layer is formed over the Fin structure, an insulating material layer is formed over the liner layer, a thermal operation is performed on the Fin structure through the insulating material layer and the liner layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper Fin structure. The thermal operation changes the germanium profile in the upper fin structure.
According to an aspect of the present invention, a semiconductor device includes: a fin structure having a channel region and source/drain regions; a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and a source/drain epitaxial layer formed in the source/drain region. The channel region includes SiGe having a non-uniform Ge concentration such that the Ge concentration at or near the surface of the fin structure is higher than the Ge concentration at the center of the fin structure. In one or more of the foregoing and following embodiments, the Ge concentration is graded in the channel region. In one or more of the foregoing and following embodiments, the Ge concentration at or near a surface of the channel region in contact with the gate dielectric layer is higher than the Ge concentration at a center of the channel region. In one or more of the foregoing and following embodiments, the Ge concentration has a peak at a depth in a range of 1nm to 5nm from a surface of the channel region. In one or more of the foregoing and following embodiments, the Ge concentration at the peak is in a range of 30 atomic% to 40 atomic%. In one or more of the foregoing and following embodiments, the lowest Ge concentration in the channel region is in a range of 10 atomic% to 25 atomic%. In one or more of the foregoing and following embodiments, a difference between a highest Ge concentration and a lowest Ge concentration in the channel region is in a range of 5 to 35 percentage points. In one or more of the foregoing and following embodiments, the semiconductor device further includes an isolation insulating layer from which the fin structure protrudes. In one or more of the foregoing and following embodiments, the fin structure includes a fin bottom structure and an upper fin portion including the channel region, and the fin bottom structure is made of a different semiconductor material than the upper fin portion. In one or more of the foregoing and following embodiments, the semiconductor device further includes a liner layer disposed on a side of the fin bottom structure. In one or more of the foregoing and following embodiments, a liner layer covers a bottom of the upper fin. In one or more of the foregoing and following embodiments, a width of the channel along a gate extending direction at a level of an upper surface of the isolation insulating layer is in a range from 15nm to 30 nm. In one or more of the foregoing and following embodiments, the Ge concentration has two peaks. In one or more of the foregoing and following embodiments, the Ge concentration at the surface of the channel region is in a range of 5 atomic% to 15 atomic%.
According to another aspect of the present invention, a semiconductor device includes: a fin structure having a channel region and source/drain regions; a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and a source/drain epitaxial layer formed in the source/drain region. The channel region includes a SiGe layer having a non-uniform Ge concentration and an overlying semiconductor layer located over the SiGe layer. In one or more of the foregoing and following embodiments, the Ge concentration in the SiGe layer at or near the interface between the SiGe layer and the overlying semiconductor layer is higher than the Ge concentration at the center of the channel region. In one or more of the foregoing and following embodiments, the Ge concentration has a peak at a depth in a range of 1nm to 5nm from an interface of the channel region. In one or more of the foregoing and following embodiments, the Ge concentration at the peak is in a range of 30 atomic% to 40 atomic%. In one or more of the foregoing and following embodiments, the Ge concentration at the peak is higher than the Ge concentration in the capping semiconductor layer.
According to another aspect of the present invention, a semiconductor device includes: a fin structure having a fin bottom structure and an upper fin portion including a channel region and source/drain regions; an isolation insulating layer from which a channel region protrudes; a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and a source/drain epitaxial layer formed in the source/drain region. The Ge concentration at or near the surface of the channel region in contact with the gate dielectric layer is higher than the Ge concentration at the center of the channel region.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.