Power amplifier device and amplitude limiting circuit thereof
阅读说明：本技术 一种功放装置及其限幅电路 (Power amplifier device and amplitude limiting circuit thereof ) 是由 杨颖� 于 2020-12-15 设计创作，主要内容包括：本发明公开了一种限幅电路,该电路包括：控制单元,在与斩波信号对应的电平信号成预定比例的脉冲信号宽度达到第一阈值的情况下,输出控制信号；多个放大单元中的至少一个放大单元的正输入端和负输入端,在所述控制信号的作用下被短路；多个放大单元中正输入端和负输入端未短路的放大单元对输入信号进行放大处理,获得第一放大信号；斩波单元对第一放大信号进行处理,输出斩波信号。本方案的电路与传统的D类功放硬限幅相比,实现了软限幅,有效抑制过大的输入信号,消除了放音时的破音现象,提高了系统的可靠性。(The invention discloses a clipping circuit, which comprises: a control unit that outputs a control signal when a pulse signal width in a predetermined ratio to a level signal corresponding to the chopper signal reaches a first threshold value; a positive input terminal and a negative input terminal of at least one of the plurality of amplifying units, which are short-circuited by the control signal; amplifying an input signal by using an amplifying unit of which the positive input end and the negative input end are not short-circuited in a plurality of amplifying units to obtain a first amplified signal; the chopper unit processes the first amplified signal and outputs a chopper signal. Compared with the traditional D-type power amplifier hard amplitude limiting, the circuit of the scheme realizes soft amplitude limiting, effectively inhibits overlarge input signals, eliminates the sound breaking phenomenon during sound reproduction and improves the reliability of the system.)
1. A clipping circuit, comprising:
a control unit that outputs a control signal when a pulse signal width in a predetermined ratio to a level signal corresponding to the chopper signal reaches a first threshold value;
a plurality of amplifying units, a positive input terminal and a negative input terminal of at least one of the amplifying units being short-circuited by the control signal; amplifying an input signal by using an amplifying unit of which the positive input end and the negative input end are not short-circuited in a plurality of amplifying units to obtain a first amplified signal;
the chopper unit processes the first amplified signal and outputs a chopper signal;
a power output stage connected with the chopping unit.
2. The slicing circuit according to claim 1, wherein the control unit does not output the control signal in a case where a pulse signal width in a predetermined proportion to a level signal corresponding to the chopping signal does not reach the first threshold value;
the amplifying units amplify the input signals to obtain second amplified signals;
and the chopping unit is used for processing the second amplified signal and outputting a chopped signal.
3. The clipping circuit of claim 1, wherein the plurality of amplification units comprise a first fully differential amplifier and a second fully differential amplifier,
the positive output end of the first fully differential amplifier is connected with the positive input end of the second fully differential amplifier, and the negative output end of the first fully differential amplifier is connected with the negative input end of the second fully differential amplifier; the positive output end of the second fully differential amplifier is connected with the positive input end of the chopping unit, and the negative output end of the second fully differential amplifier is connected with the negative input end of the chopping unit; and the output end of the pulse signal generating circuit is connected with the positive input end and the negative input end of the second fully differential amplifier.
4. The clipping circuit of claim 3, wherein the control unit comprises a detection unit and a clipping unit;
a detection unit that outputs a level signal corresponding to the chopper signal based on a duty ratio of the chopper signal;
and a clipping unit that outputs a pulse signal proportional to the level signal based on the level signal corresponding to the chopper signal.
5. The clipping circuit of claim 4, wherein the clipping unit comprises a pulse trigger switch and a pulse signal generation circuit, the pulse signal generation circuit comprising:
the circuit comprises a first comparator, a second comparator, a first operational amplifier, a second operational amplifier and a NAND gate circuit;
the positive input end of the first operational amplifier is connected with a reference voltage, and the negative input end of the first operational amplifier is connected with a resistor voltage division point;
the positive input end of the second operational amplifier is connected with the output end of the detection unit, and the negative input end of the second operational amplifier is connected with a resistor voltage division point; the output end of the first operational amplifier is connected with the positive input end of the first comparator; the output end of the second operational amplifier is connected with the negative input end of the second comparator;
the negative input end of the first comparator and the positive input end of the second comparator input oscillating triangular waves with the same frequency as the carrier waves of the chopping unit; the output end of the first comparator and the output end of the second comparator are respectively connected with a NAND gate circuit;
the NAND gate circuit is connected with the input end of the second fully differential amplifier;
one end of the pulse trigger switch is connected with the output end of the pulse signal generating circuit, and the other end of the pulse trigger switch is connected with the positive input end and the negative input end of the second fully differential amplifier; the pulse trigger switch is controlled to be switched on or switched off by a pulse signal sent by a pulse signal generating circuit.
6. The amplitude limiting circuit according to claim 5, wherein an operating frequency of the pulse signal generating circuit is the same as an operating frequency of the chopping unit, and the chopping unit is a PWM chopping unit.
7. The clipping circuit of claim 4, wherein the detection unit comprises a first set of dual switches, a second set of dual switches, a first capacitor and a second capacitor;
the first group of duplex switches comprises a first switch and a second switch, the first switch is connected with the reference voltage end, and the second switch is grounded;
the second group of duplex switches comprises a third switch and a fourth switch, the third switch is connected with the first group of duplex switches, and the fourth switch is connected with the output end of the module;
the first capacitor is grounded and connected between the third switch and the fourth switch in parallel, and the second capacitor is grounded and connected between the fourth switch and the output end of the module in parallel;
the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.
8. The clipping control circuit of any of claims 1 to 7, wherein the acquired signal is an analog audio signal.
9. A power amplifier arrangement, characterized in that it comprises a limiter circuit according to any of claims 1-7.
Technical Field
The invention relates to the technical field of signal conversion, in particular to a power amplifier device and an amplitude limiting circuit thereof.
Background
The existing amplitude limiting control technology of audio class-D power amplifiers generally sets an amplitude limiting threshold value to control the level of analog output voltage in a set track, so as to limit the output amplitude. The amplitude limiting threshold voltage can be obtained by a peripheral divider resistor, the internal amplitude limiting module compares the amplitude limiting threshold voltage with the output of the signal path after the two-stage integrator, and when the amplitude of the output waveform after the integrator is higher than the set voltage, the internal comparator opens the current pulling path through logic control, so that the input signal is additionally shunted, and the preceding-stage input signal of the integrator is limited. Under the condition that the power supply voltage, the closed loop gain, the load and the input amplitude are the same, the output amplitude is related to the amplitude limiting threshold value.
The common amplitude limiting control technology has a certain amplitude limiting effect, but the output amplitude is limited on a fixed amplitude and is not immediately related to the size of an input signal, and the output is subjected to top cutting or bottom cutting after passing through an amplitude limiting circuit, so that sound breaking is caused by output hard amplitude limiting.
Disclosure of Invention
Compared with the traditional hard amplitude limiting of a class D power amplifier, the scheme has the advantages that soft amplitude limiting is realized, overlarge input signals are effectively restrained, the sound breaking phenomenon during sound reproduction is eliminated, and the reliability of a system is improved.
Another object of this scheme is to provide a power amplifier device, this device includes above-mentioned amplitude limiting circuit.
In order to achieve the purpose, the scheme is as follows:
a clipping circuit, comprising:
a control unit that outputs a control signal when a pulse signal width in a predetermined ratio to a level signal corresponding to the chopper signal reaches a first threshold value;
a plurality of amplifying units, a positive input terminal and a negative input terminal of at least one of the amplifying units being short-circuited by the control signal; amplifying an input signal by using an amplifying unit of which the positive input end and the negative input end are not short-circuited in a plurality of amplifying units to obtain a first amplified signal;
the chopper unit processes the first amplified signal and outputs a chopper signal;
a power output stage connected with the chopping unit.
Preferably, the control unit does not output the control signal when a pulse signal width in a predetermined ratio to a level signal corresponding to the chopper signal does not reach the first threshold value;
the amplifying units amplify the input signals to obtain second amplified signals;
and the chopping unit is used for processing the second amplified signal and outputting a chopped signal.
Preferably, the plurality of amplifying units includes a first fully differential amplifier and a second fully differential amplifier,
the positive output end of the first fully differential amplifier is connected with the positive input end of the second fully differential amplifier, and the negative output end of the first fully differential amplifier is connected with the negative input end of the second fully differential amplifier; the positive output end of the second fully differential amplifier is connected with the positive input end of the chopping unit, and the negative output end of the second fully differential amplifier is connected with the negative input end of the chopping unit;
and the output end of the pulse signal generating circuit is connected with the positive input end and the negative input end of the second fully differential amplifier.
Preferably, the control unit comprises a detection unit and a limiting unit;
a detection unit that outputs a level signal corresponding to the chopper signal based on a duty ratio of the chopper signal;
and a clipping unit that outputs a pulse signal proportional to the level signal based on the level signal corresponding to the chopper signal.
Preferably, the clipping unit includes a pulse trigger switch and a pulse signal generating circuit, and the pulse signal generating circuit includes:
the circuit comprises a first comparator, a second comparator, a first operational amplifier, a second operational amplifier and a NAND gate circuit;
the positive input end of the first operational amplifier is connected with a reference voltage, and the negative input end of the first operational amplifier is connected with a resistor voltage division point;
the positive input end of the second operational amplifier is connected with the output end of the detection unit, and the negative input end of the second operational amplifier is connected with a resistor voltage division point;
the output end of the first operational amplifier is connected with the positive input end of the first comparator; the output end of the second operational amplifier is connected with the negative input end of the second comparator;
the negative input end of the first comparator and the positive input end of the second comparator input oscillating triangular waves with the same frequency as the carrier waves of the chopping unit; the output end of the first comparator and the output end of the second comparator are respectively connected with a NAND gate circuit;
the NAND gate circuit is connected with the input end of the second fully differential amplifier;
one end of the pulse trigger switch is connected with the output end of the pulse signal generating circuit, and the other end of the pulse trigger switch is connected with the positive input end and the negative input end of the second fully differential amplifier; the pulse trigger switch is controlled to be switched on or switched off by a pulse signal sent by a pulse signal generating circuit.
Preferably, the operating frequency of the pulse signal generating circuit is the same as the operating frequency of the chopper unit, and the chopper unit is a PWM chopper unit.
Preferably, the detection unit includes a first group of duplex switches, a second group of duplex switches, a first capacitor and a second capacitor;
the first group of duplex switches comprises a first switch and a second switch, the first switch is connected with the reference voltage end, and the second switch is grounded;
the second group of duplex switches comprises a third switch and a fourth switch, the third switch is connected with the first group of duplex switches, and the fourth switch is connected with the output end of the module;
the first capacitor is grounded and connected between the third switch and the fourth switch in parallel, and the second capacitor is grounded and connected between the fourth switch and the output end of the module in parallel;
the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.
Preferably, the acquired signal is an analog audio signal.
In a second aspect, a power amplifier device is provided, which includes the above amplitude limiting control circuit.
The scheme has the following beneficial effects:
compared with the traditional D-type power amplifier hard amplitude limiting, the scheme realizes soft amplitude limiting, effectively inhibits overlarge input signals, eliminates the sound breaking phenomenon during sound reproduction and improves the reliability of the system.
Drawings
In order to illustrate the implementation of the solution more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the solution, and that other drawings may be derived from these drawings by a person skilled in the art without inventive effort.
Fig. 1 is a schematic diagram of a clipping circuit;
FIG. 2 is a schematic diagram of a detection unit;
fig. 3 is a schematic diagram of a clipping unit;
wherein, 1-a first fully differential amplifier; 2-a second fully differential amplifier; 3-PWM chopping unit; 4-a detection unit; 5-a clipping unit; 6-power output stage; 7-a first comparator; 8-a second comparator; 9-a first operational amplifier; 10-second operational amplifier.
Detailed Description
Embodiments of the present solution will be described in further detail below with reference to the accompanying drawings. It is clear that the described embodiments are only a part of the embodiments of the present solution, and not an exhaustive list of all embodiments. It should be noted that, in the present embodiment, features of the embodiment and the embodiment may be combined with each other without conflict.
The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
Due to the characteristics of high efficiency and small volume of the class-D power amplifier, the class-D power amplifier is gradually used for the audio amplification technology along with the continuous deepening of the digital audio technology, and the key step of the application of the class-D power amplifier is the modulation of audio signals. The existing control technology can not realize the timely correlation with the size of the input signal, so that the sound breaking phenomenon can occur in the output signal. The scheme aims to provide the amplitude limiting control circuit, soft amplitude limiting of signals is achieved, the sound breaking phenomenon is eliminated, and system reliability is improved.
A clipping circuit, the circuit comprising: the power amplifier comprises a control unit, a plurality of amplifying units, a chopping unit and a power output stage; the control unit outputs a control signal when a pulse signal width in a predetermined ratio to a level signal corresponding to the chopper signal reaches a first threshold value; the positive input end and the negative input end of at least one amplifying unit in the plurality of amplifying units are short-circuited under the action of the control signal; amplifying an input signal by using an amplifying unit of which the positive input end and the negative input end are not short-circuited in a plurality of amplifying units to obtain a first amplified signal; the chopping unit processes the first amplified signal and outputs a chopping signal to the power output stage;
the control unit does not output the control signal in a case where a pulse signal width in a predetermined proportion to a level signal corresponding to the chopper signal does not reach a first threshold value; the amplifying units amplify the input signals to obtain second amplified signals; and the chopping unit processes the second amplified signal and outputs a chopping signal to the power output stage.
The chopping unit in the scheme is a PWM chopping unit.
As shown in fig. 1, in one embodiment, the signal amplification unit includes a first fully differential amplifier 1 and a second fully differential amplifier 2; after being amplified by the first fully differential amplifier 1 and the second fully differential amplifier 2, an externally input analog signal enters the PWM chopper unit 3 and is converted into a PWM (pulse width modulation) signal; the detection unit 4 is connected with the PWM chopping unit 3 and the amplitude limiting unit 5; the clipping unit 5 is connected to the input of the second fully differential amplifier 2.
The positive output end of the first fully differential amplifier 1 is connected with the positive input end of the second fully differential amplifier 2, and the negative output end of the first fully differential amplifier 1 is connected with the negative input end of the second fully differential amplifier 2; the positive output end of the second fully differential amplifier 2 is connected with the positive input end of the chopper unit 3, and the negative output end of the second fully differential amplifier 2 is connected with the negative input end of the chopper unit 3; the first fully differential amplifier 1 and the second fully differential amplifier 2 function to linearly amplify an input analog audio signal; the PWM chopping unit 3 functions to convert the analog audio signal into a PWM pulse width modulated signal whose duty ratio varies with the amplitude of the audio signal.
In one embodiment, the operating frequency of the pulse signal generating circuit is the same as the operating frequency of the PWM chopping unit. In one embodiment, the control unit comprises a detection unit 4 and a clipping unit 5;
the detection unit 4 outputs a level signal corresponding to the chopping signal based on the duty ratio of the chopping signal output by the PWM chopping unit 3; the clipping unit 5 outputs a pulse signal proportional to the level signal.
The detection unit 4 detects the duty ratio of the PWM chopper signal and outputs a level signal proportional to the duty ratio; after the input level signal rises to a set value, the amplitude limiting unit 5 starts to output a pulse signal with the pulse width proportional to the input level, and drives the pulse trigger switch to short circuit the two input ends of the second fully differential amplifier, so that the effective amplitude of the power amplifier channel is limited.
As shown in fig. 2, the detection circuit 4 includes a first set of duplex switches, a second set of duplex switches, a first capacitor C1 and a second capacitor C2; the first group of the duplex switches comprises a first switch k1 and a second switch k2, the first switch k1 is connected with a reference voltage end VREF, and the second switch k2 is grounded; the second group of double-link switches comprises a third switch k3 and a fourth switch k4, the third switch k3 is connected with the first group of double-link switches, and the fourth switch k4 is connected with the output end of the module; a first capacitor C1 is connected in parallel to ground between the third switch k3 and the fourth switch k4, and a second capacitor C2 is connected in parallel to ground between the fourth switch k4 and the output of the module.
In another embodiment, the capacitance of the first capacitor C1 is less than the capacitance of the second capacitor C2.
As shown in fig. 3, in one embodiment, the pulse signal generating circuit 5 includes: a first comparator 7, a second comparator 8, a first operational amplifier 9, a second operational amplifier 10 and a nand gate circuit;
the positive input end of the first operational amplifier 9 is connected with a reference voltage, and the negative input end is connected with a resistor voltage division point; the positive input end of the second operational amplifier 10 is connected with the output end of the detection circuit 4, and the negative input end is connected with the resistance voltage division point; the output end of the first operational amplifier 9 is connected with the positive input end of the first comparator 7; the output end of the second operational amplifier 10 is connected with the negative input end of the second comparator 8; the negative input end of the first comparator 7 and the positive input end of the second comparator 8 input oscillating triangular waves with the same frequency as the carrier waves of the PWM chopping unit; the output end of the first comparator 7 and the output end of the second comparator 8 are respectively connected with a NAND gate circuit; the nand gate is connected to the input of the second fully differential amplifier 2.
In one embodiment, the amplitude limiting circuit further comprises a pulse trigger switch k5, the pulse trigger switch k5 is controlled to be turned on or off by a pulse signal sent by the pulse signal generating circuit 5, one end of the pulse trigger switch k5 is connected with the output end of the pulse signal generating circuit 5, and the other end is connected with the positive input end and the negative input end of the second fully differential amplifier 2; the detection circuit 4 detects the duty ratio of the PWM chopper signal and outputs a level signal proportional to the duty ratio; after the input level signal rises to a set value, the pulse signal generating circuit starts to output a pulse signal with the pulse width proportional to the input level, and drives the pulse trigger switch k5 to short circuit the two input ends of the second fully differential amplifier 2, so that the effective amplitude of a power amplification channel is limited.
In this embodiment, the control signal is a pulse signal output by the pulse signal generating circuit, the pulse trigger switch is controlled by the pulse signal to be opened or closed, and the switch k5 is closed when the high level of the pulse signal is output. The positive input end and the negative input end of the second fully differential amplifier are short-circuited, differential input signals are restrained, and externally input signals are amplified by the first fully differential amplifier, input to the PWM chopping unit for chopping processing and then output as chopped signals. If the pulse signal generating circuit does not output high-level pulse signals, the pulse trigger switch is not closed and is in an open state, the positive input end and the negative input end of the first fully differential amplifier and the second fully differential amplifier can normally input signals, all the input ends are not short-circuited, and the input signals are not inhibited.
In another embodiment, the externally acquired signal is an analog audio signal.
In a second aspect, the present scheme further provides a power amplifier device including the above amplitude limiting circuit.
Compared with the traditional D-type power amplifier hard amplitude limiting, the scheme realizes soft amplitude limiting, effectively inhibits overlarge input signals, eliminates the sound breaking phenomenon during sound reproduction and improves the reliability of the system.
The present solution is specifically described below with reference to the accompanying drawings.
As shown in fig. 1, the clipping control circuit is composed of a first fully differential amplifier 1, a second fully differential amplifier 2, a PWM chopping unit 3, a detection unit 4, a clipping unit 5, and a power output stage 6. The input analog audio signals are amplified by the first fully differential amplifier 1 and the second fully differential amplifier 2, and the amplification factor is determined by R2/R1+ R4/R3; the amplified audio signal enters the PWM chopping unit 3, and is output by the power output stage 6 after chopping processing. The PWM chopping unit 3 compares the input audio signal with a triangular wave operating at a fixed carrier frequency. And generating a series of pulses under the condition of carrier frequency, wherein the duty ratio of the PWM pulse is in direct proportion to the amplitude of the audio signal in each carrier period, and completing the modulation of the audio signal on the carrier signal. For large positive inputs, the duty cycle is close to 100%, and for large negative inputs, the duty cycle is close to 0%. Full modulation occurs if the audio amplitude exceeds the amplitude of the triangle wave, at which point the pulse train stops switching and the duty cycle is 0% or 100% during a particular period.
In this embodiment, the detection unit 4 converts the change of the pulse width into the change of the level by the charge pump charging operation principle, and outputs the amplitude detection level proportional to the duty ratio of the chopping signal of the PWM chopping unit 3.
As shown in fig. 2, the detection unit 4 includes two capacitors C1, C2 and two sets of duplex switches. The first group of the duplex switches comprises a first switch k1 and a second switch k2, the first switch k1 is connected with a reference voltage end VREF, and the second switch k2 is grounded; selecting a point C between the first switch and the second switch, wherein the second group of duplex switches are connected with the first group of duplex switches through the point C; the second group of duplex switches comprises a third switch k3 and a fourth switch k4, the third switch k3 is connected with the point C of the first group of duplex switches, and the fourth switch k4 is connected with the output end of the detection unit 4; the first capacitor C1 is connected in parallel at a point a between the third switch k3 and the fourth switch k4, the second capacitor C2 is connected in parallel at a point B between the fourth switch k4 and the output terminal of the detection unit 4, the first capacitor C1 is grounded, and the second capacitor C2 is grounded.
The first switch k1 is turned on during the high-low level period of the pulse output from the PWM chopper unit 3, and the second switch k2 is turned off during the high-low level period of the pulse output from the PWM chopper unit 3. When the input signal is small, the frequency of the pulse signal output by the PWM is close to the switching frequency, and the signals of the control switches k1 and k2 obtained through logic operation are in low level, the switches k1 and k2 are disconnected, and the amplitude limiting start control signal is zero. The duty ratio of the PWM pulse signal corresponding to a large audio input is large, the duty ratios of the signals controlling the switches k1 and k2 are also increased, and the larger the high pulse width period is, the longer the on time of the first switch k1 is and the shorter the on time of the second switch k2 is. The level of the point C is influenced by the first switch k1 and the second switch k2, the level of the point A is closer to the reference voltage VREF along with the increase of the audio input signal, the long turn-on period of the first switch k1 and the short turn-on period of the second switch k2, and otherwise, the level is closer to the zero level;
the third switch k3 and the fourth switch k4 are controlled by an eight-frequency division signal of the carrier clock, when the edge of the carrier eight-frequency division clock jumps, the third switch k3 and the fourth switch k4 switch, the third switch k3 is turned on/the fourth switch k4 is turned off, the level of the point C is transmitted to the point A, and the level of the point B is 0V; the third switch k3 is turned off/the fourth switch k4 is turned on, the charge on the first capacitor C1 is discharged to the second capacitor C2, and the point B is raised; the switch is switched, after the third switch k3 is switched on/the fourth switch k4 is switched off, the point A tends to the point C, and the point B keeps the last level; the switch is switched again, and after the third switch k3 turns off the fourth switch k4, the point B is raised due to the charging of the second capacitor C2. Thus, the charged level of the first capacitor C1 is transmitted into the second capacitor C2 during each switch switching, the capacitance of the first capacitor C1 is designed to be much smaller than that of the second capacitor C2, and when the point C is the VREF voltage, the level on the first capacitor C1 is at VREF/maintains the last period of discharging low level during clock on/off; and the level on the second capacitor C2 is raised to the low level of C1 each time the clock switches to turn on the fourth switch k 4. The low level at point a rises step by step, and the carrier divided by eight clock signals are filtered out because the capacitance of the second capacitor C2 is large enough. The output signal of the detection unit 4 is a ramp level that rises as the PWM duty cycle increases.
In this embodiment, the amplitude limiting unit 5 is configured to compare the output level of the detecting unit 4 with a triangular wave signal having the same frequency as the PWM carrier in a comparator to obtain a pulse output with a variable pulse width, so as to control an input signal of the second fully-differential amplifier 2 and limit the effective gain of the power amplifier channel.
As shown in fig. 3, the clipping unit 5 includes a pulse signal generating circuit composed of a first comparator 7, a second comparator 8, a first operational amplifier 9, a second operational amplifier 10, and a not gate circuit, and a pulse trigger switch k5, the pulse trigger switch k5 being connected to an output terminal of the pulse signal generating circuit.
The positive input end of the first operational amplifier 9 is connected with the reference voltage VREF, and the negative input end is connected with the resistance voltage division point; the positive input end of the second operational amplifier 10 is connected with the output end of the detection unit 4; the output end of the first operational amplifier 9 is connected with the positive input end of the first comparator 7; the output end of the second operational amplifier 10 is connected with the negative input end of the second comparator 8; the output end of the first comparator 7 and the output end of the second comparator 8 are respectively connected with a NAND gate circuit; the NAND gate circuit is connected with the input end of the second fully differential amplifier 2; the pulse trigger switch k5 is connected in parallel between the two input terminals of the second fully differential amplifier 2.
The positive input of the first comparator 7 is VxThe negative terminal of the second comparator 8 is inputted with VyThe negative terminal of the first operational amplifier 9 is inputted with a voltage dividing point VzVREF level is the VCC midpoint level, and the first operational amplifier 9 compares VREF with VzVoltage and output the comparison result to VxAnd (4) an end. The level signal output by the detection unit 4 is input to the positive terminal of the second operational amplifier 10, and is followed and output to one end of the resistor r2, namely V, through the operational amplifier 10yEnd, VREF level is VCC midpoint level; the negative/positive inputs of the first comparator 7 and the second comparator 8 are oscillating triangular waves with the same frequency as the PWM carrier wave, and the amplitude range of the triangular wave signals is VH～VL. Vx, Vy signals and triangular wave signals are compared in a first comparator 7 and a second comparator 8, Vx、VyThe signal cuts the periodic variation level of the triangular wave to obtain pulse output with variable pulse width.
When the input signal is small, the level of the output of the detection unit 4 is low, VyNear zero level. V of power VCC after resistance voltage divisionzNear the reference midpoint VREF, the level V of the output of the first operational amplifier 9xClose to the power supply VCC. As the input signal increases, the output level V of the detection unit 4yLifting, level VxAnd gradually changing from high to low until Vy is approximately equal to Vx and VREF.
When input level V of the first comparator 7xHigher than VHWhen the output level of the first comparator 7 is high, on the contrary, when the input level V of the first comparator 7 is inputtedxBelow VHAt this time, the output level of the first comparator 7 is low, and the first comparator 7 is at this timeIs at an output level VoxAn active low pulse is generated; equivalently, the input level V of the second comparator 8yBelow VLWhen the output level of the second comparator 8 is high, the input level V of the second comparator 8 is set toyHigher than VLAt this time, the output level of the second comparator 8 is low, and at this time, the output level V of the second comparator 8 is lowoyAn active low pulse is generated.
The output levels V of the first comparator 7 and the second comparator 8ox、VoyAnd a high effective pulse signal is generated by the NAND gate and fed to the input end of the second fully differential amplifier 2, and when the pulse signal drives the pulse trigger switch k5 to be conducted, the input end of the second fully differential amplifier 2 is instantaneously suppressed to be a common-mode direct current level, so that the effective amplitude of a power amplifier channel is limited.
Compared with the traditional D-type power amplifier hard amplitude limiting, the scheme realizes soft amplitude limiting, effectively inhibits overlarge input signals, eliminates the sound breaking phenomenon during sound reproduction and improves the reliability of the system.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.