阅读说明：本技术 一种时钟多路复用器及电子设备 (Clock multiplexer and electronic equipment ) 是由 谭亚伟 王潘丰 王海力 崔运东 于 2021-06-21 设计创作，主要内容包括：本申请实施例公开了一种时钟多路复用器不仅包括两个时钟输入模块,还包括两个时钟信号产生模块,其中,时钟输入模块不仅通过时钟信号输出端输出时钟输出信号给第一逻辑门,还通过使能信号输出端输出使能信号,该使能信号和选择信号共同激发时钟信号产生模块产生时钟信号作为该时钟输入模块的时钟输入信号。可见,时钟多路复用器中的两个时钟输入模块的时钟输入信号均由各自的使能信号和选择信号共同激发产生,因此,切换时钟时选择信号发生改变,导致两个时钟输入模块的时钟输入信号产生改变。在切换时钟前目的时钟可自动开启,在切换时钟后源时钟可自动关闭,无需附加其他控制电路使得时钟多路复用器的使用电路简化。(The embodiment of the application discloses a clock multiplexer which comprises two clock input modules and two clock signal generation modules, wherein the clock input modules not only output clock output signals to a first logic gate through a clock signal output end, but also output enable signals through an enable signal output end, and the enable signals and selection signals jointly stimulate the clock signal generation modules to generate clock signals to serve as clock input signals of the clock input modules. It can be seen that the clock input signals of the two clock input modules in the clock multiplexer are both generated by respective enabling signals and selecting signals which are jointly activated, so that the selecting signals are changed when the clocks are switched, and the clock input signals of the two clock input modules are changed. The destination clock can be automatically started before the clock is switched, and the source clock can be automatically closed after the clock is switched, so that other control circuits are not required to be added, and the using circuit of the clock multiplexer is simplified.)

1. A clock multiplexer, comprising:

the clock comprises a first clock input module, a second clock input module, a first clock signal generation module, a second clock signal generation module and a first logic gate;

the first clock input module comprises a first clock signal input end, a first selection signal input end, a first clock signal output end and a first enable signal output end;

the second clock input module comprises a second clock signal input end, a second selection signal input end, a second clock signal output end and a second enable signal output end;

the first enable signal output end and the first selection signal input end are respectively connected with two input ends of the first clock signal generation module, and the output end of the first clock signal generation module is connected with the first clock signal input end;

the second enable signal output end and the second selection signal input end are respectively connected with two input ends of the second clock signal generation module, and the output end of the second clock signal generation module is connected with the second clock signal input end;

the first clock signal output end and the second clock signal output end are respectively connected with two input ends of the first logic gate, and a second logic gate is connected between the first selection signal input end and the second selection signal input end. .

2. The clock multiplexer of claim 1,

the first clock signal generation module comprises a third logic gate and a first clock signal generation unit, wherein two input ends of the third logic gate are respectively connected with the first selection signal input end and the first enable signal output end, an output end of the third logic gate is connected with an input end of the first clock signal generation unit, and an output end of the first clock signal generation unit is connected with the first clock signal input end;

the second clock signal generation module comprises a fourth logic gate and a second clock signal generation unit, two input ends of the fourth logic gate are respectively connected with the second selection signal input end and the second enable signal output end, an output end of the fourth logic gate is connected with an input end of the second clock signal generation unit, and an output end of the second clock signal generation unit is connected with the second clock signal input end.

3. The clock multiplexer of any one of claims 1 to 3,

the first clock input module comprises a fifth logic gate, a sixth logic gate, a first trigger and a second trigger; a first input end of the fifth logic gate is connected with the first selection signal input end, an output end of the fifth logic gate is connected with an input end of the first flip-flop, an output end of the first flip-flop is connected with an input end of the second flip-flop, a first output end of the second flip-flop is connected with the first enable signal output end, a second output end of the second flip-flop is further connected with a first input end of the sixth logic gate, and the first clock signal input end is respectively connected with a control end of the first flip-flop, a control end of the second flip-flop and a second input end of the sixth logic gate;

the second clock input module comprises a seventh logic gate, an eighth logic gate, a third trigger and a fourth trigger; a first input end of the seventh logic gate is connected to the second selection signal input end, an output end of the seventh logic gate is connected to an input end of the third flip-flop, an output end of the third flip-flop is connected to an input end of the fourth flip-flop, a first output end of the fourth flip-flop is connected to the second enable signal output end, a second output end of the fourth flip-flop is further connected to a first input end of the eighth logic gate, and the second clock signal input end is respectively connected to a control end of the third flip-flop, a control end of the fourth flip-flop, and a second input end of the eighth logic gate;

the output end of the sixth logic gate and the output end of the eighth logic gate are respectively connected with two input ends of the second logic gate;

a second output end of the second flip-flop is connected with a second input end of the seventh logic gate, and a second output end of the fourth flip-flop is connected with a second input end of the fifth logic gate.

4. The clock multiplexer of claim 3,

the first clock signal generation module further comprises a ninth logic gate; a first input end of the ninth logic gate is connected with an output end of the third logic gate, a second input end of the ninth logic gate is connected with a second output end of the fourth flip-flop, and an output end of the ninth logic gate is connected with an input end of the first clock signal generating unit;

the second clock signal generation module further comprises a tenth logic gate, wherein a first input end of the tenth logic gate is connected with an output end of the fourth logic gate, and a second input end of the tenth logic gate is connected with a second output end of the second flip-flop.

5. The clock multiplexer of claim 4,

the first clock signal generating unit comprises a first clock gate, two input ends of the third clock gate are respectively connected with the output end of the third logic gate and the first clock signal generator, and the output end of the third clock gate is connected with the input end of the first clock signal;

the second clock signal generating unit comprises a first clock gate, two input ends of the fourth clock gate are respectively connected with the output end of the fourth logic gate and the second clock signal generator, and the output end of the fourth clock gate is connected with the input end of the second clock signal.

6. The clock multiplexer of claim 4,

the first clock signal generating unit comprises a first clock generating circuit, wherein the input end of the first clock generating circuit is connected with the output end of the third logic gate, and the output end of the first clock generating circuit is connected with the first clock signal input end;

the second clock signal generating unit comprises a second clock generating circuit, an input end of the second clock generating circuit is connected with an output end of the fourth logic gate, and an output end of the second clock generating circuit is connected with the second clock signal input end.

7. The clock multiplexer of claim 4, wherein the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops.

8. The clock multiplexer of claim 4, wherein the second logic gate is a NOT gate, and the first, third, and fourth logic gates are OR gates, and the fifth, sixth, seventh, eighth, ninth, and tenth logic gates are AND gates.

9. An electronic device comprising a clock multiplexer according to any one of claims 1 to 8.

Technical Field

The embodiment of the application relates to the field of digital circuits, in particular to a clock multiplexer and electronic equipment.

Background

The integrated circuit includes a plurality of functional circuit blocks working together, and each functional circuit is driven by a clock. Different functional circuit blocks may require clock signals of different frequencies, for example, a first functional circuit block of an integrated circuit operates on a first clock signal and a second functional circuit block operates on a second clock signal, and such an integrated circuit is referred to as an asynchronous integrated circuit.

A Clock Multiplexer (Clock MUX) is used to provide Clock signals with different frequencies, and the selection of the Clock signals can be performed according to specific requirements. However, in the current clock multiplexer, the destination clock cannot be automatically turned on before the clock is switched, and the source clock cannot be automatically turned off after the clock is switched, which can be realized by adding other control circuits, and thus the use circuit of the clock multiplexer is complicated.

Disclosure of Invention

It is an object of the present application to provide a clock multiplexer that improves upon at least some of the above mentioned technical problems.

The embodiment of the application is realized as follows:

the present application provides a clock multiplexer, comprising:

the clock comprises a first clock input module, a second clock input module, a first clock signal generation module, a second clock signal generation module and a first logic gate;

the first clock input module comprises a first clock signal input end, a first selection signal input end, a first clock signal output end and a first enable signal output end;

the second clock input module comprises a second clock signal input end, a second selection signal input end, a second clock signal output end and a second enable signal output end;

the first enable signal output end and the first selection signal input end are respectively connected with two input ends of the first clock signal generation module, and the output end of the first clock signal generation module is connected with the first clock signal input end;

the second enable signal output end and the second selection signal input end are respectively connected with two input ends of the second clock signal generation module, and the output end of the second clock signal generation module is connected with the second clock signal input end;

and a second logic gate is connected between the first selection signal input end and the second selection signal input end, and the first clock signal output end and the second clock signal output end are respectively connected with two input ends of the first logic gate.

It is to be appreciated that the present application discloses a clock multiplexer for implementing either-or clock signal selection. The clock multiplexer not only comprises two clock input modules, but also comprises two clock signal generating modules. The clock input module not only outputs a clock signal to the first logic gate through the clock signal output end, but also outputs an enable signal through the enable signal output end, and the enable signal and the selection signal jointly excite the clock signal generation module to generate the clock signal as the clock input signal of the clock input module. It can be seen that the clock input signals of the two clock input modules in the clock multiplexer are both generated by respective enabling signals and selecting signals which are jointly activated, so that the selecting signals are changed when the clocks are switched, and the clock input signals of the two clock input modules are changed. The destination clock can be automatically started before the clock is switched, and the source clock can be automatically closed after the clock is switched, so that other control circuits are not required to be added, and the using circuit of the clock multiplexer is simplified.

In an alternative embodiment of the present application, the first clock signal generating module includes a third logic gate and a first clock signal generating unit, two input terminals of the third logic gate are respectively connected to the first selection signal input terminal and the first enable signal output terminal, an output terminal of the third logic gate is connected to an input terminal of the first clock signal generating unit, and an output terminal of the first clock signal generating unit is connected to the first clock signal input terminal;

the second clock signal generation module comprises a fourth logic gate and a second clock signal generation unit, two input ends of the fourth logic gate are respectively connected with the second selection signal input end and the second enable signal output end, an output end of the fourth logic gate is connected with an input end of the second clock signal generation unit, and an output end of the second clock signal generation unit is connected with the second clock signal input end.

In an alternative embodiment of the present application, the first clock input module includes a fifth logic gate, a sixth logic gate, a first flip-flop, and a second flip-flop; a first input end of the fifth logic gate is connected with the first selection signal input end, an output end of the fifth logic gate is connected with an input end of the first flip-flop, an output end of the first flip-flop is connected with an input end of the second flip-flop, a first output end of the second flip-flop is connected with the first enable signal output end, a second output end of the second flip-flop is further connected with a first input end of the sixth logic gate, and the first clock signal input end is respectively connected with a control end of the first flip-flop, a control end of the second flip-flop and a second input end of the sixth logic gate;

the second clock input module comprises a seventh logic gate, an eighth logic gate, a third trigger and a fourth trigger; a first input end of the seventh logic gate is connected to the second selection signal input end, an output end of the seventh logic gate is connected to an input end of the third flip-flop, an output end of the third flip-flop is connected to an input end of the fourth flip-flop, a first output end of the fourth flip-flop is connected to the second enable signal output end, a second output end of the fourth flip-flop is further connected to a first input end of the eighth logic gate, and the second clock signal input end is respectively connected to a control end of the third flip-flop, a control end of the fourth flip-flop, and a second input end of the eighth logic gate;

the output end of the sixth logic gate and the output end of the eighth logic gate are respectively connected with two input ends of the second logic gate;

a second output end of the second flip-flop is connected with a second input end of the seventh logic gate, and a second output end of the fourth flip-flop is connected with a second input end of the fifth logic gate.

In an alternative embodiment of the present application, the first clock signal generation module further comprises a ninth logic gate; a first input end of the ninth logic gate is connected with an output end of the third logic gate, a second input end of the ninth logic gate is connected with a second output end of the fourth flip-flop, and an output end of the ninth logic gate is connected with an input end of the first clock signal generating unit;

the second clock signal generation module further comprises a tenth logic gate, wherein a first input end of the tenth logic gate is connected with an output end of the fourth logic gate, and a second input end of the tenth logic gate is connected with a second output end of the second flip-flop.

It will be appreciated that the clock input signals of two clock input blocks in the clock multiplexer are not only generated by the activation of the respective enable signal and select signal, but are also influenced by the signal output from the second output of the latter flip-flop of the other clock input block. When the clock signals are switched, after the selection signals are changed, the period of the early starting clock pulse of the target clock signal is shortened to be a fixed number, the output clock signal of the clock multiplexer is converted into the target clock signal at the speed as fast as possible, and the reaction speed of the clock multiplexer is improved.

In an alternative embodiment of the present application, the first clock signal generation unit includes a first clock gate, two input terminals of the first clock gate are respectively connected to the output terminal of the third logic gate and the first clock signal generator, and an output terminal of the first clock gate is connected to the first clock signal input terminal; the second clock signal generation unit comprises a second clock gate, two input ends of the second clock gate are respectively connected with the output end of the fourth logic gate and the second clock signal generator, and the output end of the second clock gate is connected with the input end of the second clock signal.

In the case of using clock gating as the clock signal generation unit, the destination clock may be automatically turned on before the switching clock, but the first pulse after the destination clock signal is turned on may be incomplete.

In an alternative embodiment of the present application, the first clock signal generating unit includes a first clock generating circuit, an input terminal of the first clock generating circuit is connected to the output terminal of the third logic gate, and an output terminal of the first clock generating circuit is connected to the first clock signal input terminal; the second clock signal generating unit comprises a second clock generating circuit, an input end of the second clock generating circuit is connected with an output end of the fourth logic gate, and an output end of the second clock generating circuit is connected with the second clock signal input end.

In the case of using the clock generation circuit as the clock signal generation unit, the destination clock can be automatically turned on before switching the clocks, and since the clock generation circuit starts to operate after being turned on, it can be ensured that the first pulse after the clock signal is turned on is complete.

In an alternative embodiment of the present application, the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops.

In an alternative embodiment of the present application, the second logic gate is a not gate, the first logic gate, the third logic gate, and the fourth logic gate are an or gate, and the fifth logic gate, the sixth logic gate, the seventh logic gate, the eighth logic gate, the ninth logic gate, and the tenth logic gate are and gates.

In a second aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes any one of the clock multiplexers described above.

The beneficial effects of the electronic device provided by the second aspect of the present application are the same as those of the first aspect, and are not described herein again.

To make the aforementioned objects, features and advantages of the present application more comprehensible, alternative embodiments accompanied with figures are described in detail below.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:

FIG. 1 is an internal circuit diagram of a prior art clock multiplexer;

FIG. 2 is a timing diagram of the clock multiplexer shown in FIG. 1;

FIG. 3 is an internal circuit diagram of a clock multiplexer provided herein;

FIG. 4 is an internal circuit diagram of a clock signal generation unit of the clock multiplexer shown in FIG. 3;

fig. 5 is an internal circuit diagram of another clock signal generation unit of the clock multiplexer shown in fig. 3;

FIG. 6 is an internal circuit diagram of a clock multiplexer provided herein;

FIG. 7 is a timing diagram of the clock multiplexer shown in FIG. 4;

FIG. 8 is a timing diagram of the clock multiplexer shown in FIG. 5;

fig. 9 is a timing diagram of the clock multiplexer shown in fig. 6.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 shows an internal circuit diagram of a clock multiplexer 100 in the prior art, wherein the clock multiplexer 100 includes a first clock input module 110, a second clock input module 120 and a first logic gate 130; the first clock input module 110 includes a first clock signal input terminal C1, a first selection signal input terminal S1, and a first clock signal output terminal C3; the second clock input module 120 includes a second clock signal input terminal C2, a second selection signal input terminal S2, and a second clock signal output terminal C4. A second logic gate 140 is connected between the first selection signal input terminal S1 and the second selection signal input terminal S2, and a first clock signal output terminal C3 and a second clock signal output terminal C4 are respectively connected to two input terminals of the first logic gate 130. The first selection signal input terminal S1 is the selection signal input terminal of the clock multiplexer 100, the output terminal C5 of the first logic gate 130 is the output terminal of the clock signal of the clock multiplexer 100, and the first logic gate 130 is an or gate.

Shown in fig. 2 is a timing diagram of the clock multiplexer shown in fig. 1. It can be seen that the output timing signal clk _ out at the output terminal C5 is converted from the source clock signal clk _ in0 to the destination clock signal clk _ in1 after the selection signal s is converted from low to high. Since the clock signal inputs C1 and C2 of the clock input modules 110 and 120 are directly provided by the two clock signals clk _ in1 and clk _ in0, the destination clock is always on before the clocks are switched, and the source clock is not automatically turned off after the clocks are switched. If the destination clock is turned on before the switching clock and the source clock is turned off after the switching clock, additional control circuits are needed, which complicates the circuit for using the clock multiplexer.

In order to solve the above problem, as shown in fig. 3, the present application provides a clock multiplexer 200, which includes: a first clock input module 210, a second clock input module 220, a first clock signal generation module 250, a second clock signal generation module 260, and a first logic gate 230.

The first clock input module 210 includes a first clock signal input terminal C1, a first selection signal input terminal S1, a first clock signal output terminal C3, and a first enable signal output terminal D1. The second clock input module 220 includes a second clock signal input terminal C2, a second selection signal input terminal S2, a second clock signal output terminal C4, and a second enable signal output terminal 2.

The first enable signal output terminal 1 and the first select signal input terminal S1 are respectively connected to two input terminals of the first clock signal generating module 250, and the output terminal C6 of the first clock signal generating module 250 is connected to the first clock signal input terminal C1. The second enable signal output terminal D2 and the second select signal input terminal S2 are respectively connected to two input terminals of the second clock signal generation module 260, and the output terminal C7 of the second clock signal generation module 260 is connected to the second clock signal input terminal C2.

A second logic gate 240 is connected between the first selection signal input terminal S1 and the second selection signal input terminal S2, and the first clock signal output terminal C3 and the second clock signal output terminal C4 are respectively connected to two input terminals of the first logic gate 230, in this embodiment, the second logic gate 140 is a not gate, and the first logic gate 130 is an or gate.

It is to be appreciated that the present application discloses a clock multiplexer for implementing either-or clock signal selection. The clock multiplexer includes not only two clock input blocks 210 and 220 but also two clock signal generation blocks 250 and 260. The clock input modules 210 and 220 not only output clock output signals to the first logic gate 230 through the clock signal output terminals C3 and C4, but also output enable signals through the enable signal output terminals D1 and D2, which together activate the clock signal generation modules 250 and 260 to generate clock signals clk _ in1 and clk _ in0 as clock input signals of the clock input modules 210 and 220, respectively. It can be seen that the clock input signals of the two clock input modules in the clock multiplexer are both generated by respective enabling signals and selecting signals which are jointly activated, so that the selecting signals are changed when the clocks are switched, and the clock input signals of the two clock input modules are changed. The destination clock can be automatically started before the clock is switched, and the source clock can be automatically closed after the clock is switched, so that other control circuits are not required to be added, and the using circuit of the clock multiplexer is simplified.

In an alternative embodiment of the present application, as shown in fig. 3, the first clock signal generating module 250 includes a third logic gate 251 and a first clock signal generating unit 252, two input terminals of the third logic gate 251 are respectively connected to the first selection signal input terminal S1 and the first enable signal output terminal D1, an output terminal of the third logic gate 251 is connected to an input terminal of the first clock signal generating unit 252, and an output terminal of the first clock signal generating unit 252 is connected to the first clock signal input terminal C1; the second clock signal generating module 260 includes a fourth logic gate 261 and a second clock signal generating unit 262, two input terminals of the fourth logic gate 261 are respectively connected to the second selection signal input terminal S2 and the second enable signal output terminal D2, an output terminal of the fourth logic gate 261 is connected to an input terminal of the second clock signal generating unit 262, and an output terminal of the second clock signal generating unit 262 is connected to the second clock signal input terminal C2.

In an alternative embodiment of the present application, as shown in fig. 4, the first clock signal generating unit 252 includes a first clock gate 2520, two input terminals of the first clock gate 2520 are respectively connected to the output terminal of the third logic gate 251 and the first clock signal generator, and an output terminal of the first clock gate 2520 is connected to the first clock signal input terminal C1; the second clock signal generating unit 262 includes a second clock gate 2620, two inputs of the second clock gate 2620 are respectively connected to an output of the fourth logic gate 261 and the second clock signal generator, an output of the second clock gate 2620 is connected to a second clock signal input C2, in this embodiment, the third logic gate 251 and the fourth logic gate 261 are or gates.

Shown in fig. 7 is a timing diagram of the clock multiplexer shown in fig. 4. As can be seen, after the select signal s goes from low to high at X3, the output timing signal clk _ out at the output terminal C5 is converted from the source clock signal clk _ in0 to the destination clock signal clk _ in1 at X5. After the selection signal s is turned from low to high at X3, the destination clock is automatically turned on in advance before X5, and the destination clock signal clk _ in1 is continuously output; the source clock is automatically turned off at X4 after the selection signal s is turned from low to high at X3, and the source clock signal clk _ in0 is lowered to low level, so that the use circuit of the clock multiplexer is simplified without adding other control circuits.

In the case of using clock gating as the clock signal generation unit, it can be seen in the timing diagram shown in fig. 7 that the destination clock is automatically turned on after the select signal s goes from low to high at X3, but the first pulse after the destination clock signal is turned on may be incomplete and the source clock and the destination clock have invalid clock pulses when they are turned on and off. In order to reduce the number of invalid clock pulses when the source clock and the destination clock are turned on and off, it may be implemented that the first pulse after the destination clock is turned on may be complete, as shown in fig. 5, the first clock signal generating unit 252 may include a first clock generating circuit 2521, an input terminal of the first clock generating circuit 2521 is connected to the output terminal of the third logic gate 251, and an output terminal of the first clock generating circuit 2521 is connected to the first clock signal input terminal C1; the second clock signal generating unit 262 includes a second clock generating circuit 2621, an input terminal of the second clock generating circuit 2621 is connected to an output terminal of the fourth logic gate 261, and an output terminal of the second clock generating circuit 2621 is connected to the second clock signal input terminal C2, in this embodiment, the third logic gate 251 and the fourth logic gate 261 are or gates, in this embodiment, the first clock generating circuit 2521 and the second oscillator clock generating circuit 2621 are oscillators, and may be other clock generating circuits, which is not limited in this application.

FIG. 8 is a timing diagram of the clock multiplexer shown in FIG. 5; in the case of using the clock generation circuit as the clock signal generation unit, the destination clock can be automatically turned on before switching the clocks, and since the clock generation circuit starts to operate after being turned on, it can be ensured that the first pulse after the clock signal is turned on is complete.

With continued reference to fig. 3, in an alternative embodiment of the present application, the first clock input module 210 includes a fifth logic gate 212, a sixth logic gate 211, a first flip-flop 213, and a second flip-flop 214. An input terminal of the fifth logic gate 212 is connected to the first selection signal input terminal S1, and an output terminal of the fifth logic gate 212Is connected with the input terminal of the first flip-flop 213, the Q output terminal of the first flip-flop 213 is connected with the input terminal of the second flip-flop 214, the Q output terminal of the second flip-flop 214 is connected with the first enable signal output terminal D1, the second flip-flop 214 is connected with the second enable signal output terminal D1An output terminal is connected to one input terminal of the sixth logic gate 211, an output terminal of the sixth logic gate 211 is connected to the first clock signal output terminal C3, and the first clock signal input terminal C1 is connected to a control terminal of the first flip-flop 213, a control terminal of the second flip-flop 214, and another input terminal of the sixth logic gate 211, respectively.

The second clock input module 220 includes a seventh logic gate 222, an eighth logic gate 221, a third flip-flop 223, and a fourth flip-flop 224. An input terminal of the eighth logic gate 222 is connected to the second selection signal input terminal S2, an output terminal of the eighth logic gate 222 is connected to an input terminal of the third flip-flop 223, a Q output terminal of the third flip-flop 223 is connected to an input terminal of the fourth flip-flop 224, a Q output terminal of the fourth flip-flop 224 is connected to the second enable signal output terminal D2, a Q output terminal of the fourth flip-flop 224 is further connected to an input terminal of the eighth logic gate 221, an output terminal of the eighth logic gate 221 serves as a second clock signal output terminal C4, and the second clock signal input terminal C2 is respectively connected to a control terminal of the third flip-flop 223, a control terminal of the fourth flip-flop 224, and another input terminal of the eighth logic gate 221.

Of the second flip-flop 214An output terminal connected to another input terminal of the seventh logic gate 222, of the fourth flip-flop 224The output terminal is connected to another input terminal of the fifth logic gate 212, and in the embodiment of the present application, the fifth logic gate 212, the sixth logic gate 211, the seventh logic gate 222, and the eighth logic gate 221 are and gates.

As shown in fig. 6, the present application provides another clock multiplexer 300, and in contrast to the clock multiplexer 200 shown in fig. 3, in the clock multiplexer 300, the first clock signal generation module 350 includes a third logic gate 351, a ninth logic gate 352, and a first clock signal generation unit 353.

Two input terminals of the third logic gate 351 are respectively connected to the first selection signal input terminal S1 and the first enable signal output terminal D1, and two input terminals of the ninth logic gate 352 are respectively connected to an output terminal of the third logic gate 351 and an output terminal of the fourth flip-flop 324The output terminal is connected, the output terminal of the ninth logic gate 352 is connected to the input terminal of the first clock signal generating unit 353, the output terminal of the first clock signal generating unit 353 is connected to the first clock signal input terminal C1, and the ninth logic gate 352 is an and gate in this embodiment.

The second clock signal generation module 360 includes a fourth logic gate 361, a tenth logic gate 362 and a second clock signal generation unit 363; two input terminals of the fourth logic gate 361 are connected to the second selection signal input terminal S2 and the second enable signal output terminal 2, respectively, and two input terminals of the tenth logic gate 362 are connected to an output terminal of the fourth logic gate 361 and the second flip-flop 314, respectivelyThe output terminal of the tenth logic gate 362 is connected to the input terminal of the second clock signal generating unit 363, and the output terminal of the second clock signal generating unit 363 is connected to the second clock signal input terminal C2, in this embodiment, the tenth logic gate 362 is an and gate.

It will be appreciated that the clock input signals of two clock input blocks in the clock multiplexer are not only generated by the respective enable and select signals, but are also subject to a subsequent flip-flop of the other clock input blockInfluence of the signal output by the output terminal. When switching clock signals, after the selection signal is changedThe early opening pulse period of the clock signal is shortened to a fixed number, the output clock signal of the clock multiplexer is converted into the target clock signal as fast as possible, and the reaction speed of the clock multiplexer is improved.

Fig. 9 is a timing diagram of clock multiplexer 300 shown in fig. 6. As can be seen, after the select signal s goes from low to high at X9, the output timing signal clk _ out at the output terminal C5 is converted from the source clock signal clk _ in0 to the destination clock signal clk _ in1 at X10. The destination clock, which is advanced by one pulse relative to X10, automatically turns on the continuous output destination clock signal clk _ in1 after X9. In fig. 7 and 8, the destination clock is advanced by two pulses with respect to the time when the select signal s transitions from low to high. It can be seen that clock multiplexer 300 has a shorter early start pulse period for the destination clock signal than clock multiplexer 200 and is fixed to 1 pulse. The output clock signal of the clock multiplexer is converted into the target clock signal as fast as possible, and the reaction speed of the clock multiplexer is improved.

On the other hand, the embodiment of the present application further provides an electronic device, where the electronic device includes any one of the clock multiplexers described above.

The beneficial effects of the electronic device provided by the application are the same as those of the first aspect, and are not described herein again.

The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. Especially, as for the device, apparatus and medium type embodiments, since they are basically similar to the method embodiments, the description is simple, and the related points may refer to part of the description of the method embodiments, which is not repeated here.

Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.

The expressions "first", "second", "said first" or "said second" used in various embodiments of the present disclosure may modify various components regardless of order and/or importance, but these expressions do not limit the respective components. The above description is only configured for the purpose of distinguishing elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

When an element (e.g., a first element) is referred to as being "operably or communicatively coupled" or "connected" (operably or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the element is directly connected to the other element or the element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), no element (e.g., a third element) is interposed therebetween.

The above description is only an alternative embodiment of the application and is illustrative of the technical principles applied. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the spirit of the invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.