阅读说明：本技术 具有阶梯状轮廓的降低表面电场和漂移结构的横向dmos器件 (Lateral DMOS device with stepped profile for reducing surface electric field and drift structure ) 是由 T·C·H·姚 R·德索萨 T·D·克利尔 于 2020-09-28 设计创作，主要内容包括：本发明题为“具有阶梯状轮廓的降低表面电场和漂移结构的横向DMOS器件”。本发明公开了一种用于制造MOSFET的方法,该方法包括在半导体衬底的表面上形成源极区和漏极区,形成栅极区,形成主体扩散区,形成金属结构,以及形成漂移区,该漂移区包括n型漂移结构,该n型漂移结构具有阶梯状掺杂剂浓度分布,其中掺杂剂浓度沿着从该器件的该漏极区到该源极区的横向方向增加。(The invention provides a lateral DMOS device with a stepped profile to reduce surface electric field and drift structure. A method for fabricating a MOSFET includes forming a source region and a drain region on a surface of a semiconductor substrate, forming a gate region, forming a body diffusion region, forming a metal structure, and forming a drift region, the drift region including an n-type drift structure having a stepped dopant concentration profile, wherein the dopant concentration increases along a lateral direction from the drain region to the source region of the device.)

1. A lateral MOSFET, comprising:

a substrate;

a source region;

a gate region;

a drain region; and

a drift region disposed between the gate region and the drain region, the drift region including a drift structure having a stepped dopant concentration profile with a dopant concentration increasing in a lateral direction from the drain region to the source region.

2. The MOSFET of claim 1, wherein the drift structure having the stepped dopant concentration profile comprises a series of overlapping drift diffusion regions formed along the lateral direction from the drain region to the source region.

3. The MOSFET of claim 1, wherein the drift structure having the stepped dopant concentration profile comprises a series of drift diffusion regions extending to a reduced depth along the lateral direction from the drain region to the source region.

4. The MOSFET of claim 1, further comprising:

a reduced surface electric field (RESURF) structure disposed in the drift region below the drift structure, the reduced surface electric field structure comprising a plurality of reduced surface electric field diffusion regions formed along the lateral direction from the drain region to the source region.

5. The MOSFET of claim 4, wherein each of the plurality of resurf diffusion regions is formed at a respective depth in the substrate, and wherein the depth of the plurality of resurf diffusion regions decreases along the lateral direction from the drain region to the source region.

6. The MOSFET of claim 4, wherein each of the plurality of resurf diffusion regions has a respective dopant concentration, and wherein the dopant concentrations of the plurality of resurf diffusion regions increase in steps along the lateral direction from the drain region to the source region.

7. The MOSFET of claim 6, wherein each overlapping drift diffusion region of the series of overlapping drift diffusion regions has a width in a lateral direction and is associated with one of the plurality of reduced surface electric field diffusion regions having the same width in the lateral direction or having a different width.

8. The MOSFET of claim 6, wherein at least one overlapping drift diffusion region of the series of overlapping drift diffusion regions is not associated with any reduced surface electric field diffusion region.

9. A method for fabricating a MOSFET, the method comprising:

forming a source region and a drain region on a surface of a semiconductor substrate;

forming a gate region;

forming a body diffusion region;

forming a metal structure; and

forming a drift region comprising an n-type drift structure having a stepped dopant concentration profile with a dopant concentration increasing in a lateral direction from the drain region to the source region of the device.

10. The method of claim 9, wherein forming the n-type drift structure comprises implanting two or more lightly doped drift diffusion regions through a surface of the semiconductor substrate, and wherein the two or more lightly doped drift diffusion regions have a stepped dopant concentration profile, wherein the dopant concentration in the two or more lightly doped drift diffusion regions increases in steps in a horizontal direction from an edge of the drain diffusion region to the body diffusion region.

11. The method of claim 9, wherein forming the drift region further comprises forming a p-type reduced surface electric field (RESURF) structure having a stepped dopant concentration profile, wherein dopant concentration increases along a lateral direction from the drain region to the source region of the device.

12. The method of claim 11, wherein forming the p-type resurf structure comprises forming one or more lightly doped p-type diffusion regions confined in a region deeper than the n-type drift structure.

Technical Field

The present description relates to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) for power supply applications.

Background

Lateral double-diffused MOS transistors (LDMOS) may be a preferred device in high voltage and smart power supply applications. Whether discrete or embedded in a BCD (BIPOLAR-CMOS-DMOS) technology platform, the primary performance criteria for LDMOS devices is a specific on-state resistance (Rsp) at a given breakdown voltage (BVdss). In practice, lower Rsp devices may result in smaller devices, which in turn may result in more devices being fabricated on a single wafer.

Disclosure of Invention

A lateral double diffused MOS device (LDMOS) fabricated on a semiconductor substrate has a drift diffusion region that includes a stepped profile drift structure and a stepped profile reduced surface electric field (RESURF) structure. In an n-type LDMOS device, the stepped profile drift structure is n-type and the surface electric field reducing structure is p-type.

In an example embodiment of an n-type LDMOS device, the stepped profile drift structure has an increasing doping concentration along a lateral or horizontal line from the drain side to the source side of the device.

In some example embodiments of the n-type LDMOS device, the p-type stepped profile reduced surface electric field structure has an increasing doping concentration along a lateral line from the drain side to the source side of the device.

In some example embodiments of the n-type LDMOS device, the p-type stepped profile reduced surface electric field structure is located at a reduced depth in the semiconductor substrate along a lateral line from the drain side to the source side of the device.

In example embodiments, the doping profile of the stepped profile drift structure and the stepped profile reduced surface electric field structure may be optimized to minimize the on-state resistance (Rsp) of the device at a given breakdown voltage (BVdss).

Drawings

Fig. 1 shows a half-pitch cross-section of a device cell of an example n-type LDMOS device.

Fig. 2 shows an exemplary n-type LDMOS device with different numbers of nDrift and pResurf diffusion regions.

Fig. 3 illustrates an example n-type LDMOS device including an n-type stepped profile drift structure and a p-type stepped profile reduced surface electric field structure.

Fig. 4 shows an example n-type LDMOS device fabricated on a substrate with an n-type buried layer (nBL).

Figure 5 shows a cross-sectional view of impact ionization lines and equipotential lines of a test device.

Fig. 6 is a graph showing Rsp and BVdss values for various groups of doping concentration values for the test device of fig. 5.

Fig. 7-15 show schematic views of a substrate as it is processed through various steps of an exemplary nLDMOS device fabrication process.

Fig. 16 illustrates an example method for fabricating an nLDMOS device.

Detailed Description

High voltage MOSFET devices may include thick and low doped epitaxial layers, which may make integration with low voltage circuitry difficult. The on-state resistance of such devices is large due to the high resistivity of thick and low doped epitaxial layers. To obtain a lower Rsp, a reduced surface electric field (RESURF) structure may be used in the device during the blocking state of the device to obtain a fully depleted area in the drift region. The reduced surface electric field structure utilizes a lightly doped substrate (e.g., a p-doped substrate) and a thin epitaxial layer (e.g., an n-type epitaxial layer) to block high voltages in the device. Lateral diodes formed from a thin n-type epitaxial layer on a lightly doped p-substrate may have a higher breakdown voltage than conventional lateral diodes without a reduced surface electric field.

Example LDMOS devices disclosed herein include reduced surface electric field structures and drift structures that can significantly improve device performance (e.g., lower Rsp and higher BVdss). The reduced surface electric field structure or the drift structure (or both) may include a stepped dopant concentration profile. The LDMOS device may be an n-type (nLDMOS) or p-type (pLDMOS) device. For the sake of brevity, only the n-type version of the device is described herein, but it should be understood that the n-type and p-type dopants can be interchanged to describe the p-type version of the device.

An example LDMOS device may have four terminals, e.g., a drain terminal, a gate terminal, a source terminal, and a body terminal. If the source and body terminals are electrically connected together to form a single terminal (commonly referred to as the source), the device may have three terminals, namely a drain terminal, a gate terminal, and a source terminal.

An example LDMOS device may have a drift diffusion region that includes a reduced surface electric field structure having a stepped dopant concentration profile (stepped profile reduced surface electric field structure) and a drift structure having a stepped dopant concentration profile (stepped profile drift structure).

The stepped profile reduced surface electric field structure may have an increasing dopant concentration along a horizontal or lateral line from the drain side to the source side of the device, or a decreasing diffusion depth along a horizontal or lateral line from the drain side to the source side, or a combination of both (i.e., an increasing dopant concentration and a decreasing diffusion depth along a lateral line). The stepped profile drift structure may have an increasing doping concentration along a horizontal or lateral line from the drain side to the source side of the device. In example embodiments, the doping profile that reduces the surface electric field and the drift structure may be designed to maximize the breakdown voltage and minimize the resistance of the device.

In an example embodiment, the nLDMOS device may be fabricated in a BCD technology platform.

In an example embodiment, the nLDMOS device may include one or more of the following structures:

a. surface field reducing oxide between polysilicon gate and drift region

b. Self-aligned body diffusion region with link diffusion region on source side of device

c. Butted source body connected with silicide

d. Body separated from source by field oxide (shallow trench isolation (STI), local oxidation of silicon (LOCOS), etc.)

e. A vertically isolated Buried Layer (BL) diffusion of the device body from the substrate is provided beneath the entire device.

The diffusion regions (i.e., doped regions) described herein may be formed, for example, by ion implantation followed by thermal diffusion.

In an example, when an nLDMOS device has a BL diffusion region (e.g., n-type BL (nbl)), the device may be further laterally isolated by an additional ring-shaped n-type diffusion region around the device. The additional n-type diffusion region may be deep enough to physically contact the BL diffusion region and shallow enough to physically contact a standard metal contact/silicide/source-drain (SD) structure at the substrate surface.

In some embodiments, an nLDMOS device may be fabricated on the surface of a p-doped layer of silicon (e.g., a pEpi layer) grown or deposited on a semiconductor substrate. Two Active Areas (AA) -a source Active Area (AA) and a drain AA-may be formed on the surface of the semiconductor substrate. The two AAs can be laterally separated by growing or depositing a relatively thin (e.g., <20nm) dielectric layer (e.g., a gate oxide layer) on the pEpi layer. The two AA's can also be laterally separated by a reduced surface field oxide layer formed on the surface of the semiconductor substrate as a thicker (e.g., >30nm) dielectric (e.g., silicon dioxide) layer. In some embodiments, the gate oxide layer may have the same thickness as the reduced surface field oxide layer, and the source AA and the drain AA may be combined into a single AA.

Further, in device fabrication, a gate (e.g., a heavily doped n-type polysilicon polygon) may be formed that overlaps a portion (but not all) of the source AA and a portion of the reduced surface field oxide layer. Spacers (e.g., dielectric structures) may be formed around the entire gate. A heavily doped n-type diffusion region (commonly referred to as nLink or nLDD) may be formed at the surface of the source AA and under the spacer.

In an example embodiment, the nLDD may be provided by a CMOS technology component of the BCD platform on which the device is fabricated, while the nLink may be dedicated to the nLDMOS.

Further, in device fabrication, a source diffusion region (e.g., a heavily doped n-type diffusion region) may be formed through the surface of the source AA and along the spacers, and a body tap diffusion region (e.g., a heavily doped p-type diffusion region) may be formed through the surface of the source AA and along the source diffusion region. In some embodiments, the body tap region may contact the source diffusion region. In some embodiments, the body tap region may be separated from the source diffusion region by an additional isolation dielectric (e.g., field oxide such as LOCOS or STI) that separates the source AA into two AAs (source AA and body AA).

Further, in device fabrication, a drain diffusion region (e.g., a heavily doped n-type diffusion region) may be formed through the surface of the drain AA.

In device fabrication, metallization structures may be fabricated on the surface of both the semiconductor substrate and the gate on the following regions: a gate polygon, a drain diffusion region, a source diffusion region, and a body tap region. The metallization structure may include a silicide contact (e.g., metal contact + silicide, etc.). The metal structure may define a gate terminal, a drain terminal, a source terminal, and a body terminal of the nLDMOS device.

In example embodiments where the body tap region and the source diffusion region are in contact, the source terminal and the body terminal may be connected together as a single source terminal.

Further, in device fabrication, a body diffusion region (e.g., a lightly doped p-type diffusion region) may be formed through the surface of the semiconductor substrate. The body diffusion region may extend vertically from the surface of the semiconductor substrate to reach deeper than the nLink/nLDD, the source diffusion region, and the body tap region, and may extend horizontally (laterally) to surround the body tap region, the source diffusion region, the nLink/nLDD, and the portion of the source AA covered by the gate. The portion of the body diffusion region that overlaps the gate may form a channel of the device. The channel may have a channel length (Lg). The nLink/nLDD may provide electrical continuity between the channel and source diffusions, which may in turn provide electrical continuity for the source terminal.

The body diffusion regions may be formed by using a p-type ion implant sequence through a single mask (e.g., a CMOS pWell mask) or through multiple masks (e.g., a CMOS pWell + self-aligned pBody mask).

Further, in device fabrication, a drift diffusion region (nDrift diffusion region) (e.g., a lightly doped n-type diffusion region) may be formed through the surface of the substrate. The nDrift diffusion region may extend vertically from the surface of the substrate to reach deeper than the drain diffusion region and the reduced surface field oxide layer, and may extend horizontally to surround at least a portion of the drain diffusion region, the reduced surface field oxide layer, and the source AA.

In some embodiments, the nDrift diffusion region and the body diffusion region may be in contact. In some embodiments, the nDrift diffusion region and the bulk diffusion region may be separated. In some embodiments, the nDrift diffusion region and the body diffusion region may overlap.

The nDrift diffusion region may have a stepped dopant concentration profile, e.g., with a doping concentration that gradually increases in a horizontal (lateral) direction from an edge of the drain diffusion region toward a junction of the drain diffusion region and the body diffusion region.

In an example embodiment, a sequence or chain of n-type implants through partially overlapping masks (e.g., a minimum of two partially overlapping masks) may be used to generate a stair-stepped profile of an nDrift diffusion region. Each nDrift diffusion region may have a width (step) corresponding to an opening of a corresponding mask.

Further, in device fabrication, a surface field reducing diffusion region (pResurf diffusion region) (e.g., a lightly doped p-type diffusion region) may be formed through the surface of the substrate at a depth below the surface of the substrate. The pResurf diffusion region may be limited to a region deeper than the nDrift diffusion region and may not extend vertically to the surface of the semiconductor substrate. However, in some embodiments, the pResurf diffusion region may be locally clipped to an nDrift diffusion region. The pResurf can extend horizontally to surround the nDrift diffusion region. However, in some embodiments, the pResurf diffusion region overlaps the bulk diffusion region.

The pResurf diffusion region may have a stepped profile, for example, with a doping concentration that increases gradually in the horizontal direction from the drain diffusion region toward the body diffusion region. The depth of the pResurf diffusion region in the semiconductor substrate may decrease in a horizontal direction from the drain diffusion region toward the body diffusion region.

In an example embodiment, a sequence or chain of p-type implants through one mask may be used to create a stair-stepped profile of the pResurf diffusion region. However, in some embodiments, a sequence or chain of p-type implants across multiple masks may be used to create a stepped profile of the pResurf diffusion region. In some embodiments, the mask used to create the stepped profile of the pResurf diffusion region can be the same mask used to create the nDrift diffusion region.

Further, in device fabrication, the nLDMOS device may be electrically isolated vertically from the pEpi/pSubstrate by an n-type buried layer (nBL) (e.g., a lightly doped buried n-type layer). nBL may be confined to a region deeper than the prresurf diffusion region, and may not extend vertically toward the surface of the semiconductor substrate.

In some embodiments, nBL may extend horizontally across the device. In such cases, device fabrication may include additional lateral isolation surrounding the entire device. In some embodiments, additional lateral isolation may be achieved with an annular n-type diffusion region (e.g., an nSinker diffusion region) surrounding the device. The nSinker diffusion region may extend vertically from the surface of the semiconductor substrate where the nSinker diffusion region may be contacted (e.g., metal contacts, silicide, etc.) to nBL. In some embodiments, additional lateral isolation may be achieved using a Deep Trench Isolation (DTI) structure. In some embodiments, additional lateral isolation may be achieved by combining DTI and nSinker diffusion region structures.

Fig. 1 shows a half pitch cross section of a device cell of an example n-type LDMOS device 100 having a p-type stepped profile reduced surface electric field structure 120 and an n-type stepped profile drift structure 110.

For ease of description, the relative orientation or coordinates of features of device 100 may be described herein with reference to, for example, the X-axis and Y-axis shown on the page of fig. 1. The direction parallel to the X axis may be referred to as the horizontal or lateral direction. The direction parallel to the Y-axis may be referred to as the vertical direction or depth. Furthermore, only half of the device cells of device 100 are shown in fig. 1 for visual clarity. A practical LDMOS device may comprise tens or hundreds of device cells, which may be obtained, for example, by mirroring and repeating (e.g., in the X direction) the limited half-cell structure shown in fig. 1.

The device 100 may be fabricated on a BCD technology platform. The device 100 may have a drain structure 130, a gate structure 140, and a source-body structure 150. The device 100 may have three or four terminals (e.g., a drain terminal, a gate terminal, a source terminal, and a body terminal). The source terminal and the body terminal may be connected together. Fig. 1 shows a device 100 having, for example, the following terminals: a drain terminal 131, a gate terminal 141, and a source-body terminal 151 connected together.

In an example embodiment, the device 100 may be built on a p-type substrate/p-epi/n buried layer (nBL) substrate (e.g., substrate 101). Although nBL may be optional, nBL is useful for high voltage switching applications of device 100.

In an example embodiment, the source-body structure 150 (e.g., a Low Voltage (LV) source) may have a body that includes a p-type well (e.g., pWell 154), a p-type body (e.g., pBody153), and a p-type source-drain diffusion region (e.g., pSD 152). In an example embodiment, the source-body structure 150 may include an n-type source-drain diffusion region (e.g., nSD 155). In some embodiments, the body of the source-body structure 150 may include only a p-type well (e.g., pWell 154) and a p-type source diffusion region (e.g., pSD 152).

In an example embodiment, the gate structure 140 of the device 100 may include an n-type polysilicon gate (e.g., npye 143) and a gate oxide 144 deposited or grown on the silicon surface 102 of the substrate 101. Further, spacers 145 (e.g., dielectric structures) may be formed around the entire gate polysilicon. In some implementations, a channel is formed at the silicon surface 102 under the gate structure 140.

In an example embodiment, the source-body structure 150 (e.g., a low voltage LV source) may have a source coupled to an n-type source-drain diffusion region (e.g., nSD 155) for gate region transition through an n-type chain structure (e.g., nLink 154 under the spacer 145). In some embodiments, the source of source structure 150 may be coupled to an n-type source-drain diffusion (e.g., nSD 155) through a lightly doped drain diffusion (e.g., nLDD) for gate region transitions. The nLDD may be implemented using CMOS components of the BCD technology platform.

In an example embodiment, the device 100 may include a reduced surface electric field (resurf) oxide structure (e.g., the reduced surface electric field oxide 160) at the surface 102 between the drain structure 130 and the gate structure 140 to reduce surface electric field effects in the device 100. The resurf oxide 160 may extend at least partially under the gate structure 140. In an example embodiment, a resurf oxide layer (e.g., resurf oxide 160) is disposed on a surface (e.g., surface 102) of the substrate below a gate (e.g., gate structure 140) of the device.

In device 100, drain structure 130 may include an n-type source-drain diffusion region (e.g., nSD 132) in low-resistance contact with drain terminal 131. The drain structure 130 further comprises one or both of a stepped profile reduced surface electric field structure 120 and an n-type stepped profile drift structure 110. In an example embodiment, the reduced surface electric field effect in the device 100 is obtained from one or both of the p-type stepped profile reduced surface electric field structure 120 and the n-type stepped profile drift structure 110 included in the device.

The n-type stepped profile drift structure 110, which may be fabricated by n-dopant implantation through an overlap mask, may include a series of M nDrift diffusion regions (e.g., region 110-1, region 110-2, region 110-i.. and region 110-M, where M is an integer and i is an integer less than M). In example embodiments, M may be two or greater. As shown in fig. 1, the nDrift diffusion regions (e.g., the nDrift diffusion region 110-1, the region 110-2, the region 110-i,. and the region 110-M) may have increasing dopant concentrations in a series of M steps (e.g., step 1, step 2, step i,. and step M) along a lateral or horizontal line from the drain side to the source side of the device. For example, the dopant concentration in region 110-2 at step 2 may be greater than the dopant concentration at step 1 in region 110-1, the dopant concentration in region 110-i at step i may be greater than the dopant concentration in region 110-2 at step 2, the dopant concentration in region 110-M at step M may be greater than the dopant concentration in region 110-i at step i, and so on. The nDrift diffusion region steps (e.g., step 1, step 2, step i, and step M) may have horizontal widths (e.g., X1, X2, Xi,.., XM, respectively).

In example embodiments, the nDrift diffusion regions may extend to different vertical depths in the substrate. For example, Ndrift diffusion region 110-1 at step 1 may extend to a depth d1 below surface 102, region 110-2 at step 2 may extend to a depth d2 below surface 102, region 110-i at step i may extend to a depth di below surface 102, and region 110-M at step M may extend to a depth dm below surface 102. In an example embodiment, the depth of each of the nDrift diffusion regions (e.g., nDrift diffusion region 110-1, region 110-2, region 110-i.. and region 110-M) below surface 102 may decrease (e.g., in steps) in a lateral direction from the drain diffusion region toward the body diffusion region (e.g., d1> d2> di > dm).

The nDrift diffusion regions may overlap and extend horizontally below or underneath each other. For example, region 110-1 (having width X1 and depth d1) may extend horizontally below region 110-2 (having width X2< X1 and depth d2< d1) and region 110-i (having width Xi < X2 and depth di < d2), and so on. Accordingly, a portion of zone 110-2 may be disposed between a portion of zone 110-i and zone 110-1. Also, a portion of zone 110-i may be disposed between a portion of zone 110-M and zone 110-2.

The n-type stepped profile drift structure 110 may be fabricated by n-dopant implantation through one or more masks. In example embodiments, a sequence or chain of n-type implants through partially overlapping masks (e.g., a minimum of two partially overlapping masks) may be used to create a stepped profile with increasing doping concentration along a lateral or horizontal line from the drain side to the source side of the device. The nDrift diffusion regions (e.g., nDrift diffusion region 110-1, region 110-2, region 110-i.. and region 110-M) may have horizontal widths (e.g., X1, X2, Xi.. XM, respectively) that correspond to openings of an overlapping mask (not shown) through which the n-dopant implantation is performed.

The p-type stepped profile reduced surface electric field structure 120, which may be fabricated by p-dopant implantation through one or more masks, may include a series of m pResurf diffusion regions (e.g., pResurf diffusion region 120-1, region 120-2, region 120-j.. and region 120-m, where m is an integer and j is an integer less than m). In an example embodiment, the number M of pResurf diffusion regions in the p-type stepped profile lowering surface electric field structure 120 in the device 100 may be the same as the number M of nDrift diffusion regions in the n-type stepped profile drift structure 110 (i.e., M ═ M). Each of the prresurf diffusion regions may be located at a corresponding depth in the substrate. For example, as shown in FIG. 1, pResurf diffusion region 120-1 at step 1 may be at depth D1 below surface 102, region 120-2 at step 2 may be at depth D2 below surface 102, region 120-j at step i may be at depth Dj below surface 102, and region 120-M at step M may be at depth Dm below surface 102. In example embodiments, a sequence or chain of p-type implants through one or more masks may be used to create a stair-step profile along a lateral line from the drain side to the source side of the device. The depth of each of the prresurf diffusions (e.g., prresurf diffusion 120-1, region 120-2, region 120-j,. and region 120-M) under the n-type stepped profile drift region structure 110 may decrease in a lateral direction from the drain diffusion toward the body diffusion (e.g., D1 at step 1> D2 at step 2> Dj at step i > Dm at step M).

The reduced surface electric field effect in the device 100 due to the n-type stepped profile drift region structure 110 and the p-type stepped profile reduced surface electric field structure 120 may result in a lower Rsp and a higher BVdss.

Although fig. 1 shows an n-type LDMOS, it should be understood that a p-type LDMOS can be obtained by exchanging the n-dopant type and the p-dopant type.

In the example device 100 shown in fig. 1, the n-type stepped profile drift region structure 110 and the p-type stepped profile reduced surface electric field structure 120 may be obtained by implantation using a common set of overlapping masks. Further, the number M of nDrift diffusion regions may be the same as the number M of prresurf diffusion regions. In other words, each nDrift diffusion region (e.g., nDrift region 110-1, region 110-2, region 110-i,. or region 110-M) may have a corresponding or associated pResurf diffusion region (e.g., pResurf region 120-1, region 120-2, region 120-j,. or region 120-M). The corresponding or associated pResurf diffusion region (e.g., pResurf region 120-1, region 120-2, region 120-j,. or region 120-M) can have the same width (e.g., X1, X2, Xi, XM) as the nDrift diffusion region (e.g., Ndrift region 110-1, region 110-2, region 110-i,. and region 110-M).

Fig. 2 illustrates an example device 200 in which the number M of nDrift diffusion regions is different from the number M of prresurf diffusion regions (e.g., M + 1). In the example device 200, for example, the first nDrift diffusion region 110-1 does not have a corresponding pResurf diffusion region (i.e., the pResurf diffusion region 120-1 is not present in the stepped profile reduced surface electric field structure 120 shown in FIG. 2). For example, when implanting through a common set of overlapping masks, a stepped profile reduced surface electric field structure 120 without pResurf diffusion region 120-1 can be obtained when obtaining the n-type stepped profile drift structure 110 and the p-type reduced surface electric field structure 120 by setting the p-type implant dose for pResurf diffusion region 120-1 to zero.

In some embodiments, implantation through a common set of overlapping masks may not be required to obtain the n-type stepped profile drift structure 110 and the p-type stepped profile reduced surface electric field structure 120. The n-type and p-type stepped profile drift structures 110 and 120 may be obtained by implanting through different sets of masks to obtain different numbers or different geometries of Ndrift and pResurf diffusion regions in the n-type and p-type stepped profile reduced surface electric field structures 110 and 120, respectively. This geometric flexibility may provide additional control parameters for designing LDMOS device characteristics (e.g., Rsp and BVdss).

Fig. 3 illustrates an example device 300 in which not only the number M (e.g., M-4) of nDrift diffusion regions that is different from the number M (e.g., M-3) of prresurf diffusion regions is obtained by implantation through different sets of masks, but also the n-type stepped profile drift structure 110 and the p-type stepped profile reduced surface electric field structure 120 are obtained. For example, FIG. 3 shows an example device 300 having four nDrift regions (regions 110-1, 110-2, 110-I, and 110-M) and only three pResurf2 regions (regions 120-2, 120-j, and 120-M). In the example device 300 shown in FIG. 3, only pResurf2 region 120-2 may be implanted through the same mask as its corresponding nDrift region 110-2. pResurf2 region 120-j and region 120-m can be implanted through a different mask than any mask used in the four nDrift regions. Region 120-2 of pResurf2 and the corresponding nDrift region 110-2 implanted through the same mask (opening) may have the same horizontal width (e.g., X2). However, the horizontal widths (e.g., Xrm, Xrj) of pResurf2 region 120-M and region 120-j (implanted through a different mask than any mask used in the four nDrift regions) may differ from the widths (Xm, Xi) of the corresponding nDrift regions 110-M and 110-i.

Fig. 4 shows an example device 400 in which a substrate 101 includes a buried n-type buried layer (nBL) 170. nBL 170 may be an n-type diffusion region below the device and deeper than pResurf1 (e.g., region 120-1 of fig. 1) and pWell 154. In the example device 400, the nBL diffusion region may form a barrier separating the p-type region of the device (e.g., pBody153, pWell 154, and surface electric field-reducing structures 120) from the underlying ppi/pSubstrate 101, such that the body of the device may be biased independently of the ppi/pSubstrate 101.

Fig. 5 shows a cross-sectional view of impact ionization lines and equipotential lines of a test nLDMOS device obtained by a Technical Computer Aided Design (TCAD) simulation of the test nLDMOS device. The test nLDMOS device has, for example, two pairs of Ndrift and pResurf diffusion regions (i.e., Ndrift1/pResurf1 and Ndrift2/pResurf2 of fig. 1). Different configurations of implant doses for the nddrift 1 region, the nDrift2 region, the Presurf1 region, and the Presurf2 region are contemplated.

Fig. 6 is a graph showing Rsp and BVdss values obtained for various sets of doping concentration values (i.e., dopant concentration group 610) of implant doses for the pResurf1, pResurf2, nDRift1, and nDRift2 regions as test nLDMOS devices. Fig. 6 also shows the Rsp and BVdss values obtained for the conventional device (labeled WFR 620). As can be seen from the results shown in fig. 6, the test nLDMOS device (labeled WFR 630) showed Rsp values reduced by about 21% and had higher BVdss values (e.g., increased by about 1V) compared to the conventional device POR WFR 620. The best results for the target WFR 630 correspond, for example, to D11 for the pResurf2, nDRift1, and nDRift2 regions; d32; d33 and D11; d42; dopant concentration group 610 of D43.

Fig. 7-15 show schematic views of a substrate 101 as it is processed through various steps of an example fabrication process to fabricate an example nLDMOS device (e.g., device 100 of fig. 1).

Fig. 7 shows a starting p-type substrate 101 that may have a sacrificial oxide layer 701 grown over the substrate after pEpi growth, pad oxide growth, and STI formation.

Figure 8 shows a reduced surface field oxide layer 801 grown on a substrate 101. Reducing the growth of the surface field oxide layer may involve pad nitride layer deposition, reducing the surface field oxide lithography pattern mask, nitride etching, resist stripping, reducing the surface field oxide growth, and nitride stripping.

The n-type drift structure 110 and the p-type surface-electric-field-reducing structure 120 may be formed in the substrate 101 by ion implantation through a sequence of one or more resist masks (not shown). In an example embodiment, a sequence or chain of n-type implants through partially overlapping masks may be used to form the n-type drift structure 110. A sequence or chain of p-type implants through the same partially overlapping masks may be used to form the p-type surface electric field reducing structure 120. For example, a first resist mask may be placed on the substrate 101, and n-type ions may be implanted through the mask to form a first Ndrift region of the n-type drift structure 110, and p-type ions may be implanted through the same mask to form a first pResurf region of the p-type reduced surface electric field structure 120. Next, a second resist mask (overlapping the first mask) may be placed on the substrate 101. N-type ions may be implanted through a second resist mask to form a second Ndrift region of the N-type drift structure 110 and p-type ions may be implanted through the same mask to form a second pResurf region of the p-type surface electric field reducing structure 120. Further, the process of implanting n-type and p-type ions may be repeated through additional overlapping resist masks placed on the substrate to form additional Ndrift and pResurf regions. N-type ions may be implanted through each of the resist masks placed on the substrate 101 before or after the implantation of p-type ions.

Fig. 9 shows an n-type drift structure 110 and a p-type reduced surface electric field structure 120 formed in a substrate 101. N-type drift structure 110 may include a plurality of Ndrift diffusion regions (e.g., Ndrift1, Ndrift2, Ndrift, …, and NdriftN). The P-type surface field reducing structure 120 may include a plurality of surface field reducing diffusion regions (e.g., pResurf1, pResurf2, pResurf … and pResurf N). The formation of these structures may involve: nDrift1 mask, nDrift1 implant chain, resurf1 implant chain, and resist strip; …, respectively; nDriftN mask, nDriftN implant chain, pResurfN implant chain, resist strip, and the like.

Fig. 10 shows a p-type well 1001 formed in the substrate 101. The formation of the p-well may involve: PWell mask, PWell implant and resist strip.

Fig. 11 shows the formation of a gate oxide 1101 on the top surface of the substrate 101 (after sacrificial oxide layer stripping).

Fig. 12 shows the substrate 101 after forming a precursor structure 1201 for a gate (e.g., npy), a structure 1202 for a p body, and a structure 1203 for an nLink in the substrate. The formation of these structures may involve: polysilicon deposition, self-aligned pBody masking, polysilicon etching, nLink implants, pBody implants, and resist stripping.

Fig. 13 shows the substrate 101 after a gate structure 1301 is formed in the substrate 101. The formation of the structure may involve: polysilicon masking, polysilicon etching, and resist stripping.

Fig. 14 shows the substrate 101 after forming source and drain structures (e.g., spacers 1401, psds 12P, and nSD 13N) in the substrate 101. The formation of these structures may involve: spacer formation, nSD mask, nSD implant, resist strip, pSD mask, pSD implant, and resist strip.

Fig. 15 shows the substrate 101 after formation of device terminals (e.g., source terminal 1501, gate terminal 1502, and drain terminal 1503) by a back-end metallization process that includes a silicide layer 1504. Back-end processing may involve: silicide formation, interlayer dielectric (ILD) layer formation, ILD formation, and conductive material or metal contact formation.

Fig. 16 illustrates an example method 1600 for fabricating a MOSFET device (e.g., an n-type LDMOS) having a reduced on-state resistance (Rsp) at a given breakdown voltage (BVdss).

The method 1600 includes forming source and drain regions on a surface of a semiconductor substrate (1610); forming a gate region (1620); forming a body diffusion region (1630); forming a metal structure 1640; and forming a drift region (1650). The semiconductor substrate may, for example, be a p-type substrate (e.g., pEpi/pSubstrate) having a p-type doped silicon epitaxial layer.

Forming the source and drain regions 1610 may include forming a dielectric layer (e.g., a gate oxide layer less than about 20nm) at a surface of a semiconductor substrate and forming a reduced surface field oxide layer (e.g., a dielectric layer greater than about 30nm) at the semiconductor surface to separate the source and drain regions.

Forming the gate region 1620 may include forming a gate polygon (e.g., a heavily doped n-type polysilicon layer) to overlap a portion, but not all, of the source region and a portion of the reduced surface field oxide layer. Forming the gate region 1620 may further include forming spacers (i.e., dielectric structures) around the gate polygons.

Forming the source and drain regions 1610 may further include: a first heavily doped n-type diffusion (commonly referred to as nLink or nLDD) is formed below the spacer and the surface of the source region, a second heavily doped n-type diffusion (source diffusion) is formed at the surface of the source region and along the spacer, and a heavily doped p-type diffusion (body tap) is formed at the surface of the source region and along the source diffusion.

In some example embodiments, the body tap diffusion may contact the source diffusion. In some example embodiments, the body tap may be separated from the source diffusion by an additional isolation dielectric (e.g., field oxide, LOCOS, STI, etc.). The additional isolation dielectric may divide the source region into two parts: a source region and a body region.

Forming the source and drain regions 1610 may further include forming heavily doped n-type diffusions (drain diffusions) at the surface of the drain AA.

Forming the body diffusion region 1630 may include forming a lightly doped p-type diffusion (body diffusion) by using a p-type ion implant sequence through a single mask (e.g., CMOS pWell mask) or through multiple masks (e.g., CMOS pWell mask + self-aligned pBody mask). The body diffusion region may extend vertically from the surface of the semiconductor substrate deeper than the nLink/nLDD, source diffusion and body tap. Further, the body diffusion may extend horizontally to surround the body tap, the source diffusion, the nLink/nLDD, and the portion of the source region covered by the gate region. The portion of the body diffusion region that overlaps the gate region is commonly referred to as the channel and its length (Lg) is commonly referred to as the gate length. In example embodiments, the nLink/nLDD may provide electrical continuity between the channel and source diffusions.

Forming the metal structure 1640 may include forming the metal structure at a surface of both the semiconductor substrate and the gate region (e.g., over the gate polygon, the drain diffusion, the source diffusion, and the body tap). The metal structure may include a silicide layer and a metal or conductive contact. The metal structure defines the terminals (e.g., gate, drain, source, and body terminals) of the device. In example embodiments, the source terminal and the body terminal may be connected into a single terminal (i.e., the source terminal) in the case where the source diffusion and the body diffusion are in contact in the device.

Forming the drift region 1650 may include forming an n-type drift structure having a stepped dopant concentration profile, wherein the dopant concentration increases in a lateral direction from a drain region to a source region of the device (1652).

Forming the n-type drift structure 1652 can include implanting two or more lightly doped drift diffusion regions (nDrift diffusion regions) through a surface of the semiconductor substrate. In an example embodiment, implanting two or more lightly doped drift diffusion regions through a surface of a semiconductor substrate includes implanting n-type ions through a plurality of overlapping masks. In an example embodiment, a MOSFET device may have an n-type drift structure with two implanted overlapping drift diffusion regions.

The nDrift diffusion region may extend vertically from the surface of the semiconductor substrate to reach deeper than the drain diffusion and the reduced surface field oxide. In addition, the nDrift diffusion region may extend horizontally to surround at least a portion of the drain diffusion, the reduced surface field oxide, and the source region.

In some example embodiments, the nDrift diffusion region and the body diffusion region may be in contact. In some example embodiments, the nDrift diffusion region and the body diffusion region may be separated, and in some example embodiments, the nDrift diffusion region and the body diffusion region may overlap.

In example embodiments, the nDrift diffusion region may have a dopant concentration profile in which the dopant concentration in the nDrift diffusion region is stepped in steps horizontally from the edge of the drain diffusion region to the junction with the body diffusion region. The stepped dopant concentration profile may be formed by a sequence of n-type ion implants through a plurality of overlapping masks. In an example embodiment, a minimum of two partially overlapping masks may be used to form a stepped dopant concentration profile (e.g., a dopant concentration profile with one intermediate dopant concentration step over two nDrift diffusion regions).

Forming the drift region 1650 may further include forming a p-type resurf structure having a stepped dopant concentration profile, wherein the dopant concentration increases in a lateral direction from a drain region to a source region of the device (1654).

The p-type resurf structure may include one or more pResurf diffusion regions. The one or more pResurf diffusion regions may be confined to a region deeper than the nDrift diffusion region and may not extend vertically to the surface of the semiconductor substrate. In some embodiments, the pResurf diffusion region can be locally tailored to nDrift diffusion.

Further, the pResurf diffusion region can extend horizontally to surround the nDrift diffusion region. In some embodiments, the pResurf diffusion region can overlap the bulk diffusion region.

In an example embodiment, the pResurf diffusion region may have a dopant concentration profile in which the dopant concentration diffuses in a horizontal direction from below the drain diffusion toward the body to increase in steps. In some embodiments, the depth of the pResurf diffusion region may decrease in steps in the horizontal direction from below the drain diffusion toward the body diffusion.

In some example embodiments, the stepped dopant concentration profile of the pResurf diffusion region may be formed by a sequence of p-type ion implants through a single mask or through multiple masks.

In some example embodiments, the stepped dopant concentration profile of the pResurf diffusion region may be formed by p-type ion implant sequences through the same overlapping mask of n-type ion implant sequences for the stepped dopant concentration profile of the nDrift diffusion region.

In an example embodiment, the number of overlapping masks may be two. Implantation through two overlapping masks can produce a stepped dopant concentration profile for an nDrift diffusion region with two diffusion regions (the dopant concentration between the two diffusion regions has a step).

The method 1600 may further include forming an isolation structure to electrically isolate the device from the substrate (1660). In an example embodiment, forming the isolation structure 1660 may include forming a lightly doped buried n-type diffusion (nBL). For example, nBL may electrically isolate the nLDMOS device vertically from the pEpi/pSubstrate.

nBL may extend horizontally to encompass the entire device. In an example embodiment, nBL is confined to a region deeper than the prresurf diffusion region and does not extend vertically to the surface of the semiconductor substrate. In some example embodiments, the pResurf diffusion region may be locally tailored to nBL.

Further, forming the isolation structure 1660 may include forming additional lateral isolation surrounding the entire device. Forming additional lateral isolation may include forming an n-type diffusion region (nSinker). nSinker can be an annular diffusion region that surrounds the device and extends vertically from the substrate surface to nBL. The nSinker can be contacted at the surface of the substrate by a metal structure (e.g., a metal contact, a silicide layer, etc.).

In some example embodiments, forming additional lateral isolation may include forming a deep trench structure (DTI) or combining DTI with nSinker for lateral isolation.

It will also be understood that when an element such as a transistor or resistor is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it can be directly on, connected to, or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers present. Elements shown as directly on, directly connected to, or directly coupled to the element may be referred to in this manner, although the terms directly on …, directly connected to …, or directly coupled to … may not be used throughout the detailed description. The claims of this application, if included, may be amended to recite exemplary relationships that are described in the specification or illustrated in the drawings.

As used in this specification, the singular forms can include the plural forms unless the context clearly dictates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above …, above …, above …, below …, below …, below …, below …, etc.) are intended to encompass different orientations of the device in use or operation. In some embodiments, relative terms above … and below … may include vertically above … and vertically below …, respectively. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

Implementations of the various techniques described herein may be implemented (e.g., included) in digital electronic circuitry, in computer hardware, firmware, software, or in combinations of them. Portions of the methods may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Embodiments may be implemented in a computing system that includes an industrial motor driver, a solar inverter, a ballast, a general half-bridge topology, an auxiliary and/or traction motor inverter driver, a switched mode power supply, an in-vehicle charger, an Uninterruptible Power Supply (UPS), a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a client computer having a Web browser or a graphical user interface through which a user can interact with an embodiment), or any combination of such back-end, middleware, or front-end components. The components may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a Local Area Network (LAN) and a Wide Area Network (WAN), such as the Internet.

Some embodiments may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and the like.

While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It is to be understood that such modifications and variations are presented by way of example only, and not limitation, and that various changes in form and details may be made. Any portion of the devices and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or subcombinations of the functions, components and/or features of the different embodiments described.