阅读说明：本技术 碳化硅沟槽mosfet器件及制备方法 (Silicon carbide groove MOSFET device and preparation method thereof ) 是由 张金平 王鹏蛟 吴庆霖 刘竞秀 张波 于 2020-12-29 设计创作，主要内容包括：本发明属于功率半导体器件技术领域,具体涉及一种碳化硅沟槽MOSFET器件及其制备方法。本发明相对于传统的沟槽型碳化硅MOSFET,去掉了其N型碳化硅衬底,在器件源区一侧引入了第一N型碳化硅缓冲层,在器件漏区一侧引入了第二N型碳化硅缓冲层,并且在器件漏区一侧引入了P型多晶硅/N型碳化硅异质结以及不相连的P型区域。所述器件结构可以使沟槽型碳化硅MOSFET在获得大的正反向对称耐压的同时,具有较小的正向导通压降。此外,为了进一步解决该器件栅氧化层可靠性问题及栅漏电容较大问题,给出了几种相应的衍生结构。(The invention belongs to the technical field of power semiconductor devices, and particularly relates to a silicon carbide trench MOSFET device and a preparation method thereof. Compared with the traditional groove type silicon carbide MOSFET, the groove type silicon carbide MOSFET is provided with the N type silicon carbide substrate removed, the first N type silicon carbide buffer layer is introduced at one side of the source region of the device, the second N type silicon carbide buffer layer is introduced at one side of the drain region of the device, and the P type polycrystalline silicon/N type silicon carbide heterojunction and the unconnected P type region are introduced at one side of the drain region of the device. The device structure can enable the groove type silicon carbide MOSFET to obtain large forward and reverse symmetrical voltage resistance and simultaneously have small forward conduction voltage drop. In addition, in order to further solve the problems of reliability of the gate oxide layer of the device and large gate leakage capacitance, a plurality of corresponding derivative structures are provided.)

1. A silicon carbide trench MOSFET device comprises a half-cell structure which comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,

a grid electrode (9) and a first N-type silicon carbide buffer layer (11) are arranged above the N-type silicon carbide epitaxial layer (3), a first P-type base region (4) is arranged above the first N-type silicon carbide buffer layer (11), a first P-type source region (5) and a first N-type source region (7) are arranged above the first P-type base region (4), the first P-type source region (5) and the first N-type source region (7) are connected in a left-right mode, and source metal (6) is respectively connected with the first P-type source region (5) and part of the first N-type source region (7) in an up-down mode;

a gate dielectric layer (10) is arranged between the gate (9) and the N-type silicon carbide epitaxial layer (3), between the gate (9) and the first N-type source region (7), between the gate (9) and the first P-type base region (4) and between the gate (9) and the first N-type silicon carbide buffer layer (11);

the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with unconnected P-type regions (12); ohmic contact is formed between the lower part of the P-type region (12) and the back drain metal (1); a P-type polycrystalline silicon region (13) is arranged between the adjacent P-type regions (12), the upper surface of the P-type polycrystalline silicon region (13) is connected with the second N-type silicon carbide buffer layer (21), and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal (1).

2. A silicon carbide trench MOSFET device comprises a half-cell structure which comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,

a grid electrode (9) and a first N-type silicon carbide buffer layer (11) are arranged above the N-type silicon carbide epitaxial layer (3), a first P-type base region (4) is arranged above the first N-type silicon carbide buffer layer (11), a first P-type source region (5) and a first N-type source region (7) are arranged above the first P-type base region (4), the first P-type source region (5) and the first N-type source region (7) are connected in a left-right mode, and source metal (6) is respectively connected with the first P-type source region (5) and part of the first N-type source region (7) in an up-down mode;

a gate dielectric layer (10) is arranged between the gate (9) and the N-type silicon carbide epitaxial layer (3), between the gate (9) and the first N-type source region (7), between the gate (9) and the first P-type base region (4) and between the gate (9) and the first N-type silicon carbide buffer layer (11);

the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with unconnected P-type regions (12); no contact is formed between the lower part of the P-type region (12) and the back drain metal (1), and the second N-type silicon carbide buffer layer (21) is completely floated; the P-type polysilicon region (13) is located below the P-type region (12) and has a smaller width than the P-type region (12).

3. A silicon carbide trench MOSFET device comprises a half-cell structure which comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,

a grid electrode (9) and a first N-type silicon carbide buffer layer (11) are arranged above the N-type silicon carbide epitaxial layer (3), a first P-type base region (4) is arranged above the first N-type silicon carbide buffer layer (11), a first P-type source region (5) and a first N-type source region (7) are arranged above the first P-type base region (4), the first P-type source region (5) and the first N-type source region (7) are connected in a left-right mode, and source metal (6) is respectively connected with the first P-type source region (5) and part of the first N-type source region (7) in an up-down mode;

a gate dielectric layer (10) is arranged between the gate (9) and the N-type silicon carbide epitaxial layer (3), between the gate (9) and the first N-type source region (7), between the gate (9) and the first P-type base region (4) and between the gate (9) and the first N-type silicon carbide buffer layer (11);

the method is characterized in that: the P-type polycrystalline silicon regions (13) are not connected in the second N-type silicon carbide buffer layer (21); the P-type regions (12) are also unconnected in the second N-type silicon carbide buffer layer (21); the upper surface of the P-type polycrystalline silicon region (13) is contacted with the P-type region (12), and the lower surface is contacted with the back drain metal (1).

4. A silicon carbide MOSFET as claimed in claim 1 or claim 2 or claim 3 wherein: and a P-type buried layer (14) is arranged below the gate dielectric layer (10).

5. A silicon carbide MOSFET as claimed in claim 1 or claim 2 or claim 3 wherein: and a shielding grid (15) and a shielding grid dielectric layer (16) on the right side of the shielding grid dielectric layer (15) are arranged below the grid dielectric layer (10), and a P-type buried layer (14) is arranged below the shielding grid dielectric layer (16).

6. A silicon carbide MOSFET as claimed in any one of claims 1 to 5 wherein: the half-cell structure on the front side comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,

a first N-type silicon carbide buffer layer (11) is arranged above the N-type silicon carbide epitaxial layer (3), a gate dielectric layer (10) is arranged above the first N-type silicon carbide buffer layer (11), a gate (9) is arranged inside the gate dielectric layer (10), a first P-type base region (4) is arranged on the right side of the gate dielectric layer (10), the left side of the first P-type base region (4) is in contact with the gate dielectric layer (10), the upper left surface is in contact with a first N-type source region (7), the upper right surface is in contact with a first P-type source region (5), the lower part is in contact with the first N-type silicon carbide buffer layer (11), and source metal (6) is arranged above the first P-type source region (5); the source metal (6) covers the upper surface and the right surface of the first N-type source region (7).

7. A silicon carbide MOSFET as claimed in any one of claims 1 to 5 wherein: the cell structure on the front side comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,

a first N-type silicon carbide buffer layer (11) is arranged above the N-type silicon carbide epitaxial layer (3), a grid electrode (9) is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer (11), a grid dielectric layer (10) is arranged above the first N-type silicon carbide buffer layer (11), a second P-type source region (51) is arranged at the left portion of the upper portion of the first N-type silicon carbide buffer layer (11), a second N-type source region (71) and a second P-type base region (41) are arranged on the right side of the second P-type source region (51), the second N-type source region (71) and the second P-type base region (41) are connected up and down, a third P-type source region (52) is arranged on the right side of the grid electrode (9), the third P-type source region (52) extends to the middle portion of the grid electrode (9) leftwards, a third N-type source region (72) and a third P-type base region (42) are arranged on the right side of the third P-type source region (52), the third N, the gate (9) and the second P-type base region (41), the gate (9) and the first N-type silicon carbide buffer layer (11), and the gate (9) and the third P-type source region (52) are isolated by a gate dielectric layer (10).

8. A silicon carbide MOSFET as claimed in claim 1 or claim 2 or claim 3 wherein: all silicon carbide materials are replaced by material A, A is selected from one of gallium nitride, gallium oxide, boron nitride and silicon materials, polysilicon materials are replaced by material B, and the forbidden bandwidth of the material B is smaller than that of the material A.

9. A method of fabricating a silicon carbide trench MOSFET device according to claim 1, comprising the steps of:

step 1: preparing a second N-type silicon carbide buffer layer (21) on the surface of the N-type silicon carbide substrate (2) by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer (3) on the surface of the second N-type silicon carbide buffer layer (21) by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer (3) by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer (10) on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a grid electrode (9) in the grid dielectric layer (10) by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer (11), a P-type silicon carbide base region (4), an N-type silicon carbide source region (7) and a P-type silicon carbide source region (5) in the N-type silicon carbide epitaxial layer (3) by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate (2) by adopting a grinding process;

and 8: preparing P-type regions (12) distributed at intervals in the second N-type silicon carbide buffer layer (21) by adopting photoetching and ion implantation processes;

and step 9: preparing a P-type polycrystalline silicon region (13) on the back surface of the second N-type silicon carbide buffer layer (21) by adopting a deposition and etching process;

step 10: preparing source metal (6) by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain electrode metal (1) by adopting an evaporation or sputtering process and an etching process.

Technical Field

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a silicon carbide trench MOSFET device and a preparation method thereof.

Background

The inverter is a device for converting direct current into alternating current, and has a wide application range, such as a photovoltaic inverter, an uninterruptible power supply, a rail transit and trolley bus, a frequency converter and the like. The multi-level inverter has the excellent characteristics of low loss, low noise, output waveform close to a sine wave and the like, so that the application scene of the multi-level inverter is wider. The matrix inverter is a novel power converter, and can directly realize alternating current-alternating current conversion. Compared with the traditional alternating current-direct current-alternating current frequency conversion mode, the matrix inverter does not need a direct current capacitor for intermediate energy storage, the reliability of the whole system is improved, and the cost is reduced.

Bidirectional switches with forward and reverse conduction capability and blocking capability are core devices of multilevel inverters and matrix inverters. A reverse-blocking type insulated gate bipolar transistor (RB-IGBT) is a novel IGBT with bidirectional blocking capability, and two RB-IGBTs are reversely connected in parallel to form a bidirectional switch. Compared with the conventional bidirectional switch which is generally composed of two ordinary IGBTs and two fast recovery diodes, the bidirectional switch composed of RB-IGBTs has fewer elements and lower conduction loss. The conventional RB-IGBT generally adopts a non-punch-through (NPT) structure, which has a long IGBT drift region, and thus has a severe current tail and a large turn-off loss. How to reduce the power loss of the bidirectional switch is one of the current research hotspots.

Silicon carbide, which is one of typical representatives of the third-generation semiconductor materials, has excellent characteristics such as a large forbidden band width, a high electron saturation drift velocity, and a high thermal conductivity. Compared with the IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. Therefore, if the silicon carbide MOSFET can realize bidirectional blocking, its performance is much superior to that of the RB-IGBT. Fig. 1 shows a conventional trench-type silicon carbide MOSFET, which has a large forward blocking capability and a low on-state voltage drop. However, this structure does not have reverse blocking capability.

Disclosure of Invention

The invention aims to solve the problems of how to enable a trench type silicon carbide MOSFET to have large forward and reverse symmetrical voltage resistance and how to reduce the conduction voltage drop of the MOSFET. Conventional trench silicon carbide MOSFETs, as shown in fig. 1, do not have reverse blocking capability. The invention provides three technical schemes. Technical scheme 1 as shown in fig. 2, in this technical scheme, a silicon carbide substrate in a conventional trench-type silicon carbide MOSFET structure is removed, a first N-type silicon carbide buffer layer is introduced on one side of a source region, a second N-type silicon carbide buffer layer is introduced on one side of a drain region, P-type regions which are not adjacently distributed are introduced into the second N-type silicon carbide buffer layer, and P-type polysilicon regions are introduced to form a P-type polysilicon/N-type silicon carbide heterojunction, wherein the P-type regions and the P-type polysilicon regions are directly connected to a drain metal. The structure of the device enables the groove type silicon carbide MOSFET to obtain large forward and reverse symmetrical voltage resistance and lower forward conduction voltage drop. Technical solution 2 as shown in fig. 3, in the technical solution 2, a silicon carbide substrate in a conventional trench type silicon carbide MOSFET structure is also removed, a first N-type silicon carbide buffer layer is introduced on one side of a source region, and a second N-type silicon carbide buffer layer is introduced on one side of a drain region, where the difference from the technical solution 1 is a back structure of a device, in the technical solution, a P-type region is not directly connected to a drain metal but floats in the second N-type silicon carbide buffer layer, and meanwhile, compared with the technical solution 1, the position of the P-type polysilicon region is changed to a certain extent, that is, the position of the P-type polysilicon region corresponds to the P-type region, but the width is slightly smaller than the P-type region, so that leakage current of the device when the device is blocked reversely is further reduced, and a lower forward conduction voltage drop is achieved. Technical solution 3 as shown in fig. 4, in the technical solution 3, a silicon carbide substrate in a conventional trench type silicon carbide MOSFET structure is also removed, a first N-type silicon carbide buffer layer is introduced at one side of a source region, and a second N-type silicon carbide buffer layer is introduced at one side of a drain region, which is different from the two previous technical solutions in that a P-type polysilicon region in the technical solution is formed by a deposition process after an etching trench is formed in the second N-type silicon carbide buffer layer by etching. The invention also provides a preparation method of the device in the three technical schemes, and the preparation method is simple and controllable in manufacturing process and strong in compatibility with the existing process.

The first technical scheme is as follows:

a silicon carbide reverse resistance type groove MOSFET device comprises a half cell structure which comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

Preferably, a P-type buried layer 14 is provided below the gate dielectric layer 10, as shown in fig. 5.

Preferably, a shielding gate 15 and a shielding gate dielectric layer 16 on the right side thereof are disposed below the gate dielectric layer 10, and a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, as shown in fig. 6.

Preferably, all silicon carbide materials are replaced by material A, A is selected from gallium nitride, gallium oxide, boron nitride and silicon materials, and polysilicon material is replaced by material B, and the forbidden bandwidth of material B is smaller than that of material A.

Preferably, the silicon carbide MOSFET has a front half-cell structure comprising a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 10 is arranged above the first N-type silicon carbide buffer layer 11, a gate 9 is arranged inside the gate dielectric layer 10, a first P-type base region 4 is arranged on the right side of the gate dielectric layer 10, the left side of the first P-type base region 4 is in contact with the gate dielectric layer 10, the left upper surface of the first P-type base region is in contact with a first N-type source region 7, the right upper surface of the first P-type base region is in contact with a first P-type source region 5, the lower part of the first P-type base region is in contact with the first N-type silicon carbide buffer; the source metal 6 covers the upper and right surfaces of the first N-type source region 7,

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

Preferably, as shown in fig. 12, the front cell structure of the silicon carbide MOSFET includes a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a grid electrode 9 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 11, a grid medium layer 10 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 11, a second P-type source region 51 is arranged on the right side of the second P-type source region 51, a second N-type source region 71 and a second P-type base region 41 are arranged on the right side of the second N-type silicon carbide buffer layer 11, the second N-type source region 71 and the second P-type base region 41 are connected up and down, a third P-type source region 52 is arranged on the right side of the grid electrode 9, the third P-type source region 52 extends to the middle of the grid electrode 9 leftwards, a third N-type source region 72 and a third P-type base region 42 are arranged on the right side of the third P-type source region 52, the third N-type base region 72 and the third P-type base region 42 are connected up and down, the grid electrode 9 and the second N-type source;

the invention also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer 11, a P-type silicon carbide base region 4, an N-type silicon carbide source region 7 and a P-type silicon carbide source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and 8: preparing P-type regions 12 distributed at intervals in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

and step 9: preparing a P-type polycrystalline silicon region 13 on the back of the second N-type silicon carbide buffer layer 21 by adopting a deposition and etching process;

step 10: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

The second technical scheme 2:

a silicon carbide reverse resistance type groove MOSFET device comprises a half cell structure which comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; no contact is formed between the lower part of the P-type region 12 and the back drain metal 1, and the P-type region completely floats in the second N-type silicon carbide buffer layer 21; the P-type polysilicon region 13 is located below the P-type region 12 and has a smaller width than the P-type region 12.

Preferably, a P-type buried layer 14 is provided below the gate dielectric layer 10, as shown in fig. 5.

Preferably, a shielding gate 15 and a shielding gate dielectric layer 16 on the right side thereof are disposed below the gate dielectric layer 10, and a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, as shown in fig. 6.

Preferably, all silicon carbide materials are replaced by material A, A is selected from gallium nitride, gallium oxide, boron nitride and silicon materials, and polysilicon material is replaced by material B, and the forbidden bandwidth of material B is smaller than that of material A.

Preferably, the silicon carbide MOSFET has a front half-cell structure comprising a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 10 is arranged above the first N-type silicon carbide buffer layer 11, a gate 9 is arranged inside the gate dielectric layer 10, a first P-type base region 4 is arranged on the right side of the gate dielectric layer 10, the left side of the first P-type base region 4 is in contact with the gate dielectric layer 10, the left upper surface of the first P-type base region is in contact with a first N-type source region 7, the right upper surface of the first P-type base region is in contact with a first P-type source region 5, the lower part of the first P-type base region is in contact with the first N-type silicon carbide buffer; the source metal 6 covers the upper and right surfaces of the first N-type source region 7.

Preferably, as shown in fig. 12, the front cell structure of the silicon carbide MOSFET includes a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a grid electrode 9 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 11, a grid medium layer 10 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 11, a second P-type source region 51 is arranged on the right side of the second P-type source region 51, a second N-type source region 71 and a second P-type base region 41 are arranged on the right side of the second N-type silicon carbide buffer layer 11, the second N-type source region 71 and the second P-type base region 41 are connected up and down, a third P-type source region 52 is arranged on the right side of the grid electrode 9, the third P-type source region 52 extends to the middle of the grid electrode 9 leftwards, a third N-type source region 72 and a third P-type base region 42 are arranged on the right side of the third P-type source region 52, the third N-type base region 72 and the third P-type base region 42 are connected up and down, the grid electrode 9 and the second N-type source;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

The invention also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer 11, a P-type silicon carbide base region 4, an N-type silicon carbide source region 7 and a P-type silicon carbide source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and 8: preparing P-type regions 12 distributed at intervals in the second N-type silicon carbide buffer layer 21 by photoetching and ion implantation processes;

and step 9: preparing a P-type polycrystalline silicon region 13 on the back of the second N-type silicon carbide buffer layer 21 by adopting a deposition and etching process;

step 10: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

Thus, the trench type silicon carbide reverse resistance MOSFET device in the technical scheme is manufactured.

Three technical schemes 3:

a silicon carbide reverse resistance type groove MOSFET device comprises a half cell structure which comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the P-type polycrystalline silicon regions 13 are not connected in the second N-type silicon carbide buffer layer 21; the P-type regions 12 are also unconnected in the second N-type silicon carbide buffer layer 21; the upper surface of the P-type polysilicon region 13 is in contact with the P-type region 12, and the lower surface is in contact with the back drain metal 1.

Preferably, a P-type buried layer 14 is provided below the gate dielectric layer 10, as shown in fig. 5.

Preferably, a shielding gate 15 and a shielding gate dielectric layer 16 on the right side thereof are disposed below the gate dielectric layer 10, and a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, as shown in fig. 6.

Preferably, all silicon carbide materials are replaced by material A, A is selected from gallium nitride, gallium oxide, boron nitride and silicon materials, and polysilicon material is replaced by material B, and the forbidden bandwidth of material B is smaller than that of material A.

Preferably, the silicon carbide MOSFET has a front half-cell structure comprising a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 10 is arranged above the first N-type silicon carbide buffer layer 11, a gate 9 is arranged inside the gate dielectric layer 10, a first P-type base region 4 is arranged on the right side of the gate dielectric layer 10, the left side of the first P-type base region 4 is in contact with the gate dielectric layer 10, the left upper surface of the first P-type base region is in contact with a first N-type source region 7, the right upper surface of the first P-type base region is in contact with a first P-type source region 5, the lower part of the first P-type base region is in contact with the first N-type silicon carbide buffer; the source metal 6 covers the upper and right surfaces of the first N-type source region 7,

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

Preferably, as shown in fig. 12, the front cell structure of the silicon carbide MOSFET includes a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a grid electrode 9 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 11, a grid medium layer 10 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 11, a second P-type source region 51 is arranged on the right side of the second P-type source region 51, a second N-type source region 71 and a second P-type base region 41 are arranged on the right side of the second N-type silicon carbide buffer layer 11, the second N-type source region 71 and the second P-type base region 41 are connected up and down, a third P-type source region 52 is arranged on the right side of the grid electrode 9, the third P-type source region 52 extends to the middle of the grid electrode 9 leftwards, a third N-type source region 72 and a third P-type base region 42 are arranged on the right side of the third P-type source region 52, the third N-type base region 72 and the third P-type base region 42 are connected up and down, the grid electrode 9 and the second N-type source;

the invention also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer 11, a P-type silicon carbide base region 4, an N-type silicon carbide source region 7 and a P-type silicon carbide source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and 8: preparing P-type regions 12 distributed at intervals in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

and step 9: preparing etching grooves distributed at intervals by adopting an etching process;

step 10: filling the etching groove with a P-type polycrystalline silicon region 13 by adopting a deposition process;

step 11: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 12: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

Thus, the trench type silicon carbide reverse resistance MOSFET device in the technical scheme is manufactured.

Further, for simplifying the description, the device structure and the manufacturing method of the above three technical solutions are illustrated by taking an N-channel MOSFET as an example, but the present invention is also applicable to the manufacturing of a P-channel MOSFET device.

The working principle of the invention is as follows:

a conventional trench-type silicon carbide MOSFET is shown in fig. 1. During forward operation, a positive voltage is applied to the drain electrode, a negative voltage is applied to the source electrode, the device is started by applying a proper forward bias voltage to the grid electrode, when the device needs to be turned off, the forward bias voltage of the grid electrode is removed, a reverse PN junction formed by the P-type base region and the N-type drift region bears a withstand voltage, the depletion region expands towards the direction of the substrate, and the N-type substrate has high doping concentration, so that the further expansion of the depletion region is prevented, the punch-through of the device is prevented, and the forward withstand voltage is ensured. However, when the MOSFET is turned off in the reverse direction, the conventional trench silicon carbide MOSFET cannot form a voltage-withstanding region, and thus does not have a reverse voltage-withstanding capability.

The invention has three technical schemes, and the basic principles of the three technical schemes are similar, so that only the working principle of the technical scheme 1 is explained. In the first scheme, a silicon carbide substrate in a traditional groove type silicon carbide MOSFET structure is removed, a first N type silicon carbide buffer layer is introduced at one side of a source region, a second N type silicon carbide buffer layer is introduced at one side of a drain region, P type regions which are not distributed adjacently are introduced in the second N type silicon carbide buffer layer, and meanwhile, a P type polycrystalline silicon region is introduced at the back of the second N type silicon carbide buffer layer so as to form a P type polycrystalline silicon/N type silicon carbide heterojunction. It should be noted that, in the present invention, the concentration of the first N-type silicon carbide buffer layer and the second N-type silicon carbide buffer layer is higher than that of the drift region, but lower than that of the conventional trench-type silicon carbideSubstrate concentration of MOSFET in the range of 10¹⁵cm^-3To 10¹⁶cm^-3And the order of magnitude ensures that the device can obtain larger symmetrical voltage resistance.

When the MOSFET device structure is normally conducted, because the P-type polycrystalline silicon/N-type silicon carbide heterojunction barrier is lower than the PN junction barrier, current can flow through a conducting channel of the P-type polycrystalline silicon/N-type silicon carbide heterojunction barrier at first, the device is conductive for many minutes, and because the P-type polycrystalline silicon/N-type silicon carbide heterojunction barrier is lower than the barrier of ohmic contact, compared with the traditional groove-type silicon carbide MOSFET, the MOSFET device structure can obtain lower MOSFET drain contact resistance, and meanwhile, because the concentrations of the introduced first N-type silicon carbide buffer layer and the second N-type silicon carbide buffer layer are higher than that of a drift region, the conduction voltage drop of the device can be further reduced. When a device passes a large surge current, because a large voltage drop is generated in the N-type silicon carbide by a large transverse current above a P-type silicon carbide/N-type silicon carbide PN junction, the P-type silicon carbide/N-type silicon carbide PN junction on the back is conducted, and a large number of holes are injected into the N-type silicon carbide by the P-type silicon carbide on the back to form local conductance modulation, so that the conduction resistance in the N-type silicon carbide is reduced, the loss of the device is obviously reduced, and the through-current capability of the device is improved, so that the surge current resistance of the device is improved, and the device has high surge current bearing capability.

When forward voltage resistance is achieved, firstly, the PN junction formed by the P-type base region and the first N-type silicon carbide buffer layer carries out voltage resistance, the concentration of the introduced first N-type silicon carbide buffer layer is not very high, so that the depletion region can penetrate through the first N-type silicon carbide buffer layer and continuously extends towards the lower part of the drift region, and when the depletion region reaches the second N-type silicon carbide buffer layer, the concentration of the second N-type silicon carbide buffer layer is higher than that of the drift region, so that the extension of the depletion region can be prevented, and larger forward voltage resistance is guaranteed. When the device reaches the first N-type silicon carbide buffer layer, because the concentration of the first N-type silicon carbide buffer layer is higher than that of the drift region, the expansion of the depletion region is stopped, the punch-through of the device is prevented, and the device is ensured to have larger reverse withstand voltage. Therefore, the device structure has large forward and reverse symmetric voltage resistance and smaller forward conduction voltage drop.

The beneficial effects of the invention are as follows:

bidirectional switches are the core devices of multilevel inverters and matrix inverters. Two RB-IGBTs are reversely connected in parallel to form a bidirectional switch, a non-punch-through (NPT) structure is usually adopted for the conventional silicon-based RB-IGBT, and the IGBT drift region of the structure is long, so that the current tailing is serious, and the turn-off loss is large. Compared with a silicon-based IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. The invention relates to a groove type silicon carbide reverse resistance MOSFET device, which has a structure with larger forward and reverse symmetrical voltage resistance and smaller forward conduction voltage drop.

Drawings

FIG. 1 is a schematic diagram of a conventional trench-type silicon carbide MOSFET half-cell structure;

FIG. 2 is a schematic diagram of a half-cell structure according to embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of a half-cell structure according to embodiment 2 of the present invention;

FIG. 4 is a schematic diagram of a half-cell structure according to embodiment 3 of the present invention;

FIG. 5 is a schematic view of a first derivative structure half-cell of embodiment 1 of the present invention;

FIG. 6 is a schematic view of a second derivative structure half-cell of embodiment 1 of the present invention;

FIG. 7 is a schematic view of a first derivative structure half-cell of embodiment 2 of the present invention;

FIG. 8 is a schematic view of a second derivative structure half-cell of embodiment 2 of the present invention;

FIG. 9 is a schematic view of a first derivative structure half-cell of embodiment 3 of the present invention;

FIG. 10 is a schematic view of a second derivative structure half-cell of embodiment 3 of the present invention;

FIG. 11 is a schematic diagram of a half-cell of a front side structure of the present invention, the front side structure being suitable for use with all devices of the present invention;

FIG. 12 is a schematic diagram of a front side structure of a cell of the present invention, the front side structure being suitable for use in all devices of the present invention;

fig. 13 is a schematic structural diagram of the manufacturing process of embodiment 1 of the present invention after a second N-type silicon carbide buffer layer 21 is epitaxially formed on the N-type substrate 2 by an epitaxial process;

fig. 14 is a schematic structural diagram of the second N-type silicon carbide buffer layer 21 after the N-type epitaxial layer 3 is epitaxially formed thereon by an epitaxial process in the manufacturing process of claim 1;

fig. 15 is a schematic structural diagram of a process of manufacturing the device according to claim 1 after a trench is etched above the N-type epitaxial layer 3 by photolithography and etching;

fig. 16 is a schematic structural diagram of a thin gate dielectric layer 10 grown on the surface of the trench by a thermal oxidation process in the manufacturing process of claim 1;

fig. 17 is a schematic structural diagram of the gate dielectric layer 10 after the gate 9 is deposited and formed by a deposition process in the manufacturing process of the technical scheme 1 of the present invention;

fig. 18 is a schematic structural diagram of the first N-type silicon carbide buffer layer 11, the P-type base region 4, the N-type source region 7, and the P-type source region 5 formed in the N-type epitaxial layer 3 in sequence by photolithography and ion implantation in the manufacturing process of technical scheme 1 of the present invention;

fig. 19 is a schematic structural diagram of a reversed silicon wafer in the manufacturing process of technical scheme 1 of the present invention, after the N-type silicon carbide substrate 2 is removed by a grinding process;

fig. 20 is a schematic structural diagram of the second N-type silicon carbide buffer layer 21 after the P-type region 12 is formed by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention;

fig. 21 is a schematic structural diagram of a P-type polysilicon region 13 formed on the back surface of the second N-type silicon carbide buffer layer 21 by deposition and etching processes in the manufacturing process of claim 1.

Fig. 22 is a schematic structural diagram of the source metal 6 formed on the surfaces of the N-type source region 7 and the P-type source region 5 by an evaporation or sputtering process and an etching process in the manufacturing process of technical scheme 1 of the present invention;

fig. 23 is a schematic structural diagram after the back drain metal 1 is formed by deposition and etching processes in the manufacturing process of technical scheme 1 of the present invention.

In fig. 1 to 12, 1 is a back drain metal, 2 is an N-type silicon carbide substrate, 21 is a second N-type silicon carbide buffer layer, 3 is an N-type silicon carbide epitaxial layer, 4 is a first P-type base region, 41 is a second P-type base region, 42 is a third P-type base region, 5 is a first P-type source region, 51 is a second P-type source region, 52 is a third P-type source region, 6 is a source metal, 7 is a first N-type source region, 71 is a second N-type source region, 72 is a third N-type source region, 9 is a gate electrode, 10 is a gate dielectric layer, 11 is a first N-type silicon carbide buffer layer, 12 is a P-type region, 13 is a P-type polysilicon region, 14 is a P-type buried layer, 15 is a shield gate, and 16 is a shield gate dielectric layer.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Example 1:

a silicon carbide reverse resistance type trench MOSFET device has a half-cell structure as shown in FIG. 2, wherein the half-cell structure comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

The embodiment also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer 11, a P-type silicon carbide base region 4, an N-type silicon carbide source region 7 and a P-type silicon carbide source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and 8: preparing P-type regions 12 distributed at intervals in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

and step 9: preparing a P-type polycrystalline silicon region 13 on the back of the second N-type silicon carbide buffer layer 21 by adopting a deposition and etching process;

step 10: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

All silicon carbide materials are replaced by material A, A is selected from one of gallium nitride, gallium oxide, boron nitride and silicon materials, polysilicon materials are replaced by material B, and the forbidden bandwidth of the material B is smaller than that of the material A.

Example 2:

a silicon carbide reverse resistance type trench MOSFET device has a half-cell structure as shown in FIG. 3, wherein the half-cell structure comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; no contact is formed between the lower part of the P-type region 12 and the back drain metal 1, and the P-type region completely floats in the second N-type silicon carbide buffer layer 21; the P-type polysilicon region 13 is located below the P-type region 12 and has a smaller width than the P-type region 12.

The embodiment also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and 4, step 4: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 5: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

step 6: sequentially forming a first N-type silicon carbide buffer layer 11, a P-type silicon carbide base region 4, an N-type silicon carbide source region 7 and a P-type silicon carbide source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and 8: preparing P-type regions 12 distributed at intervals in the second N-type silicon carbide buffer layer 21 by photoetching and ion implantation processes;

and step 9: preparing a P-type polycrystalline silicon region 13 on the back of the second N-type silicon carbide buffer layer 21 by adopting a deposition and etching process;

step 10: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

The difference between this embodiment and embodiment 1 is that the structure of the back surface of the device is obviously adjusted, the P-type region 12 is completely floated in the second N-type silicon carbide buffer layer 21 and does not contact with the drain metal 1, and at the same time, the position of the P-type polysilicon region 13 is adjusted. When conducting in the forward direction, the current still flows through the P-type polysilicon/N-type silicon carbide heterojunction, so that the forward conducting voltage drop is lower. The forward withstand voltage principle is similar to that of a conventional silicon carbide MOSFET. When reverse voltage resistance is performed, because the floating P-type region 12 is located above the P-type polysilicon 13 and has a width greater than that of the P-type polysilicon 13, compared with embodiment 1, the P-type region 12 can better shield the heterojunction interface in this embodiment, further reducing leakage current and improving reverse voltage resistance.

Example 3:

a silicon carbide reverse resistance type trench MOSFET device has a half-cell structure as shown in FIG. 4, wherein the half-cell structure comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3,

a grid 9 and a first N-type silicon carbide buffer layer 11 are arranged above the N-type silicon carbide epitaxial layer 3, a first P-type base region 4 is arranged above the first N-type silicon carbide buffer layer 11, a first P-type source region 5 and a first N-type source region 7 are arranged above the first P-type base region 4, the first P-type source region 5 and the first N-type source region 7 are connected left and right, and source metal 6 is respectively connected with the first P-type source region 5 and part of the first N-type source region 7 up and down;

gate dielectric layers 10 are arranged between the gate 9 and the N-type silicon carbide epitaxial layer 3, between the gate 9 and the first N-type source region 7, between the gate 9 and the first P-type base region 4 and between the gate 9 and the first N-type silicon carbide buffer layer 11;

the P-type polycrystalline silicon regions 13 are not connected in the second N-type silicon carbide buffer layer 21; the P-type regions 12 are also unconnected in the second N-type silicon carbide buffer layer 21; the upper surface of the P-type polysilicon region 13 is in contact with the P-type region 12, and the lower surface is in contact with the back drain metal 1.

The present embodiment is different from embodiments 1 and 2 in that the P-type polysilicon region 13 is formed by an etching filling method. The principle of this embodiment is substantially the same as that of embodiment 2.

The invention also provides a preparation method of the silicon carbide trench MOSFET device, which comprises the following preparation steps:

the technical scheme comprises the following preparation steps:

step 1: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

step 2: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;

and step 3: growing a gate dielectric layer 10 on the surface of the trench by adopting a thermal oxidation process;

and 4, step 4: depositing a gate 9 in the gate dielectric layer 10 by adopting a deposition process;

and 5: sequentially forming a first N-type silicon carbide buffer layer 11, a first P-type base region 4, a first N-type source region 7 and a first P-type source region 5 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;

step 6: turning over the silicon wafer, and preparing P-type regions 12 distributed at intervals by adopting photoetching and ion implantation processes;

and 7: preparing etching grooves distributed at intervals by adopting an etching process;

and 8: filling the etching groove with a P-type polycrystalline silicon region 13 by adopting a deposition process;

and step 9: preparing a source metal 6 by adopting an evaporation or sputtering process and an etching process;

step 10: and preparing the back drain electrode metal 1 by adopting an evaporation or sputtering process and an etching process.

Example 4:

a derived structure of embodiment 1 has a half-cell structure as shown in fig. 5, in this embodiment, a P-type buried layer 14 is disposed under a gate dielectric layer 10 in embodiment 1, and the rest of the structure is the same as that in embodiment 1. The specific principle is as follows: because the silicon carbide has a higher critical breakdown electric field compared with silicon, the higher critical breakdown electric field causes that the electric field in the gate dielectric layer is far larger than the electric field in the gate dielectric layer of the silicon-based MOSFET when the silicon carbide MOSFET device breaks down, thereby reducing the reliability of the gate dielectric layer. The P-type buried layer 14 introduced in this embodiment can effectively reduce the electric field in the gate dielectric layer at the corner of the bottom of the trench, and improve the forward voltage withstanding capability.

Example 5:

a half-cell structure of a derivative structure in embodiment 1 is shown in fig. 6, which is an improvement on the basis of embodiment 4, a shielding gate 15 short-circuited with a source metal 6 and a shielding gate dielectric layer 16 on the right side thereof are disposed below the gate dielectric layer 10, a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, and the rest of the structure is the same as that in embodiment 4. The specific principle is as follows: the trench gate MOSFET can significantly increase the current density, but also brings about an increase in gate-drain capacitance, increasing the power loss at turn-off. The magnitude of the gate-drain capacitance is directly related to the effective overlap area between the gate region and the drain region. The shielding gate 15 introduced in the present embodiment effectively reduces the effective overlapping area between the gate region and the drain region, thereby reducing the gate-drain capacitance. In addition, the thickness of the shielding gate dielectric layer 16 is larger than that of the gate oxide layer, so that the forward voltage resistance of the device is improved.

Example 6:

a derived structure of embodiment 2 has a half-cell structure as shown in fig. 7, in this embodiment, a P-type buried layer 14 is disposed under the gate dielectric layer 10 of embodiment 2, and the rest of the structure is the same as that of embodiment 2. The specific principle is as follows: because the silicon carbide has a higher critical breakdown electric field compared with silicon, the higher critical breakdown electric field causes that the electric field in the gate dielectric layer is far larger than the electric field in the gate dielectric layer of the silicon-based MOSFET when the silicon carbide MOSFET device breaks down, thereby reducing the reliability of the gate dielectric layer. The P-type buried layer 14 introduced in this embodiment can effectively reduce the electric field in the gate dielectric layer at the corner of the bottom of the trench, and improve the forward voltage withstanding capability.

Example 7:

a derived structure of embodiment 2 is a half-cell structure as shown in fig. 8, which is an improvement on the basis of embodiment 6, in which a shielding gate 15 short-circuited with a source metal 6 and a shielding gate dielectric layer 16 on the right side thereof are disposed below a gate dielectric layer 10, a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, and the rest of the structure is the same as that of embodiment 6. The specific principle is as follows: the trench gate MOSFET can significantly increase the current density, but also brings about an increase in gate-drain capacitance, increasing the power loss at turn-off. The magnitude of the gate-drain capacitance is directly related to the effective overlap area between the gate region and the drain region. The shielding gate 15 introduced in the present embodiment effectively reduces the effective overlapping area between the gate region and the drain region, thereby reducing the gate-drain capacitance. In addition, the thickness of the shielding gate dielectric layer 16 is larger than that of the gate oxide layer, so that the forward voltage resistance of the device is improved.

Example 8:

a derived structure of embodiment 3 has a half-cell structure as shown in fig. 9, in this embodiment, a P-type buried layer 14 is disposed under the gate dielectric layer 10 of embodiment 2, and the rest of the structure is the same as that of embodiment 3. The specific principle is as follows: because the silicon carbide has a higher critical breakdown electric field compared with silicon, the higher critical breakdown electric field causes that the electric field in the gate dielectric layer is far larger than the electric field in the gate dielectric layer of the silicon-based MOSFET when the silicon carbide MOSFET device breaks down, thereby reducing the reliability of the gate dielectric layer. The P-type buried layer 14 introduced in this embodiment can effectively reduce the electric field in the gate dielectric layer at the corner of the bottom of the trench, and improve the forward voltage withstanding capability.

Example 9:

a derived structure of embodiment 3 is a half-cell structure as shown in fig. 10, which is an improvement on the basis of embodiment 8, wherein a shielding gate 15 short-circuited with a source metal 6 and a shielding gate dielectric layer 16 on the right side thereof are disposed below the gate dielectric layer 10, a P-type buried layer 14 is disposed below the shielding gate dielectric layer 16, and the rest of the structure is the same as that of embodiment 8. The specific principle is as follows: the trench gate MOSFET can significantly increase the current density, but also brings about an increase in gate-drain capacitance, increasing the power loss at turn-off. The magnitude of the gate-drain capacitance is directly related to the effective overlap area between the gate region and the drain region. The shielding gate 15 introduced in the present embodiment effectively reduces the effective overlapping area between the gate region and the drain region, thereby reducing the gate-drain capacitance. In addition, the thickness of the shielding gate dielectric layer 16 is larger than that of the gate oxide layer, so that the forward voltage resistance of the device is improved.

Example 10

The silicon carbide MOSFET comprises a half-cell structure which comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 10 is arranged above the first N-type silicon carbide buffer layer 11, a gate 9 is arranged inside the gate dielectric layer 10, a first P-type base region 4 is arranged on the right side of the gate dielectric layer 10, the left side of the first P-type base region 4 is in contact with the gate dielectric layer 10, the left upper surface of the first P-type base region is in contact with a first N-type source region 7, the right upper surface of the first P-type base region is in contact with a first P-type source region 5, the lower part of the first P-type base region is in contact with the first N-type silicon carbide buffer; the source metal 6 covers the upper and right surfaces of the first N-type source region 7,

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

The frontal structure of the half cell is applicable to any of the structures of embodiments 1-9 described above.

Example 11

Referring to fig. 12, the cell structure of the sic MOSFET includes a back drain metal 1, a second N-type sic buffer layer 21, and an N-type sic epitaxial layer 3 stacked in this order from bottom to top,

a first N-type silicon carbide buffer layer 11 is arranged above the N-type silicon carbide epitaxial layer 3, a grid electrode 9 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 11, a grid medium layer 10 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 11, a second P-type source region 51 is arranged on the right side of the second P-type source region 51, a second N-type source region 71 and a second P-type base region 41 are arranged on the right side of the second N-type silicon carbide buffer layer 11, the second N-type source region 71 and the second P-type base region 41 are connected up and down, a third P-type source region 52 is arranged on the right side of the grid electrode 9, the third P-type source region 52 extends to the middle of the grid electrode 9 leftwards, a third N-type source region 72 and a third P-type base region 42 are arranged on the right side of the third P-type source region 52, the third N-type base region 72 and the third P-type base region 42 are connected up and down, the grid electrode 9 and the second N-type source;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 12; ohmic contact is formed between the lower part of the P-type region 12 and the back drain metal 1; a P-type polycrystalline silicon region 13 is arranged between the adjacent P-type regions 12, the upper surface of the P-type polycrystalline silicon region 13 is connected with the second N-type silicon carbide buffer layer 21, and the lower surface of the P-type polycrystalline silicon region is connected with the back drain metal 1.

The frontal structure of the cell is applicable to any of the structures of embodiments 1-9 described above.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.