阅读说明：本技术 一种基于跨时钟域的异步时钟选择电路及其切换方法 (Asynchronous clock selection circuit based on clock domain crossing and switching method thereof ) 是由 王爽 段曦冉 陈晓棠 丁岩 唐虹 于 2020-12-21 设计创作，主要内容包括：本发明涉及一种基于跨时钟域的异步时钟选择电路及其切换方法,根据时钟选择信号的要求,选择不同的时钟信号输出。利用跨时钟域的异步时钟选择电路,实现时钟选择信号和时钟停止信号与目标时钟信号同步。将控制信号同步,可以在提高异步时钟切换稳定性的同时,最大程度的规避异步时钟切换毛刺。满足实际跨时钟域电路中异步时钟切换对稳定性的要求,同时跨时钟域的异步时钟选择电路在稳定性的表现较直接切换时钟电路会更加优秀。(The invention relates to an asynchronous clock selection circuit based on a clock domain crossing and a switching method thereof. And the clock selection signal and the clock stop signal are synchronized with the target clock signal by using the asynchronous clock selection circuit crossing the clock domain. The control signals are synchronous, so that the switching stability of the asynchronous clock can be improved, and the switching burrs of the asynchronous clock can be avoided to the greatest extent. The requirement of the stability of the asynchronous clock switching in the actual clock domain crossing circuit is met, and meanwhile, the performance of the clock domain crossing asynchronous clock selection circuit in the stability is more excellent than that of a clock circuit directly switched.)

1. An asynchronous clock selection circuit based on clock domain crossing, comprising: the clock selection output circuit is connected with the first clock branch circuit and the second clock branch circuit;

the first clock branch and the second clock branch comprise a primary clock circuit and a secondary clock circuit which are sequentially connected;

and the secondary clock circuit of the first clock branch and the secondary clock circuit of the second clock branch are both connected with the clock selection output circuit.

2. The asynchronous clock selection circuit based on the cross-clock domain is characterized in that the primary clock circuit comprises five registers, wherein clock input ends of the five registers are used for accessing a clock signal;

the data input end of the first register is used as a clock end selection end and used for receiving a clock selection signal;

the first register, the second register and the third register are sequentially connected in series, the output end of the second register and the output end of the third register are respectively connected with two input ends of an AND gate A, the output end of the AND gate A is connected with the input end of a fourth register, and the output end of the fourth register is used as a first output end of a primary clock circuit;

the output end of the second register and the output end of the third register are respectively connected with two input ends of the NOR gate, and the output end of the NOR gate is used as the second output end of the first-stage clock circuit.

3. The asynchronous clock selection circuit based on cross-clock domain of claim 1,

for the first clock branch, the first output end of the first-stage clock circuit is connected with the second-stage clock circuit, and the second output end of the first-stage clock circuit is connected with the second-stage clock circuit in the second clock branch;

for the second clock branch, the first output end of the first-stage clock circuit is connected with the second-stage clock circuit, and the second output end of the first-stage clock circuit is connected with the second-stage clock circuit in the first clock branch.

4. The asynchronous clock selection circuit based on cross-clock domain as claimed in claim 1, wherein the secondary clock circuit comprises four registers, the clock input terminals of the four registers are used for accessing the clock signal;

the data input end of the sixth register is used as the input end of the second-stage clock circuit;

the sixth register, the seventh register and the eighth register are sequentially connected in series, the output end of the seventh register and the output end of the eighth register are respectively connected with two input ends of an AND gate B, the output end of the AND gate B is connected with the input end of a ninth register, the output end of the ninth register and the first output end of the primary clock circuit are respectively connected with two input ends of an AND gate C, and the output end of the AND gate C is used as the output end of the secondary clock circuit.

5. The asynchronous clock selection circuit based on the cross-clock domain is characterized in that the clock selection output circuit comprises a register A, a register B, an AND gate D, an AND gate E and an OR gate; the clock input end of the register A, the clock input end of the register B, the second input end of the AND gate D and the second input end of the AND gate E are all connected with clock signals;

the input end of the register A is connected with the output end of the secondary clock circuit in the first clock branch, and the output end of the register A is connected with the first input end of the AND gate D;

the input end of the register B is connected with the output end of the secondary clock circuit in the second clock branch, and the output end of the register B is connected with the first input end of the AND gate E; the second input end of the AND gate E is connected with the first output end of the first-stage clock circuit in the second clock branch circuit;

the output end of the AND gate D and the output end of the AND gate E are respectively connected with two input ends of the OR gate, and the output end of the OR gate is used as the output of the asynchronous clock selection circuit and used for outputting a system working clock.

6. A cross-clock domain asynchronous clock selection switching method is characterized in that: a control circuit for selecting an operating clock for a microprocessor system in response to a clock select signal, comprising the steps of:

the first-stage clock circuit performs clock synchronization of a clock selection signal: converting a clock selection signal asynchronous with a target clock into a target signal clock selection signal synchronous with the target clock; judging and outputting a current clock stop signal according to the clock selection signal;

the second-level clock circuit performs clock synchronization of the current clock stop signal: converting a current clock stop signal asynchronous with the target clock into a current clock stop signal synchronous with the target clock;

the control signal after the target clock synchronization is judged, that is, the selection signal and the stop signal, and the clock selected by the control signal is output.

7. The method according to claim 6, wherein the clock synchronization of the clock selection signal specifically comprises: registering the clock selection signal for 3 times according to the target clock, and performing phase comparison between the clock selection signal registered for the 2 nd time and the clock selection signal registered for the 3 rd time to obtain a stable clock selection signal synchronous with the target clock;

the clock synchronization of the clock stop signal is specifically as follows: and registering the clock stop signal for 3 times according to the target clock, and performing AND operation on the clock stop signal registered for the 2 nd time and the clock stop signal registered for the 3 rd time to obtain a stable clock stop signal synchronous with the target clock.

8. The method as claimed in claim 6, wherein the clock selection signal determines the clock stop signal, and if the clock selection signal selects a non-current clock, the clock stop signal is at a high level, otherwise the clock stop signal is at a low level.

9. The method of claim 6, wherein if the synchronized clock selection signal and the synchronized current clock stop signal are both high, the output is the target clock, otherwise the output is the current clock.

10. An asynchronous clock switching method based on clock domain crossing is characterized by comprising the following steps:

when the current clock is the clock 2 received by the second clock branch and the clock selection signal is selected to be switched to the clock 1, the clock selection signal of the first-stage clock circuit of the first clock branch is at a high level, the clock selection signal is driven by the clock 2 at the moment, and the clock selection signal is an asynchronous signal of the clock 1 received by the first clock branch;

in the first clock branch, register the clock selection signal 3 times in clock 1, change clock 1 selection signal and clock 1 into the synchronizing signal to control the clock; when the secondary register signal of the clock 1 selection signal output by the second register and the tertiary register signal of the clock 1 selection signal output by the third register are both high level, the clock 1 selection signal output by the fourth register after synchronization is high level;

in the second clock branch, when the secondary register signal of the clock 2 selection signal output by the second register and the tertiary register signal of the clock 2 selection signal output by the third register are both at low level, the stop signal of the clock 2 output by the fifth register is at high level; at this time, the clock 2 stop signal is driven by the clock 2, so the clock 2 stop signal is an asynchronous signal of the clock 1;

the second-level clock circuit of the first clock branch registers the stop signal of the clock 2 for 3 times under the clock 1, and the stop signal of the clock 2 and the clock 1 are changed into synchronous signals to control the clock;

in the first clock branch, when the secondary register signal of the clock 2 stop signal output by the seventh register and the tertiary register signal of the clock 2 stop signal output by the eighth register are both at high level, the clock 2 stop signal output by the ninth register after synchronization is at high level;

and finally, after the clock 1 selection signal after the synchronization and the clock 2 stop signal after the synchronization are both high, the clock 1 enable signal output by the register A in the output circuit is at a high level, and the output clock is converted into the clock 1 from the clock 2 at the moment.

Technical Field

The invention belongs to the field of embedded microprocessors, and provides a circuit design capable of stably and efficiently switching clocks.

Background

With the development of consumer electronics, automotive electronics, industrial control and other fields, the application of high-performance embedded microprocessors is more and more extensive, and the requirements on the processing capability of the embedded microprocessors are also more and more high. Meanwhile, the application fields of the embedded microprocessor are mostly portable equipment, consumer electronics and field control equipment, the requirements on the time sequence of the embedded microprocessor are very strict, and the embedded microprocessor is required to stabilize the clock as much as possible. Therefore, in order to meet the application requirements of the embedded microprocessor, the stability of the embedded microprocessor needs to be improved, and the efficiency of the embedded microprocessor needs to be reduced as much as possible.

The existing embedded processor adopts a clock conversion circuit for filtering, and meanwhile, in order to increase efficiency, the existing circuit structure mostly adopts asynchronous control logic to directly convert a clock. Although this circuit design handles the glitch, it also increases the stability of the circuit to a certain extent, but the stability of the circuit cannot be increased to a greater extent while the efficiency of the circuit is increased. Therefore, the asynchronous clock selection circuit crossing the clock domain is designed, high efficiency and high stability of a circuit clock are combined by utilizing a plurality of registers and gates, and the system stability can be improved to the maximum extent while the system clock processing capacity is improved.

Disclosure of Invention

The invention aims to design a stable and efficient clock domain crossing asynchronous clock selection circuit to overcome the defects of the asynchronous clock switching circuit. And the clock selection signal and the clock stop signal are synchronized with the target clock signal by using the asynchronous clock selection circuit crossing the clock domain. The control signals are synchronous, so that the switching stability of the asynchronous clock can be improved, and the switching burrs of the asynchronous clock can be avoided to the greatest extent. The requirement of the stability of the asynchronous clock switching in the actual clock domain crossing circuit is met, and meanwhile, the performance of the clock domain crossing asynchronous clock selection circuit in the stability is more excellent than that of a clock circuit directly switched.

The technical scheme adopted by the invention for realizing the purpose is as follows: an asynchronous clock selection circuit based on clock domain crossing, comprising: the clock selection output circuit is connected with the first clock branch circuit and the second clock branch circuit;

the first clock branch and the second clock branch comprise a primary clock circuit and a secondary clock circuit which are sequentially connected;

and the secondary clock circuit of the first clock branch and the secondary clock circuit of the second clock branch are both connected with the clock selection output circuit.

The first-stage clock circuit comprises five registers, and the clock input ends of the five registers are used for accessing clock signals;

the data input end of the first register is used as a clock end selection end and used for receiving a clock selection signal;

the first register, the second register and the third register are sequentially connected in series, the output end of the second register and the output end of the third register are respectively connected with two input ends of an AND gate A, the output end of the AND gate A is connected with the input end of a fourth register, and the output end of the fourth register is used as a first output end of a primary clock circuit;

the output end of the second register and the output end of the third register are respectively connected with two input ends of the NOR gate, and the output end of the NOR gate is used as the second output end of the first-stage clock circuit.

For the first clock branch, the first output end of the first-stage clock circuit is connected with the second-stage clock circuit, and the second output end of the first-stage clock circuit is connected with the second-stage clock circuit in the second clock branch;

for the second clock branch, the first output end of the first-stage clock circuit is connected with the second-stage clock circuit, and the second output end of the first-stage clock circuit is connected with the second-stage clock circuit in the first clock branch.

The secondary clock circuit comprises four registers, and the clock input ends of the four registers are used for accessing clock signals;

the data input end of the sixth register is used as the input end of the second-stage clock circuit;

the sixth register, the seventh register and the eighth register are sequentially connected in series, the output end of the seventh register and the output end of the eighth register are respectively connected with two input ends of an AND gate B, the output end of the AND gate B is connected with the input end of a ninth register, the output end of the ninth register and the first output end of the primary clock circuit are respectively connected with two input ends of an AND gate C, and the output end of the AND gate C is used as the output end of the secondary clock circuit.

The clock selection output circuit comprises a register A, a register B, an AND gate D, an AND gate E and an OR gate; the clock input end of the register A, the clock input end of the register B, the second input end of the AND gate D and the second input end of the AND gate E are all connected with clock signals;

the input end of the register A is connected with the output end of the secondary clock circuit in the first clock branch, and the output end of the register A is connected with the first input end of the AND gate D;

the input end of the register B is connected with the output end of the secondary clock circuit in the second clock branch, and the output end of the register B is connected with the first input end of the AND gate E; the second input end of the AND gate E is connected with the first output end of the first-stage clock circuit in the second clock branch circuit;

the output end of the AND gate D and the output end of the AND gate E are respectively connected with two input ends of the OR gate, and the output end of the OR gate is used as the output of the asynchronous clock selection circuit and used for outputting a system working clock.

A cross-clock domain asynchronous clock selection switching method selects a control circuit of a microprocessor system working clock according to the requirement of a clock selection signal, and comprises the following steps:

the first-stage clock circuit performs clock synchronization of a clock selection signal: converting a clock selection signal asynchronous with a target clock into a target signal clock selection signal synchronous with the target clock; judging and outputting a current clock stop signal according to the clock selection signal;

the second-level clock circuit performs clock synchronization of the current clock stop signal: converting a current clock stop signal asynchronous with the target clock into a current clock stop signal synchronous with the target clock;

the control signal after the target clock synchronization is judged, that is, the selection signal and the stop signal, and the clock selected by the control signal is output.

The clock selection signal clock synchronization specifically comprises: registering the clock selection signal for 3 times according to the target clock, and performing phase comparison between the clock selection signal registered for the 2 nd time and the clock selection signal registered for the 3 rd time to obtain a stable clock selection signal synchronous with the target clock;

the clock synchronization of the clock stop signal is specifically as follows: and registering the clock stop signal for 3 times according to the target clock, and performing AND operation on the clock stop signal registered for the 2 nd time and the clock stop signal registered for the 3 rd time to obtain a stable clock stop signal synchronous with the target clock.

The clock selection signal judges a clock stop signal, if the clock selection signal selects a non-current clock, the clock stop signal is at a high level, otherwise, the clock stop signal is at a low level.

If the synchronized clock selection signal and the synchronized current clock stop signal are both high level, the output is the target clock, otherwise, the output is still the current clock.

An asynchronous clock switching method based on clock domain crossing comprises the following steps:

when the current clock is the clock 2 received by the second clock branch and the clock selection signal is selected to be switched to the clock 1, the clock selection signal of the first-stage clock circuit of the first clock branch is at a high level, the clock selection signal is driven by the clock 2 at the moment, and the clock selection signal is an asynchronous signal of the clock 1 received by the first clock branch;

in the first clock branch, register the clock selection signal 3 times in clock 1, change clock 1 selection signal and clock 1 into the synchronizing signal to control the clock; when the secondary register signal of the clock 1 selection signal output by the second register and the tertiary register signal of the clock 1 selection signal output by the third register are both high level, the clock 1 selection signal output by the fourth register after synchronization is high level;

in the second clock branch, when the secondary register signal of the clock 2 selection signal output by the second register and the tertiary register signal of the clock 2 selection signal output by the third register are both at low level, the stop signal of the clock 2 output by the fifth register is at high level; at this time, the clock 2 stop signal is driven by the clock 2, so the clock 2 stop signal is an asynchronous signal of the clock 1;

the second-level clock circuit of the first clock branch registers the stop signal of the clock 2 for 3 times under the clock 1, and the stop signal of the clock 2 and the clock 1 are changed into synchronous signals to control the clock;

in the first clock branch, when the secondary register signal of the clock 2 stop signal output by the seventh register and the tertiary register signal of the clock 2 stop signal output by the eighth register are both at high level, the clock 2 stop signal output by the ninth register after synchronization is at high level;

and finally, after the clock 1 selection signal after the synchronization and the clock 2 stop signal after the synchronization are both high, the clock 1 enable signal output by the register A in the output circuit is at a high level, and the output clock is converted into the clock 1 from the clock 2 at the moment.

The invention has the following beneficial effects and advantages:

1. the invention adopts a sequential logic circuit, designs asynchronous clock conversion, replaces the existing all-time conversion circuit, and realizes higher stability while increasing the clock efficiency of the system.

2. The invention adopts multi-time three-level register to realize the synchronization of the existing control logic signal and the target clock signal and better control the clock conversion.

3. The invention adopts the method of converting the asynchronous control logic into the synchronous control logic, designs the asynchronous clock conversion, replaces the prior asynchronous control logic to directly convert the clock, avoids the problem of burrs generated by the direct conversion of the clock, and increases the stability of the system.

Drawings

FIG. 1 is a circuit diagram of the asynchronous clock selection across clock domains of the present invention.

FIG. 2 is a schematic diagram of an embodiment of the present invention applied to an embedded microprocessor system.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

A method for realizing asynchronous clock selection switching circuit across clock domains selects a control circuit of a microprocessor system working clock according to the requirement of a clock selection signal, and comprises the following steps:

clock selection signal clock synchronization, converting a clock selection signal asynchronous with a target clock into a target signal clock selection signal synchronous with the target clock;

judging and outputting a current clock stop signal according to the clock selection signal;

the current clock stop signal is synchronous in clock, and the current clock stop signal asynchronous with the target clock is converted into a current clock stop signal synchronous with the target clock;

the control signals (the selection signal and the stop signal) synchronized with the target clock are judged, and the clock selected by the control signals is output.

The clock selection signal clock synchronization specifically comprises: and registering the clock selection signal for 3 times according to the target clock, and performing phase comparison between the clock selection signal registered for the 2 nd time and the clock selection signal registered for the 3 rd time to obtain a stable clock selection signal synchronous with the target clock.

The clock selection signal judges a clock stop signal, if the clock selection signal selects a non-current clock, the clock stop signal is at a high level, otherwise, the clock stop signal is at a low level.

The clock synchronization of the clock stop signal is specifically as follows: and registering the clock stop signal for 3 times according to the target clock, and performing AND operation on the clock stop signal registered for the 2 nd time and the clock stop signal registered for the 3 rd time to obtain a stable clock stop signal synchronous with the target clock.

If the synchronized clock selection signal and the synchronized current clock stop signal are both high level, the output is the target clock, otherwise, the output is still the current clock. The dual control of the selection signal and the current clock stop signal is adopted, so that the output synchronization of the clock switching circuit and the selected clock is ensured, and the clock output is stable and has no burrs.

Different clock signals are selected to be output according to the requirements of the clock selection signals. And the clock selection signal and the clock stop signal are synchronized with the target clock signal by using the asynchronous clock selection circuit crossing the clock domain. The control signals are synchronous, so that the switching stability of the asynchronous clock can be improved, and the switching burrs of the asynchronous clock can be avoided to the greatest extent. The requirement of the stability of the asynchronous clock switching in the actual clock domain crossing circuit is met, and meanwhile, the performance of the clock domain crossing asynchronous clock selection circuit in the stability is more excellent than that of a clock circuit directly switched.

The design idea of the asynchronous clock selection circuit across clock domains is shown in fig. 1, where clk1 is clock signal 1, clk2 is clock signal 2, clk _ sel is clock selection signal, clk1_ sel _ sync1 is clock 1 selection signal secondary register signal, clk1_ sel _ sync2 is clock 1 selection signal tertiary register signal, clk2_ sel _ sync1 is clock 2 selection signal secondary register signal, clk2_ sel _ sync2 is clock 2 selection signal tertiary register signal, clk1_ stop is clock 1 stop signal, clk2_ stop is clock 2 stop signal, clk 8 _ sel _ sync _ o is clock 1 selection signal after synchronization is completed, clk2_ sel _ sync _ o is clock 2 selection signal after synchronization is completed, clk1_ stop _ sync1 is clock 1 sync stop signal, sync _ stop signal 2 is clock 1 stop signal, and clk _ stop signal 2 is clock 1_ sync _ stop signal secondary register signal. clk2_ stop _ sync2 is a clock 2 stop signal three-level register signal, clk1_ stop _ sync _ o is a clock 1 stop signal after synchronization is completed, clk2_ stop _ sync _ o is a clock 2 stop signal after synchronization is completed, clk1_ out _ en is a clock 1 enable signal, clk2_ out _ en is a clock 2 enable signal, and clk _ out is an output clock.

When the current clock is clock 2, the clock select signal is changed to low (representing the selection of clock 1), which is an asynchronous signal of clock 1 since the clock select signal is driven by clock 2 at this time. The clock selection signal is registered 3 times at clock 1, and the clock 1 selection signal and clock 1 are changed into synchronous signals to control the clock. And when the clock 1 selection signal secondary register signal and the clock 1 selection signal tertiary register signal are both in high level, the clock 1 selection signal after synchronization is in high level. When the clock 2 selection signal secondary register signal and the clock 2 selection signal tertiary register signal are both at low level, the clock 2 stop signal is at high level. At this time, the clock 2 stop signal is driven by clock 2, so the clock 2 stop signal is an asynchronous signal to clock 1. The clock 2 stop signal is registered 3 times under the clock 1, and the clock 2 stop signal and the clock 1 are changed into a synchronous signal to control the clock. When the secondary register signal of the clock 2 stop signal and the tertiary register signal of the clock 2 stop signal are both at high level, the clock 2 stop signal after synchronization is at high level. And finally, after the clock 1 selection signal after the synchronization and the clock 2 stop signal after the synchronization are both high, the clock 1 enable signal is at a high level. At which time the output clock is converted from clock 2 to clock 1.

Clock 1 is converted to clock 2 for the same reason.

Referring to fig. 2, in an application example of the present invention applied to an embedded microprocessor system, two clock signals input may be different from those in fig. 2, and a two-input clock signal is designed for implementation, and the application related to the present invention is not limited to this example. FIG. 2 shows an embodiment of the present invention applied to an embedded microprocessor system, in which an RC OSC (RC oscillator) and a crystal oscillator are used as two input clock signals, and one of the RC OSC (RC oscillator) and the PLL is selected as a bus clock of the system after being selected by a selection signal.

In embedded microprocessor systems, there are typically multiple clock transitions. The conversion process of some clocks needs better stability, and the conversion of the clocks can be completed by using the design. The requirement of the embedded microprocessor on the stability of the design time sequence is realized through an asynchronous clock selection circuit crossing clock domains.