阅读说明：本技术 分频电路、锁相环电路以及分频电路的控制方法 (Frequency dividing circuit, phase-locked loop circuit, and method for controlling frequency dividing circuit ) 是由 彭仁国 熊廷文 徐红如 李曙光 于 2020-12-22 设计创作，主要内容包括：本申请涉及一种分频电路、锁相环电路以及分频电路的控制方法,预分频器的第一输入端用于接收压控振荡器的输出频率信号。自动校正计数器与预分频器的输出端连接。可编程计数器与预分频器的输出端连接。脉冲吞吐计数器的输入端与预分频器的输出端和可编程计数器的输出端连接。门电路的第一输入端与脉冲吞吐计数器的输出端连接,门电路的输出端与预分频的第二输入端连接。门电路的第二输入端用于输入自动频率校正使能信号。预分频器输出的信号分别送到自动校正计数器、可编程计数器和脉冲吞吐计数器。因此可以降低自动校正计数器、可编程计数器的工作频率,降低芯片的功耗。(The application relates to a frequency division circuit, a phase-locked loop circuit and a control method of the frequency division circuit. The automatic correction counter is connected with the output end of the prescaler. The programmable counter is connected with the output end of the prescaler. The input end of the pulse throughput counter is connected with the output end of the prescaler and the output end of the programmable counter. The first input end of the gate circuit is connected with the output end of the pulse throughput counter, and the output end of the gate circuit is connected with the second input end of the pre-frequency division. The second input end of the gate circuit is used for inputting the automatic frequency correction enabling signal. The signals output by the prescaler are respectively sent to an automatic correction counter, a programmable counter and a pulse throughput counter. Therefore, the working frequency of the automatic correction counter and the programmable counter can be reduced, and the power consumption of the chip can be reduced.)

1. A frequency-division circuit, comprising:

the first input end of the prescaler is used for receiving an output frequency signal of the voltage-controlled oscillator;

the automatic correction counter is connected with the output end of the prescaler;

the programmable counter is connected with the output end of the prescaler;

the input end of the pulse throughput counter is connected with the output end of the prescaler and the output end of the programmable counter; and

the first input end of the gate circuit is connected with the output end of the pulse throughput counter, the output end of the gate circuit is connected with the second input end of the prescaler, and the second input end of the gate circuit is used for inputting an automatic frequency correction enabling signal.

2. The frequency-dividing circuit of claim 1 wherein the prescaler is a divide-by-N/(N +1) dual-mode prescaler.

3. The frequency divider circuit of claim 1, wherein the gate circuit is a two-input and gate circuit.

4. The crossover circuit of claim 1, wherein the gate circuit is a two-input or gate circuit.

5. A phase locked loop circuit comprising the frequency dividing circuit of any of claims 1 to 3.

6. A control method of a frequency dividing circuit, applied to the frequency dividing circuit of claim 2, comprising:

in the automatic frequency sub-band correction stage of the voltage-controlled oscillator, an automatic frequency correction enabling signal input from the second input end of the gate circuit controls the divide-by-N/(N +1) dual-mode pre-divider to work in a divide-by-N frequency division mode through the gate circuit, and an output frequency signal of the voltage-controlled oscillator input from the input end of the divide-by-N/(N +1) dual-mode pre-divider is input to the automatic correction counter after being subjected to frequency reduction by the divide-by-N/(N +1) dual-mode pre-divider;

in the phase of locking the phase-locked loop, the automatic frequency correction enabling signal input by the second input end of the gate circuit and the control signal output by the pulse throughput counter control the pre-frequency divider through the gate circuit to realize the dual-mode pre-frequency dividing function.

7. The method as claimed in claim 6, wherein the controlling the prescaler through the gate circuit to realize the dual-mode prescaler function comprises, during a phase locked loop locking stage, an automatic frequency correction enable signal inputted to the second input terminal of the gate circuit and a control signal outputted from the pulse throughput counter:

the pulse handling counter counts signals output by the output end of the prescaler according to a preset count value;

the pulse throughput counter outputs a control signal to the gate circuit when counting is finished;

the gate circuit enables the pre-frequency divider to realize a dual-mode pre-frequency dividing function under the control of the control signal and the automatic frequency correction enabling signal.

8. The method as claimed in claim 7, wherein the step of controlling the prescaler through the gate circuit to realize the dual-mode prescaler function further comprises, during a phase locked loop locking phase, an automatic frequency correction enable signal input to the second input terminal of the gate circuit and a control signal output from the pulse throughput counter:

the programmable counter counts signals output by the output end of the prescaler according to a preset count value;

the programmable counter outputs a frequency-divided clock signal to the pulse throughput counter at the end of the counter count;

and the frequency division clock signal is used as a loading signal for loading a preset counting value of the pulse throughput counter, so that the pulse throughput counter starts to count and divide frequency according to a new frequency division preset value after receiving the loading signal.

9. The method of controlling a frequency-dividing circuit according to claim 6, wherein the gate circuit is a two-input and gate circuit.

10. The method of controlling a frequency-dividing circuit according to claim 6, wherein the gate circuit is a two-input or gate circuit.

Technical Field

The present disclosure relates to the field of frequency source generation circuits, and in particular, to a frequency divider circuit, a phase-locked loop circuit, and a method for controlling the frequency divider circuit.

Background

In the field of frequency source generation circuits, such as phase locked loops, VCO frequency subband autocorrection dividers and feedback dividers are commonly used in modern phase locked loop circuits. A feedback divider divides a high frequency VCO (voltage controlled oscillator) signal around a reference frequency, passing through a loop, so that the VCO outputs a desired frequency signal. The VCO frequency subband autocorrection frequency divider also needs to divide the frequency of the VCO output high frequency signal and then operate subsequently. Therefore, the VCO frequency subband automatic correction frequency divider and the feedback frequency divider increase the area and power consumption of a circuit chip, and increase the manufacturing cost.

Disclosure of Invention

In view of the above, it is desirable to provide a frequency dividing circuit, a phase-locked loop circuit, and a method for controlling the frequency dividing circuit.

The embodiment of the application provides a frequency division circuit, including:

the first input end of the prescaler is used for receiving an output frequency signal of the voltage-controlled oscillator;

the automatic correction counter is connected with the output end of the prescaler;

the programmable counter is connected with the output end of the prescaler;

the input end of the pulse throughput counter is connected with the output end of the prescaler and the output end of the programmable counter; and

the first input end of the gate circuit is connected with the output end of the pulse throughput counter, the output end of the gate circuit is connected with the second input end of the prescaler, and the second input end of the gate circuit is used for inputting an automatic frequency correction enabling signal.

In one embodiment, the prescaler is a divide-by-N/(N +1) dual modulus prescaler.

In one embodiment, the gate circuit is a two-input and gate circuit.

In one embodiment, the gate circuit is a two-input or gate circuit.

The embodiment of the application also provides a phase-locked loop circuit which comprises the frequency division circuit.

The embodiment of the present application further provides a control method of a frequency division circuit, which is applied to the frequency division circuit described in the above embodiment, and the method includes:

in the automatic frequency sub-band correction stage of the voltage-controlled oscillator, an automatic frequency correction enabling signal input from the second input end of the gate circuit controls the divide-by-N/(N +1) dual-mode pre-divider to work in a divide-by-N frequency division mode through the gate circuit, and an output frequency signal of the voltage-controlled oscillator input from the input end of the divide-by-N/(N +1) dual-mode pre-divider is input to the automatic correction counter after being subjected to frequency reduction by the divide-by-N/(N +1) dual-mode pre-divider;

in the phase of locking the phase-locked loop, the automatic frequency correction enabling signal input by the second input end of the gate circuit and the control signal output by the pulse throughput counter control the pre-frequency divider through the gate circuit to realize the dual-mode pre-frequency dividing function.

In one embodiment, in the phase-locked loop locking stage, the controlling of the prescaler by the gate circuit according to the automatic frequency correction enable signal input by the second input terminal of the gate circuit and the control signal output by the pulse throughput counter to realize the dual-modulus prescaler function includes:

the pulse handling counter counts signals output by the output end of the prescaler according to a preset count value;

the pulse throughput counter outputs a control signal to the gate circuit when counting is finished;

the gate circuit enables the pre-frequency divider to realize a dual-mode pre-frequency dividing function under the control of the control signal and the automatic frequency correction enabling signal.

In one embodiment, during the phase locked loop locking stage, the enabling signal for automatic frequency correction input at the second input terminal of the gate circuit and the control signal output by the pulse throughput counter control the prescaler through the gate circuit to implement the dual-modulus prescaler function further includes:

the programmable counter counts signals output by the output end of the prescaler according to a preset count value;

the programmable counter outputs a frequency-divided clock signal to the pulse throughput counter at the end of the counter count;

and the frequency division clock signal is used as a loading signal for loading a preset counting value of the pulse throughput counter, so that the pulse throughput counter starts to count and divide frequency according to a new frequency division preset value after receiving the loading signal.

In one embodiment, the gate circuit is a two-input and gate circuit.

In one embodiment, the gate circuit is a two-input or gate circuit.

The frequency dividing circuit provided by the embodiment of the application comprises a prescaler, an automatic correction counter, a programmable counter, a pulse throughput counter and a gate circuit. The first input end of the prescaler is used for receiving an output frequency signal of the voltage-controlled oscillator. The automatic correction counter is connected with the output end of the prescaler. And the programmable counter is connected with the output end of the prescaler. And the input end of the pulse throughput counter is connected with the output end of the prescaler and the output end of the programmable counter. The first input end of the gate circuit is connected with the output end of the pulse throughput counter, and the output end of the gate circuit is connected with the second input end of the pre-frequency division. And the second input end of the gate circuit is used for inputting an automatic frequency correction enabling signal. The signals output by the prescaler are respectively sent to the automatic correction counter, the programmable counter and the pulse throughput counter. And after the first input end of the prescaler receives the output frequency signal of the voltage-controlled oscillator, the prescaler prescales the frequency of the output frequency signal of the voltage-controlled oscillator. Therefore, the working frequency of the automatic correction counter and the programmable counter can be reduced, and the power consumption of a chip is reduced.

In the control method of the frequency division circuit, in the automatic correction stage of the frequency sub-band of the voltage-controlled oscillator, the automatic correction counter counts the signals output by the prescaler, outputs a count value of n bits and sends the count value to the digital baseband for judgment so as to select a proper VCO frequency sub-band. And in the phase-locked loop locking stage, the programmable counter counts the signals output by the prescaler according to a preset count value. And outputting the final frequency division clock when the counting is finished. Meanwhile, the programmable counter can send the pulse throughput counter as a loading signal for loading a preset counting value of the pulse throughput counter. And the pulse throughput counter counts the signals output by the prescaler according to a preset count value. And after the counting is finished, the pulse throughput counter stops counting and outputs a control signal. The pulse throughput counter can count and divide frequency according to a new frequency division preset value under the triggering of the loading signal. The gate circuit is used for controlling the pre-frequency divider to realize a dual-mode pre-frequency dividing function. Therefore, the frequency dividing circuit can realize that the prescaler only works in one frequency dividing mode in the VCO frequency subband automatic correction frequency dividing stage, and the programmable counter and the pulse throughput counter do not work. In the phase-locked loop locking stage, the prescaler, the programmable counter and the pulse throughput counter in the frequency dividing circuit integrally form the function of a phase-locked loop feedback frequency divider, so that the use of devices is reduced, the chip space is saved, and the energy consumption is saved.

Drawings

Fig. 1 is a structural diagram of a prescaler according to an embodiment of the present application;

fig. 2 is a structural diagram of a prescaler according to another embodiment of the present application;

fig. 3 is a structural diagram of a prescaler according to another embodiment of the present application;

fig. 4 is a structural diagram of a prescaler according to another embodiment of the present application.

Description of reference numerals:

frequency dividing circuit 10, prescaler 101, automatic correction counter 102, programmable counter 103, pulse throughput counter 104, and gate circuit 105.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly apparent, the following describes in detail the frequency dividing circuit, the phase-locked loop circuit and the control method of the frequency dividing circuit of the present application by embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the field of frequency source generating circuits, such as phase locked loops, a feedback frequency divider divides a high frequency VCO (voltage controlled oscillator) signal around a reference frequency, and the VCO is made to output a desired frequency signal through the loop. Frequency coverage of VCOThe range is divided into 2 by the switched capacitor^bA frequency sub-band. In the automatic frequency sub-band correction process, the direct counting of the high-frequency VCO signal consumes a large amount of power, so that the output high-frequency signal of the VCO needs to be divided into the lower-frequency signal first, then the low-frequency signal is counted, and the counting result is sent to the digital baseband to be judged and select a proper VCO frequency sub-band. Therefore, the feedback frequency divider and the VCO frequency subband automatic correction frequency divider divide the frequency of the high-frequency signal output by the VCO and then perform subsequent operations. The feedback frequency divider and the VCO frequency subband automatic correction frequency divider increase the area of a chip and improve the power consumption of the chip.

Based on this, the embodiment of the present application provides a frequency-division circuit 10. The frequency dividing circuit 10 includes a prescaler 101, an autocorrelation counter 102, a programmable counter 103, a pulse throughput counter 104, and a gate circuit 105. The first input terminal of the prescaler 101 is configured to receive an output frequency signal of the voltage controlled oscillator (VCO output high frequency signal). The automatic correction counter 102 is connected to the output of the prescaler 101. The programmable counter 103 is connected with the output end of the prescaler 101. The input end of the pulse throughput counter 104 is connected with the output end of the prescaler 101 and the output end of the programmable counter. A first input of the gate 105 is connected to the output of the pulse throughput counter 104, and an output of the gate 105 is connected to a second input of the pre-divider. A second input of the gate circuit 105 is used for inputting an automatic frequency correction enable signal.

Referring to fig. 2, the prescaler 101 may be an N/(N +1) dual-mode prescaler 101. The prescaler 101 may have two modes of operation, i.e., a divide-by-N mode and a divide-by-N +1 mode. The specific mode can be determined by the control signal inputted from the second input terminal of the prescaler 101. The prescaler 101 may prescale the high frequency VCO signal. The working frequency of the subsequent counting and frequency dividing module is reduced to save power consumption.

The automatic correction counter 102 may be a VCO frequency sub-band automatic correction counter 102(AFC counter). The automatic correction counter 102 may have a function of automatically counting the output signal of the prescaler 101. The programmable counter 103(P counter) also has a counting and frequency dividing function for the output signal of the prescaler 101. The output of the programmable counter 103 may also output a divided clock signal (Ndiv _ out). The pulse throughput counter 104 (swallows counter) may count the signal output by the prescaler 101 according to a preset count value. After the counting is finished, the pulse throughput counter 104 stops counting, and may output a control signal (MOD _ scnt) to the gate circuit 105. The divided clock signal output by the output terminal of the programmable counter 103 can control the pulse throughput counter 104 to reload the preset divided value to restart counting.

A first input of the gate 105 is connected to an output of the pulse throughput counter 104. The control signal output by the output of the pulse throughput counter 104 can therefore be applied to the gate circuit 105. A second input of the gate circuit 105 is used for inputting an automatic frequency correction enable signal. The afc enable signal may therefore act on the gate circuit 105. The gate circuit 105 has different control logics under the combined action of the control signal and the afc enable signal, and outputs different signals. The output end of the gate circuit 105 is connected to the second input end of the prescaler 101. The prescaler 101 operates in different modes under control of the signal output by the gate circuit 105. For example, the prescaler 101 can be switched between a divide-by-N mode and a divide-by-N +1 mode.

The frequency dividing circuit 10 provided by the embodiment of the present application includes a prescaler 101, an automatic correction counter 102, a programmable counter 103, a pulse throughput counter 104, and a gate circuit 105. The first input terminal of the prescaler 101 is configured to receive an output frequency signal of the voltage controlled oscillator. The automatic correction counter 102 is connected to the output of the prescaler 101. The programmable counter 103 is connected with the output end of the prescaler 101. The input terminal of the pulse throughput counter 104 is connected to the output terminal of the prescaler 101 and the output terminal of the programmable counter 103. A first input of the gate 105 is connected to the output of the pulse throughput counter 104, and an output of the gate 105 is connected to a second input of the pre-divider. A second input of the gate circuit 105 is used for inputting an automatic frequency correction enable signal. The signals output by the prescaler 101 are respectively sent to the automatic correction counter 102, the programmable counter 103 and the pulse throughput counter 104. After the first input end of the prescaler 101 receives the output frequency signal of the voltage controlled oscillator, the prescaler 101 prescales the output frequency signal of the voltage controlled oscillator. Therefore, the working frequency of the automatic correction counter 102 and the programmable counter 103 can be reduced, and the power consumption of the chip can be reduced.

In the stage of automatically correcting the frequency sub-band of the voltage-controlled oscillator, the automatic correction counter 102 counts the signals output by the prescaler 101, and outputs n-bit count values to be sent to the digital baseband for judgment so as to select a proper frequency sub-band of the VCO.

In the phase of locking the phase-locked loop, the programmable counter 103 counts the signals output by the prescaler 101 according to a preset count value. And outputting the final frequency division clock when the counting is finished. At the same time, the programmable counter 103 may send the pulse throughput counter 104 as a loading signal for loading a preset count value of the pulse throughput counter 104. The pulse throughput counter 104 counts the signals output by the prescaler 101 according to a preset count value. After the counting is finished, the pulse throughput counter 104 stops counting and outputs a control signal. The pulse throughput counter 104 may count down and divide by a new divide-down preset value triggered by the loading signal. The automatic frequency correction enable signal input by the second input end of the gate circuit 105 and the control signal output by the pulse throughput counter 104 control the prescaler 101 through the gate circuit 105 to realize the dual-mode prescaler function. Therefore, the frequency dividing circuit 10 can realize that the prescaler 101 operates in only one frequency dividing mode in the VCO frequency subband automatic correction frequency dividing stage, and the programmable counter 103 and the pulse throughput counter 104 do not operate. In the phase-locked loop locking stage, the prescaler 101, the programmable counter 103 and the pulse throughput counter 104 in the frequency dividing circuit 10 integrally form the function of a phase-locked loop feedback frequency divider, so that the use of devices is reduced, the chip space is saved, and the energy consumption is saved.

In one embodiment, the prescaler 101 is a divide-by-N/(N +1) dual-modulus prescaler 101. Therefore, during the vco frequency subband automatic correction phase, the prescaler 101 can operate in the fixed divide-by-N mode. The prescaler 101 divides the output frequency signal of the voltage controlled oscillator by N to a low frequency. Therefore, the working frequency of the automatic correction counter 102 and the programmable counter 103 can be reduced, and the power consumption of the chip can be reduced. The automatic correction counter 102 counts the divided signal of the output frequency signal of the voltage-controlled oscillator within a certain time period, outputs a count value of N bits to the digital baseband for judgment, and selects a proper VCO frequency sub-band.

It is understood that whether the dividing ratio of the dual-mode N/(N +1) divider is N or N +1 is controlled by the signal input from the gate circuit 105 to the second input terminal of the prescaler 101, and the high and low of the signal input from the second input terminal of the prescaler 101 controls the dual-mode dividing ratio to be in the divide-by-N or divide-by-N +1 mode, respectively.

Referring to fig. 3, in one embodiment, the gate circuit 105 is a two-input and circuit 105. The output signal MOD _ pres of the gate circuit 105 is MOD _ sctt when the output frequency signal AFC _ EN of the voltage controlled oscillator is 1. Wherein MOD _ scnt is the control signal output by the pulse throughput counter 104. When the output frequency signal AFC _ EN of the voltage-controlled oscillator is 0, the output signal MOD _ pres of the gate circuit 105 is 0. The two-input and gate circuit may include a logic and circuit and an inverter. And the input end of the inverter is the second input end of the two-input AND circuit. The automatic frequency correction enabling signal is input to the two-input AND gate circuit through the inverter.

It is to be understood that the output frequency signal AFC _ EN of the voltage-controlled oscillator may correspond to a high level, and the output frequency signal AFC _ EN of the voltage-controlled oscillator may correspond to a low level. When the prescaler 101 is an N/(N +1) prescaler 101, the N division can be set as required by controlling the N division through a high level or controlling the N division through a low level.

Referring to fig. 3, in one embodiment, the prescaler 101 operates in a divide-by-N mode when the output signal MOD _ pres of the gate circuit 105 is equal to 0, and the prescaler 101 operates in a divide-by- (N +1) mode when the output signal MOD _ pres of the gate circuit 105 is equal to 1. When the AFC _ EN signal is 1, the output signal MOD _ pres of the gate circuit 105 is 0, that is, the prescaler 101 operates in the divide-by-N mode. At this time, the control signal MOD _ sctt output by the pulse throughput counter 104 is masked. The purpose of saving power consumption can be achieved at this time.

The automatic correction counter 102 counts the low frequency signal obtained by dividing the output frequency signal of the voltage controlled oscillator by N. And after a period of time, sending the counting result into a digital baseband to judge and select a proper VCO frequency sub-band, wherein the phase is an automatic correction phase of the VCO frequency sub-band.

When the AFC _ EN signal is 0, the MOD _ pres signal is the control signal MOD _ sctt output by the pulse throughput counter 104. The frequency dividing ratio of the prescaler 101 is controlled by the automatic frequency correction enable signal MOD _ pres, i.e., the control signal MOD _ sctt output by the pulse throughput counter 104. When the control signal MOD _ scnt output by the pulse throughput counter 104 is equal to 1, the prescaler 101 divides the frequency by (N + 1). When the control signal MOD _ sctn output by the pulse throughput counter 104 is equal to 0, the prescaler 101 divides the frequency by N. In cooperation with the programmable counter 103 and the pulse throughput counter 104, the output of the programmable counter 103 outputs a frequency-divided clock signal Ndiv _ out whose output frequency is divided by the output frequency signal of the vco (NP + S). Namely, the prescaler 101, the pulse throughput counter 104, and the programmable counter 103 cooperate at this time. The auto-calibration counter 102 is not operated at this time to save power consumption.

Therefore, the frequency dividing circuit 10 can be multiplexed with the dual-mode prescaler 101 equivalent to a VCO frequency subband autocorrecting frequency divider to save chip area and power consumption. The frequency dividing circuit 10 can avoid the VCO frequency subband automatic correction counter 102 counting the output frequency signal of the VCO directly, and can also avoid the need of a separate frequency divider for dividing the output frequency signal of the VCO by N and then sending the divided output frequency signal to the VCO frequency subband automatic correction counter 102 for counting. The former works under the high-frequency signal of upper GHz, and the power consumption is increased. The latter requires a separate divider for dividing by N, increasing chip area.

Referring to fig. 4, in one embodiment, the gate circuit 105 is a two-input or gate circuit 105. At this time, when the output frequency signal AFC _ EN of the voltage-controlled oscillator is 1, the output signal MOD _ pres of the gate circuit 105 is 1. When the output frequency signal AFC _ EN of the voltage-controlled oscillator is 0, the output signal MOD _ pres of the gate circuit 105 is MOD _ sctt. MOD _ scnt is a control signal output by the pulse throughput counter 104. The output frequency signal AFC _ EN of the voltage-controlled oscillator may correspond to a high level, and the output frequency signal AFC _ EN of the voltage-controlled oscillator may correspond to a low level. When the prescaler 101 is an N/(N +1) prescaler 101, the N division can be set as required by controlling the N division through a high level or controlling the N division through a low level.

In this embodiment, the prescaler 101 operates in the divide-by-N mode when the output signal MOD _ pres of the gate circuit 105 is equal to 1, and operates in the divide-by- (N +1) mode when the output signal MOD _ pres of the gate circuit 105 is equal to 0. When the AFC _ EN signal is 1, the control signal MOD _ sctt output by the pulse throughput counter 104 is masked. The output signal MOD _ pres of the gate 105 is constantly equal to 1 and the prescaler 101 operates in divide by N mode. When the AFC _ EN is equal to 0, the output signal MOD _ pres of the gate circuit 105 is equal to the control signal MOD _ scnt output by the pulse throughput counter 104, and the prescaler 101 operates in the N-divided or (N +1) -divided mode according to the control signal MOD _ scnt output by the pulse throughput counter 104. In this case, the prescaler 101 can implement division by (NP + S) in cooperation with the programmable counter 103 and the pulse throughput counter 104.

The embodiment of the application also provides a phase-locked loop circuit. The phase-locked loop circuit includes the frequency dividing circuit 10 according to the above embodiment.

The embodiment of the present application further provides a control method of the frequency-division circuit 10. The frequency dividing circuit 10 is applied to the frequency dividing circuit 10 described in the above embodiment. The control method comprises the following steps:

s10, in the stage of automatically calibrating the frequency sub-band of the voltage controlled oscillator, the automatic frequency calibration enable signal inputted from the second input terminal of the gate circuit 105 controls the divide-by-N/(N +1) dual-mode pre-divider 101 to operate in the divide-by-N mode through the gate circuit 105, and the output frequency signal of the voltage controlled oscillator inputted from the input terminal of the divide-by-N/(N +1) dual-mode pre-divider 101 is down-converted by the divide-by-N/(N +1) dual-mode pre-divider 101 and then inputted to the automatic calibration counter 102 for counting;

s20, in the phase locked loop stage, the automatic frequency calibration enable signal input by the second input end of the gate circuit 105 and the control signal output by the pulse throughput counter 104 control the prescaler 101 through the gate circuit 105 to implement the dual-mode prescaler function.

In S10, the AFC enable signal AFC _ EN may be at a high level. The signal output from the output of the gate circuit 105 to the prescaler 101 is always kept at a high level or a low level. The dual-mode divide-by-N/(N +1) prescaler 101 module always works in a divide-by-N mode. The programmable counter 103 and the pulse throughput counter 104 are not active at this time. The output signal fpres of the output frequency signal of the voltage controlled oscillator after being down-converted by the divide-by-N/(N +1) dual-mode prescaler 101 is input to the automatic correction counter 102 for counting. After the counting is finished, the automatic correction counter 102 sends the counting value of n bits into the digital baseband to judge and select a proper VCO frequency sub-band.

In S20, the AFC _ EN signal may be low during the phase-locked loop locking phase. The signal MOD _ pres output from the output terminal of the gate circuit 105 and the control signal MOD _ scnt output from the pulse throughput counter 104 are the same signals. The prescaler 101 for dividing N/(N +1) is controlled to work in the state of dividing N or dividing (N + 1). The divide-by-N/(N +1) prescaler 101 module works in cooperation with the programmable counter 103 and the pulse throughput counter 104. So that the divided clock signal Ndiv _ out output by the output terminal of the programmable counter 103 is the result of dividing the output frequency signal of the voltage controlled oscillator by (NP + S).

In one embodiment, the S20 includes:

the pulse throughput counter 104 counts the signals output by the output end of the prescaler 101 according to a preset count value;

the pulse throughput counter 104 outputs a control signal to the gate circuit 105 at the end of counting;

the gate circuit 105 enables the pre-divider 101 to implement a dual-mode pre-division function under the control of the control signal and the afc enable signal.

In one embodiment, the S20 further includes:

the programmable counter 103 counts the signals output by the output end of the prescaler 101 according to a preset count value;

the programmable counter outputs a divided clock signal to the pulse throughput counter 104 at the end of its count;

the frequency division clock signal is used as a loading signal for loading a preset counting value of the pulse throughput counter 104, so that the pulse throughput counter 104 starts to count and divide frequency according to a new frequency division preset value after receiving the loading signal.

Specifically, in the phase-locked loop locking stage, the programmable counter 103 counts the signals output by the prescaler 101 according to a preset count value. And outputting the final frequency division clock when the counting is finished. At the same time, the programmable counter 103 may send the pulse throughput counter 104 as a loading signal for loading a preset count value of the pulse throughput counter 104. The pulse throughput counter 104 counts the signals output by the prescaler 101 according to a preset count value. After the counting is finished, the pulse throughput counter 104 stops counting and outputs a control signal. The pulse throughput counter 104 may count down and divide by a new divide-down preset value triggered by the loading signal. The automatic frequency correction enable signal input by the second input end of the gate circuit 105 and the control signal output by the pulse throughput counter 104 control the prescaler 101 through the gate circuit 105 to realize the dual-mode prescaler function. Therefore, the frequency dividing circuit 10 can realize that the prescaler 101 operates in only one frequency dividing mode in the VCO frequency subband automatic correction frequency dividing stage, and the programmable counter 103 and the pulse throughput counter 104 do not operate. In the phase-locked loop locking stage, the prescaler 101, the programmable counter 103 and the pulse throughput counter 104 in the frequency dividing circuit 10 integrally form the function of a phase-locked loop feedback frequency divider, so that the use of devices is reduced, the chip space is saved, and the energy consumption is saved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present patent. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.