阅读说明：本技术 一种提高电阻一致性的低功耗相变存储器写驱动电路 (Low-power-consumption phase change memory write drive circuit for improving resistance consistency ) 是由 张光明 雷宇 陈后鹏 宋志棠 于 2020-12-16 设计创作，主要内容包括：本发明涉及一种提高电阻一致性的低功耗相变存储器写驱动电路,其中,基准产生电路产生基准电压或电流提供给电流镜隔离电路；振荡器产生时钟信号用于时序电路；写信号处理电路判断写使能信号与时钟信号的关系,直接或延时后提供使能信号给脉冲控制电路；电流镜隔离电路在电流镜开关电路控制下给电流源电路提供偏置；脉冲控制电路用来控制电流源电路产生的电流脉冲幅度、电流脉冲持续时间、电流脉冲阶梯数和阶梯时间的控制；电流源电路根据电流镜隔离电路提供的偏置和脉冲控制电路产生的控制信号产生相应的写电流脉冲。本发明可以优化存储器上电后第一次写电流脉冲波形,并尽可能减少功耗。(The invention relates to a low-power-consumption phase change memory write drive circuit for improving resistance consistency, wherein a reference generating circuit generates reference voltage or current to supply to a current mirror isolating circuit; the oscillator generates a clock signal for the sequential circuit; the write signal processing circuit judges the relation between the write enable signal and the clock signal and provides the enable signal to the pulse control circuit directly or after time delay; the current mirror isolation circuit provides bias for the current source circuit under the control of the current mirror switch circuit; the pulse control circuit is used for controlling the current pulse amplitude, the current pulse duration, the current pulse step number and the step time generated by the current source circuit; the current source circuit generates a corresponding write current pulse according to a bias provided by the current mirror isolation circuit and a control signal generated by the pulse control circuit. The invention can optimize the first write current pulse waveform after the memory is electrified and reduce the power consumption as much as possible.)

1. A low-power consumption phase change memory write driving circuit for improving resistance consistency is characterized by comprising: the write circuit comprises an oscillator, a write signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a pulse control circuit and a current source circuit; the oscillator is respectively connected with the write signal processing circuit and the pulse control circuit and is used for generating a clock signal with fixed frequency;

the current mirror switch circuit is connected with the pulse control circuit and is used for controlling the on and off of the current mirror isolation circuit;

the current mirror isolation circuit generates a current source bias voltage VWB to the current source circuit;

the write signal processing circuit is respectively connected with the oscillator and the pulse control circuit and is used for comparing an externally input write enable signal WE _ with a clock signal generated by the oscillator and generating an enable signal WEP _ according to a comparison result to be supplied to the pulse control circuit so as to ensure the pre-charging time of the current mirror isolation circuit;

the pulse control circuit is triggered by the enable signal WEP _ and utilizes a clock signal generated by the oscillator and a logic circuit to generate a control signal to control the opening and the closing of different branches in the current source circuit;

the current source circuit generates a write current pulse according to a bias voltage VWB provided by the current mirror isolation circuit and a control signal provided by the pulse control circuit.

2. The write driving circuit for the phase change memory with low power consumption and improved resistance consistency according to claim 1, wherein the current mirror switching circuit controls the current mirror isolation circuit to be turned on and off by using a write enable signal WE _ in a first write operation after the memory is powered on; and during subsequent writing operation, the write pulse enabling WPLS output by the pulse control circuit is used for controlling the current mirror isolation circuit to be switched on and switched off.

3. The write driving circuit of the phase change memory with low power consumption for improving the consistency of resistance according to claim 1, wherein the write signal processing circuit compares the write enable signal WE _ with the clock signal when a first write enable signal WE _ input from outside comes after the memory is powered on; if the write enable signal WE _ falls, the clock signal is at low level, and the write enable signal WE _ is delayed to generate an enable signal WEP _ to the pulse control circuit; if the CLK is at high level when WE _ falling edge arrives, the write enable signal WE _ is taken as the enable signal WEP _.

4. The write driving circuit for improving resistance consistency of a phase change memory with low power consumption as claimed in claim 1, wherein the current mirror isolation circuit is connected to a reference generating circuit, the reference generating circuit is used for generating a reference signal, and the current mirror isolation circuit generates a current source bias voltage VWB according to the reference signal to reduce the influence of charge feed-through caused by control switches of different branches in the current source circuit on the bias voltage VWB.

5. The write driving circuit for improving the phase change memory with low power consumption of the resistance consistency according to claim 1, wherein the write signal processing circuit is a circuit formed by a logic circuit, a transmission gate, a flip-flop, a latch or a register.

6. The write driving circuit for the phase change memory with low power consumption and improved resistance consistency of claim 1, wherein the current mirror switch circuit is a circuit formed by a logic circuit, a transmission gate, a trigger, a latch or a register.

7. The write driving circuit of the phase change memory with low power consumption for improving the resistance consistency according to claim 1, wherein the pulse control circuit comprises a counter circuit, a comparator circuit, a frequency divider circuit and a logic trimming circuit; the counter circuit is used for calculating the number of rising edges or falling edges of clock signals, and the comparator is used for comparing the output of the counter with a set pulse time length trimming signal and determining the opening time lengths of control signals of different branches in the current source circuit; the frequency divider circuit is used for generating a plurality of clock signals with different frequencies to adjust the current pulse step time; and the logic trimming circuit determines the opening number of the control signals of different branches in the current source circuit according to the set pulse height trimming signal.

8. The write driving circuit of the phase change memory with low power consumption for improving the consistency of resistance according to claim 1, wherein the pulse control circuit provides a write pulse enable signal WPLS to the write signal processing circuit and the current mirror switch circuit simultaneously, so that the write signal processing circuit and the current mirror switch circuit perform the write enable signal WE _ delay only in the first write operation after the memory is powered on and control the switch of the current mirror isolation circuit by using the write enable signal WE _ and the write enable signal WE _ is not delayed in the subsequent write operation, and the write pulse enable signal WPLS controls the switch of the current mirror isolation circuit.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption phase change memory write driving circuit for improving resistance consistency.

Background

The core of the writing drive circuit and the system of the phase change memory is that a drive current generating circuit generates drive current to be input into a phase change unit selected by an address decoding circuit, and the phase change unit is converted between a crystalline state and an amorphous state to store 0 and 1. The prior art mainly focuses on controlling the amplitude, duration, number of current pulse steps and step time of a current pulse signal; or the magnitude of the write current of the memory is modified, which does not solve the problem that the rising edge of the first write operation is slow due to the fact that the bias voltage of the current source circuit is not precharged when the memory is powered on and is in the first write operation, and write consistency is poor.

Disclosure of Invention

The invention aims to provide a low-power-consumption phase change memory write driving circuit for improving the resistance consistency, which optimizes the first write current pulse waveform after the memory is electrified and reduces the power consumption as much as possible.

The technical scheme adopted by the invention for solving the technical problems is as follows: the write driving circuit of the low-power-consumption phase change memory for improving the resistance consistency comprises: the write circuit comprises an oscillator, a write signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a pulse control circuit and a current source circuit;

the oscillator is respectively connected with the write signal processing circuit and the pulse control circuit and is used for generating a clock signal with fixed frequency;

the current mirror switch circuit is connected with the pulse control circuit and is used for controlling the on and off of the current mirror isolation circuit;

the current mirror isolation circuit generates a current source bias voltage VWB to the current source circuit;

the write signal processing circuit is respectively connected with the oscillator and the pulse control circuit and is used for comparing an externally input write enable signal WE _ with a clock signal generated by the oscillator and generating an enable signal WEP _ according to a comparison result to be supplied to the pulse control circuit so as to ensure the pre-charging time of the current mirror isolation circuit;

the pulse control circuit is triggered by the enable signal WEP _ and utilizes a clock signal generated by the oscillator and a logic circuit to generate a control signal to control the opening and the closing of different branches in the current source circuit;

the current source circuit generates a write current pulse according to a bias voltage VWB provided by the current mirror isolation circuit and a control signal provided by the pulse control circuit.

When the current mirror switch circuit is in first write operation after the memory is electrified, a write enable signal WE _ is used for controlling the current mirror isolation circuit to be switched on and switched off; and during subsequent writing operation, the write pulse enabling WPLS output by the pulse control circuit is used for controlling the current mirror isolation circuit to be switched on and switched off.

When a first write enable signal WE _ input from the outside comes after the memory is electrified, the write signal processing circuit compares the write enable signal WE _ with a clock signal; if the write enable signal WE _ falls, the clock signal is at low level, and the write enable signal WE _ is delayed to generate an enable signal WEP _ to the pulse control circuit; if the CLK is at high level when WE _ falling edge arrives, the write enable signal WE _ is taken as the enable signal WEP _.

The current mirror isolation circuit is connected with a reference generation circuit, the reference generation circuit is used for generating a reference signal, and the current mirror isolation circuit generates a current source bias voltage VWB according to the reference signal so as to reduce the influence of charge feed-through caused by control switches of different branches in the current source circuit on the bias voltage VWB.

The write signal processing circuit is a circuit constituted by a logic circuit, a transfer gate, a flip-flop, a latch, or a register.

The current mirror switch circuit is a circuit formed by a logic circuit, a transmission gate, a trigger, a latch or a register.

The pulse control circuit comprises a counter circuit, a comparator circuit, a frequency divider circuit and a logic trimming circuit; the counter circuit is used for calculating the number of rising edges or falling edges of clock signals, and the comparator is used for comparing the output of the counter with a set pulse time length trimming signal and determining the opening time lengths of control signals of different branches in the current source circuit; the frequency divider circuit is used for generating a plurality of clock signals with different frequencies to adjust the current pulse step time; and the logic trimming circuit determines the opening number of the control signals of different branches in the current source circuit according to the set pulse height trimming signal.

The pulse control circuit provides a write pulse enabling signal WPLS to the write signal processing circuit and the current mirror switch circuit at the same time, so that the write signal processing circuit and the current mirror switch circuit only perform write enabling signal WE _ time delay for the first write operation after the memory is electrified and control the switch of the current mirror isolation circuit by using the write enabling signal WE _ time delay, the write enabling signal WE _ time delay is not performed in the subsequent write operation, and the write pulse enabling signal WPLS controls the switch of the current mirror isolation circuit.

Drawings

FIG. 1 is a block diagram of the architecture of an embodiment of the present invention;

FIG. 2 is a circuit diagram of a write signal processing circuit in an embodiment of the invention;

FIG. 3 is a circuit diagram of a current mirror switching circuit in an embodiment of the present invention;

FIG. 4 is a timing diagram of a prior art write circuit with WPLS controlled current mirror isolation circuit switches;

FIG. 5 is a timing diagram of WE _ control of the current mirror isolation circuit switch;

FIG. 6 is a timing diagram of a first write operation of a current mirror isolation circuit switch after power up of a memory according to an embodiment of the present invention;

FIG. 7 is a timing diagram of the first two write operations of the current mirror isolation circuit switch after power up of the memory according to an embodiment of the present invention;

FIG. 8 is a graph of the simulation results of the average power consumption of the current mirror isolation circuit switch controlled by WE _ during a write operation;

FIG. 9 is a graph of the simulation results of the average power consumption during a write operation according to the present invention.

Detailed Description

The embodiment of the invention relates to a low-power-consumption phase change memory write driving circuit for improving resistance consistency, as shown in fig. 1, comprising: a write signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a reference generation circuit, an oscillator, a current source circuit, and a pulse control circuit. The reference generating circuit is connected with the current mirror isolating circuit, the oscillator is respectively connected with the write signal processing circuit and the pulse control circuit, the current mirror isolating circuit is connected with the current source circuit, and the pulse control circuit is respectively connected with the write signal processing circuit, the current mirror switching circuit and the current source circuit. In the writing operation process, the current source circuit outputs the generated current pulse or voltage pulse to the phase change unit selected by the decoding control circuit.

The oscillator is used for generating a clock signal CLK with a fixed frequency.

The reference generating circuit is used for generating a reference voltage or current which is irrelevant to parameters such as power supply, process, temperature and the like.

The write signal processing circuit is used for comparing a write enable signal WE _ input from the outside with a clock signal CLK generated by the oscillator, generating an enable signal WEP _ according to a comparison result and providing the enable signal WEP _ to the pulse control circuit, so that the pre-charging time of the current mirror isolation circuit is ensured, and the first write current pulse waveform after the memory is electrified is optimized.

In this embodiment, when a first write enable signal WE _ input from the outside comes after the memory is powered on, the write signal processing circuit compares the write enable signal WE _ with the clock signal CLK; if the write enable signal WE _ falls, the clock signal CLK is at a low level, that is, the interval time between the write enable signal WE _ fall and the upcoming rising edge of the clock signal CLK is short, so that the time requirement of the current mirror isolation circuit for precharging the bias voltage VWB during the first write operation after the memory is electrified cannot be met, and the write signal processing circuit delays the write enable signal WE _ and then generates an enable signal WEP _ to the pulse control circuit; if the falling edge of the write enable signal WE _ arrives, the clock signal CLK is at a high level, that is, the interval between the falling edge of the write enable signal WE _ and the rising edge of the upcoming clock signal CLK is long, which can meet the time requirement of the current mirror isolation circuit for precharging the bias voltage VWB during the first write operation after the memory is powered on, or the second and subsequent write operations after the memory is powered on, the write signal processing circuit does not perform the delay operation, so that the enable signal WEP _ is the same as the write enable signal WE _ s.

The write signal processing circuit is a circuit constituted by a logic circuit, a transfer gate, a flip-flop, a latch, or a register. Fig. 2 is a write signal processing circuit according to this embodiment, in which POR is a power-on reset signal, and WENE is a write enable signal WE _ falling edge detection signal.

The pulse control circuit is triggered by an enable signal WEP _ provided by the write signal processing circuit, and utilizes a clock signal CLK generated by the oscillator and the logic circuit to generate control signals S <0>, S <1>, … … and S < n >, so as to control the opening and closing of different branches of the current source circuit and realize the control of the current pulse amplitude, the current pulse duration, the current pulse step number and the descending step time.

The pulse control circuit of the present embodiment includes a counter circuit, a comparator circuit, a frequency divider circuit, and a logic trimming circuit. The counter calculates the number of rising edges or falling edges of clock signals, the output of the comparator compares the output of the counter with a set pulse time length trimming signal to determine the opening time lengths of control signals S <0>, S <1>, … … and S < n >, the frequency divider generates a plurality of clock signals with different frequencies to trim the current pulse step time, and the logic trimming circuit determines the opening numbers of the control signals S <0>, S <1>, … … and S < n > according to the set pulse height trimming signal, thereby realizing the control of different current pulse amplitudes, current pulse duration, current pulse step numbers and falling step time.

The pulse control circuit provides a write pulse enabling signal WPLS to the write signal processing circuit and the current mirror switch circuit, so that the write signal enabling circuit and the current mirror switch circuit only perform write enabling signal WE _ time delay for the first write operation after the memory is electrified and control the switch of the current mirror isolation circuit by using WE _ time delay, the write enabling signal WE _ time delay is not performed for the subsequent write operation, the write pulse enabling signal WPLS controls the switch of the current mirror, and the power consumption is reduced as much as possible while the waveform of the first write current pulse after the memory is electrified is optimized.

The current mirror switch circuit is used for controlling the on and off of the current mirror isolation circuit. In this embodiment, when the current mirror switching circuit performs a first write operation after the memory is powered on, the current mirror switching circuit controls the switch of the current mirror isolation circuit with a write enable signal WE _ and controls the switch of the current mirror isolation circuit with a write pulse enable WPLS output by the pulse control circuit for a subsequent write operation. Fig. 3 is a circuit diagram of a current mirror switching circuit according to this embodiment.

The current mirror isolation circuit is used for generating a current source bias voltage VWB according to the reference provided by the reference generating circuit so as to remarkably reduce the influence of charge feed-through caused by S <0>, S <1>, … … and S < n > switches on the bias voltage VWB.

The current source circuit generates corresponding write current pulses according to a bias voltage VWB provided by the current mirror isolation circuit and control signals S <0>, S <1>, … … and S < n > provided by the pulse control circuit, and generates voltage initialization pulses under the control of a VRST signal.

As shown in fig. 4, in the conventional write circuit, WPLS controls a current mirror isolation circuit switch, and after the memory is powered on, the current flowing through the phase change cell in the first write operation rises slowly, resulting in poor write consistency. As shown in fig. 5, when WE _ control the current mirror isolation circuit switch and WE _ falling edge is closer to the rising edge of CLK, the current flowing through the phase change cell in the first write operation after the memory is powered on still rises slowly, resulting in poor write consistency.

In the current mirror isolation circuit switch of the embodiment, after the memory is powered on, the first write operation is controlled by WE _ and the relation between WE _ and CLK is judged, as shown in FIG. 6, if WE _ falling edge is closer to CLK rising edge, WEP _ is generated after delay and is provided for a pulse control circuit, so that the pre-charging time is ensured, and the first write current pulse rises faster after the power on; and the subsequent write operation is controlled by WPLS, so that compared with WE _ control, the conduction time of the current mirror isolation circuit is shortened, and the power consumption is reduced. As shown in FIG. 7, in this embodiment, the first write current rises quickly after power-up, and the phase change cell has better write uniformity.

FIG. 8 is the average power consumption of the current mirror isolation circuit switch controlled by WE-during a write operation; fig. 9 is average power consumption at the time of write operation in the present embodiment. After comparison, the average power consumption of the embodiment in the write operation is significantly lower than that of the WE _ controlled current mirror isolation circuit switch in the write operation.

It should be noted that the rising edge, the falling edge, the high level and the low level in the present embodiment are only for convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application.