阅读说明：本技术 氮化镓器件和集成电路的栅极驱动电路及电压调节器 (Gallium nitride device, gate drive circuit of integrated circuit and voltage regulator ) 是由 李湛明 傅玥 刘雁飞 于 2019-06-27 设计创作，主要内容包括：本发明实施例提供一种氮化镓器件和集成电路的栅极驱动电路及电压调节器,采用氮化镓HEMT技术实现的电压稳定和调压电路能够提供稳定的输出电压,适用于氮化镓功率晶体管栅极驱动器和氮化镓集成电路的低压辅助电源等应用。栅极驱动器和电压调节器模块包括至少一个串联连接在一起的DHEMT和至少两个EHEMTs,以便至少一个DHEMT作为可变电阻工作,并且至少两个EHEMTs作为限制输出的齐纳二极管工作。栅极驱动器和电压调节器模块可以实现作为一个氮化镓集成电路,并且可以在单个芯片上与放大器和功率HEMT等其他组件整体集成,以提供氮化镓HEMT功率模块集成电路。(The embodiment of the invention provides a gallium nitride device, a grid driving circuit of an integrated circuit and a voltage regulator, wherein the voltage stabilizing and regulating circuit realized by adopting a gallium nitride HEMT technology can provide stable output voltage, and is suitable for application of a gallium nitride power transistor grid driver, a low-voltage auxiliary power supply of the gallium nitride integrated circuit and the like. The gate driver and voltage regulator module includes at least one DHEMT and at least two EHEMTs connected together in series such that at least one DHEMT operates as a variable resistor and at least two EHEMTs operate as output limiting Zener diodes. The gate driver and voltage regulator module may be implemented as one gallium nitride integrated circuit and may be monolithically integrated with other components, such as the amplifier and power HEMT, on a single chip to provide a gallium nitride HEMT power module integrated circuit.)

A gate drive circuit of a gallium nitride (GaN) power High Electron Mobility Transistor (HEMT), comprising:

an input point for receiving an input voltage, an output point for outputting a voltage for driving the power HEMT;

a series circuit comprising at least one gallium nitride D-mode hemt (dhemt) and at least first and second gallium nitride E-mode hemts (ehemts);

wherein: the drain of the DHEMT is connected to the input point, and the source of the DHEMT is connected to the drain of the first EHEMT and the output point;

the grid electrode of the DHEMT is connected with the source electrode of the DHEMT;

a source of the first EHEMT is connected to a drain of the second EHEMT;

a gate of the first EHEMT is connected to a drain of the first EHEMT;

a source of the second EHEMT is connected to a circuit common; and the gate of the second EHEMT is connected to the drain of the second EHEMT;

wherein the gate drive circuit is implemented on a gallium nitride Integrated Circuit (IC) or using discrete gallium nitride devices.

A gate drive circuit as claimed in claim 1, wherein the gate drive circuit provides voltage downshifting and overvoltage protection to drive a gallium nitride power HEMT.

A gate drive circuit as claimed in claim 1, wherein the at least one DHEMT operates as a variable resistor and the at least first and second EHEMTs operate as zener diodes that limit the output voltage to about 6V.

A gate drive circuit as claimed in claim 1, wherein the DHEMT, the at least first and second EHEMTs are low voltage devices.

A gate drive circuit as claimed in claim 1, wherein the DHEMT has a different channel length and/or a different channel width than at least the at least first and second EHEMTs.

A gate drive circuit as claimed in claim 1, wherein the DHEMT has at least the same channel length as the at least first and second EHEMTs.

A gate drive circuit as claimed in claim 1, wherein the channel width of the DHEMT is at least 17% to 25% of the smallest channel width of the first and second EHEMTs.

The gate driver circuit of claim 1, wherein at least the first and second EHEMTs have the same channel width, and wherein the ratio of the channel widths of the DHEMT to the EHEMTs is about 1: 4.7.

A gallium nitride (GaN) Integrated Circuit (IC) power module, comprising:

a gate drive circuit according to claim 1; and a power HEMT;

wherein, the gate drive module and the power HEMT are integrally integrated in a die.

The gallium nitride integrated circuit power module of claim 9, wherein:

the power HEMT includes at least a first high-voltage HEMT and a second high-voltage HEMT connected together in parallel;

the first high-voltage HEMT is smaller than the second high-voltage HEMT so that a region of the die is not occupied by the power HEMT; and is

The gate drive module is disposed in a mold area not occupied by the power HEMT.

A method for implementing a gate drive circuit for a gallium nitride power HEMT, comprising:

providing an input point receiving an input voltage and an output point outputting a voltage to drive the power HEMT;

connecting at least one gallium nitride DHEMT and at least a first gallium nitride EHEMT and a second gallium nitride EHEMT together in series; wherein:

the drain of the DHEMT is connected to the input point, and the source of the DHEMT is connected to the drain of the first EHEMT and the output point;

the grid electrode of the DHEMT is connected with the source electrode of the DHEMT;

a source of the first EHEMT is connected to a drain of the second EHEMT;

a gate of the first EHEMT is connected to a drain of the first EHEMT;

a source of the second EHEMT is connected to a circuit common; and is

A gate of the second EHEMT is connected to a drain of the second EHEMT; and the gate drive circuit is implemented on a gallium nitride integrated circuit.

The method of claim 11, wherein the gate drive circuit provides voltage downshifting and overvoltage protection to drive the gallium nitride power HEMT.

The method of claim 11, comprising:

operating the DHEMT as a variable resistor, and operating the at least first and second EHEMTs as a Zener diode that limits the output voltage to about 6V.

The method of claim 11, wherein the DHEMT and the at least first and second EHEMTs are low-voltage devices.

The method of claim 11, wherein the DHEMT and the at least first and second EHEMTs have different channel lengths and/or different channel widths.

The method of claim 11, wherein the DHEMT and the at least first and second EHEMTs have the same channel length.

The method of claim 11, wherein the channel width of the DHEMT is 17% to 25% of the smallest channel width of the at least first and second EHEMTs.

The method of claim 11, wherein the channel widths of the at least first and second EHEMTs are the same, and wherein the DHEMT to EHEMTs ratio is about 1: 4.7.

The method of claim 11, comprising integrally integrating the gate driver with the power HEMT in a single gallium nitride die.

The method of claim 19, wherein:

the power HEMT is realized by connecting at least a first high-voltage HEMT and a second high-voltage HEMT in parallel;

wherein the first high-voltage HEMT is smaller than the second high-voltage HEMT such that a region of the die is not occupied by the power HEMT; and the gate drive module is disposed in a mold area not occupied by the power HEMT.

A voltage regulator circuit for a gallium nitride (GaN) Integrated Circuit (IC), comprising:

an input point for receiving an input voltage and an output point for outputting a voltage for driving the GaN integrated circuit;

a series circuit comprising at least one gallium nitride D-mode HEMT (dhemt) having a gate-to-source connection and at least first to fourth gallium nitride E-mode HEMTs (ehemt), each HEMT having a drain-to-gate connection;

an output EHEMT having a drain connected to the input point and a source connected to the output point;

wherein:

the drain of the DHEMT is connected to the input point, and the source of the DHEMT is connected to the drain of the first EHEMT and the gate of the output EHEMT;

the source of the first EHEMT is connected to the drain of the second EHEMT,

the source of the second EHEMT is connected to the drain of the third EHEMT,

the source of the third EHEMT is connected to the drain of the fourth EHEMT,

a source of the fourth EHEMT is connected to circuit common;

wherein the voltage regulator circuit is implemented on a gallium nitride integrated circuit or using a discrete gallium nitride device.

The voltage regulator circuit according to claim 21, wherein the voltage regulator circuit provides a reference voltage output.

The voltage regulator circuit of claim 21, wherein the voltage regulator circuit is configured to drive a low voltage gallium nitride circuit.

The voltage regulator circuit according to claim 21, wherein the at least one DHEMT operates as a variable resistor and the at least first to fourth EHEMTs operate as zener diodes that limit the output voltage to about 6V.

The voltage regulator circuit of claim 21, wherein the DHEMT and the at least first through fourth EHEMTs are low voltage devices.

The voltage regulator circuit of claim 21, wherein the DHEMT and at least the first to fourth EHEMTs have different channel lengths and/or different channel widths.

The voltage regulator circuit of claim 21, wherein a channel width of the DHEMT is approximately 3.5% of a smallest channel width of the at least first through fourth EHEMTs.

The voltage regulator circuit of claim 21, wherein the channel widths of the at least first through fourth EHEMTs are the same.

A gallium nitride (GaN) Integrated Circuit (IC) power module, comprising:

the voltage regulator circuit of claim 1;

an amplifier; and a power HEMT;

wherein the voltage regulator circuit, the amplifier and the power HEMT are integrally integrated in one die.

The gan integrated circuit power module of claim 29, wherein:

the power HEMT comprises at least a first high-voltage HEMT and a second high-voltage HEMT which are connected together in parallel;

the first high-voltage HEMT is smaller than the second high-voltage HEMT so that one region of the die is not occupied by the power HEMT; and is

The voltage regulator circuit and amplifier are located in the die area not occupied by the power HEMT.

A method for implementing a gallium nitride integrated circuit voltage regulator circuit, comprising:

providing an input point for receiving an input voltage and an output point for outputting a driving voltage of the gallium nitride integrated circuit;

connecting at least one gallium nitride D-mode HEMT (DHEMT) in series with the gate-to-source connection, wherein at least one gallium nitride E-mode HEMT (EHEMT) is connected in series with the drain-to-gate connection;

connecting the drain of the output EHEMT to an input point and the source of the output HEMT to an output point;

wherein:

the drain of the DHEMT is connected to the input point, and the source of the DHEMT is connected to the drain of the first EHEMT and the gate of the output EHEMT;

the source of the first EHEMT is connected to the drain of the second EHEMT,

the source of the second EHEMT is connected to the drain of the third EHEMT,

the source of the third EHEMT is connected to the drain of the fourth EHEMT,

a source of the fourth EHEMT is connected to circuit common;

the voltage regulator circuit is implemented on a gallium nitride integrated circuit or using discrete gallium nitride devices.

The method of claim 31, wherein the voltage regulator circuit provides a reference voltage output.

The method of claim 31, wherein the voltage regulator circuit is configured to drive a low voltage gallium nitride circuit.

The method of claim 31, wherein the at least one DHEMT operates as a variable resistor and the at least first through fourth EHEMTs operate as zener diodes that limit the output voltage to about 6V.

The method of claim 31, wherein the DHEMT and at least the first to fourth EHEMTs are low-voltage devices.

The method of claim 31, wherein the DHEMT and at least the first to fourth EHEMTs have different channel lengths and/or different channel widths.

The method of claim 31, wherein the channel width of the DHEMT is about 3.5% of the smallest channel width of the at least first to fourth EHEMTs.

The method of claim 31, wherein the channel widths of the at least first through fourth EHEMTs are the same.

The method of claim 31, comprising integrally integrating the voltage regulator circuit with the amplifier and the power HEMT;

wherein the voltage regulator circuit, the amplifier and the power HEMT are integrally integrated in one die.

The method according to claim 39, characterized in that it comprises:

a power HEMT that implements at least a first EHEMT and a second high-voltage HEMT in parallel;

wherein the first high-voltage HEMT is smaller than the second high-voltage HEMT, so that a region of the die is not occupied by the power HEMT; and the voltage regulator circuit and amplifier are located in the die area not occupied by the power HEMT.