阅读说明：本技术 一种时钟网络结构、一种时钟信号传递方法 (Clock network structure and clock signal transmission method ) 是由 张陈兰 黄平 何梓明 杨洋 陈宏� 于 2020-12-18 设计创作，主要内容包括：本发明公开一种时钟网络结构及一种时钟信号传递方法,其中时钟网络结构包括分频电路、时钟树和若干个倍频电路,其中时钟树分别与分频电路和各倍频电路相连；所述分频电路,用于接收来自时钟源的初始时钟信号,并对所述初始时钟信号进行分频,将所得分频信号发送至时钟树；所述倍频电路,用于接收时钟树输出的输出信号,并对所述输出信号进行倍频,输出倍频信号,所述倍频信号与所述初始时钟信号的频率一致。本发明通过在时钟树根部添加一个分频电路,降低时钟树的时钟源头的时钟频率,从而通过降低时钟树工作的时钟频率以减少功耗；然后再通过在时钟树分枝末端添加倍频电路,从而还原时钟频率,保证本发明中时钟网络结构所在的芯片的正常工作。(The invention discloses a clock network structure and a clock signal transmission method, wherein the clock network structure comprises a frequency division circuit, a clock tree and a plurality of frequency multiplication circuits, wherein the clock tree is respectively connected with the frequency division circuit and each frequency multiplication circuit; the frequency division circuit is used for receiving an initial clock signal from a clock source, dividing the frequency of the initial clock signal and sending the obtained frequency division signal to a clock tree; and the frequency doubling circuit is used for receiving the output signal output by the clock tree, doubling the frequency of the output signal and outputting a frequency doubling signal, wherein the frequency of the frequency doubling signal is consistent with that of the initial clock signal. According to the invention, the frequency division circuit is added at the root of the clock tree, so that the clock frequency of the clock source of the clock tree is reduced, and the power consumption is reduced by reducing the clock frequency of the clock tree; and then, a frequency multiplication circuit is added at the tail end of the clock tree branch, so that the clock frequency is restored, and the normal work of a chip where the clock network structure is located is ensured.)

1. A clock network structure is characterized by comprising a frequency dividing circuit, a clock tree and a plurality of frequency multiplying circuits, wherein the clock tree is respectively connected with the frequency dividing circuit and each frequency multiplying circuit;

the frequency division circuit is used for receiving an initial clock signal from a clock source, dividing the frequency of the initial clock signal and sending the obtained frequency division signal to a clock tree;

and the frequency doubling circuit is used for receiving the output signal output by the clock tree, doubling the frequency of the output signal and outputting a frequency doubling signal, wherein the frequency of the frequency doubling signal is consistent with that of the initial clock signal.

2. The clock network structure of claim 1, wherein:

the clock selection circuit is also included;

the clock source comprises a test clock and a functional clock;

the clock selection circuit is respectively connected with the test clock, the functional clock and the frequency division circuit;

the frequency dividing circuit acquires an initial clock signal from the test clock or the functional clock through the clock selection circuit.

3. Clock network structure according to claim 1 or 2, characterized in that:

the frequency division circuit is a two-frequency division circuit, and the frequency multiplication circuit is a two-frequency multiplication circuit.

4. The clock network structure of claim 3, wherein:

the frequency doubling circuit comprises a first pulse generating circuit, a second pulse generating circuit and a pulse integrating circuit, wherein the first pulse generating circuit is respectively connected with the pulse integrating circuit and the clock tree, and the second pulse generating circuit is respectively connected with the pulse integrating circuit and the clock tree;

the first pulse generating circuit is used for generating a first pulse signal with time delay, and the first pulse signal corresponds to the rising edge of the output signal;

the second pulse generating circuit is used for generating a second pulse signal with time delay, and the second pulse signal corresponds to the falling edge of the output signal;

the time delay of the first pulse signal is the same as that of the second pulse signal;

the pulse integration circuit is used for integrating the first pulse signal and the second pulse signal to obtain a corresponding frequency multiplication signal.

5. The clock network structure of claim 4, wherein:

the first pulse generating circuit comprises a first inverter, a first AND gate and a buffer circuit;

the input end of the first inverter is connected with the clock tree through a buffer circuit;

and the first input end of the first AND gate is connected with the output end of the first phase inverter, the second input end of the first AND gate is connected with the input end of the first phase inverter, and the output end of the first AND gate is connected with the pulse integration circuit.

6. The clock network structure of claim 5, wherein:

the second pulse generating circuit comprises a second inverter, a second AND gate and an inverting buffer circuit, and the time delay of the inverting buffer circuit is equal to that of the buffer circuit;

the input end of the second inverter is connected with the clock tree through an inverting buffer circuit;

and the first input end of the second AND gate is connected with the output end of the second phase inverter, the second input end of the second AND gate is connected with the input end of the second phase inverter, and the output end of the second AND gate is connected with the pulse integration circuit.

7. The clock network structure of claim 6, wherein:

the buffer circuit comprises a plurality of buffers which are sequentially connected in series;

the inverting buffer circuit comprises an odd number of inverters which are sequentially connected in series.

8. The clock network structure of claim 7, wherein:

the pulse integration circuit is a two-input OR gate.

9. A clock signal transmission method using the clock network structure of any one of claims 1 to 8, comprising the steps of:

the frequency division circuit receives an initial clock signal from a clock source, divides the frequency of the initial clock signal and transmits a generated frequency division signal to a clock tree;

the clock tree receives the frequency division signal and outputs corresponding output signals to each frequency multiplication circuit;

and the frequency doubling circuit performs frequency doubling processing on the received output signal to obtain a corresponding frequency doubling signal and outputs the frequency doubling signal, wherein the clock frequency of the frequency doubling signal is equal to that of the initial clock signal.

10. The clock signal transfer method of claim 9, wherein:

the clock source comprises a test clock and a functional clock;

the clock selection circuit collects operation data of a user, takes a clock signal generated by a test clock or a functional clock as an initial clock signal based on the operation data, and sends the initial clock signal to the frequency division circuit.

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a clock network structure and a clock signal transmission method based on the clock network structure.

Background

In digital integrated circuit design, a clock is used as a reference for signals that are critical to the functionality and performance of the circuitry. The carrier of the clock signal is a clock tree, the clock tree is a propagation network for describing the clock signal, and the clock signal is transmitted from the clock source to the clock receiving end of the sequential device in a grading way through the clock tree.

The clock network has a large occupancy rate for layout wiring and power consumption resources, and is one of the circuits with the highest flip frequency in the chip. With the continuous expansion of the scale of digital integrated circuits and the continuous progress of the production process of integrated circuits, the requirements on clock frequency are higher and higher, the structure of a clock network is more and more complex, the increase of the scale of the clock network causes a clock signal to draw larger current when being overturned, and the higher the clock frequency is, the smaller the signal conversion time is, the more easily causes noise on a power supply network.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a clock network structure and a clock signal transmission method based on the clock network structure, the clock frequency of the clock tree work is reduced through a frequency division circuit, so that the power consumption of the clock tree is effectively reduced, and then a frequency multiplication circuit is utilized to restore the output signal output by the clock tree, thereby ensuring the normal work of the chip.

In order to solve the technical problem, the invention is solved by the following technical scheme:

a clock network structure comprises a frequency dividing circuit, a clock tree and a plurality of frequency multiplying circuits, wherein the clock tree is respectively connected with the frequency dividing circuit and each frequency multiplying circuit;

the frequency division circuit is used for receiving an initial clock signal from a clock source, dividing the frequency of the initial clock signal and sending the obtained frequency division signal to a clock tree;

and the frequency doubling circuit is used for receiving the output signal output by the clock tree, doubling the frequency of the output signal and outputting a frequency doubling signal, wherein the frequency of the frequency doubling signal is consistent with that of the initial clock signal.

The clock tree transmits clock signals to the registers and the combinational logic driven by the clock tree through the frequency doubling circuit, and the frequency doubling signals have the same clock frequency with the initial clock signals, so that the chips can work normally.

Because the power consumption of the clock tree is larger in the power consumption of the whole chip, the clock frequency of the clock tree is reduced, and therefore the purpose of reducing the power consumption is achieved.

As an implementable embodiment:

the clock selection circuit is also included;

the clock source comprises a test clock and a functional clock;

the clock selection circuit is respectively connected with the test clock, the functional clock and the frequency division circuit;

the frequency dividing circuit acquires an initial clock signal from the test clock or the functional clock through the clock selection circuit.

The clock network structure provided by the application can be suitable for a testability chip by the design of the clock selection circuit.

As an implementable embodiment:

the frequency division circuit is a two-frequency division circuit, and the frequency multiplication circuit is a two-frequency multiplication circuit.

When the frequency division multiple is less than 2, the clock frequency of the clock tree cannot be effectively reduced, and the effect of reducing power consumption cannot be achieved, and when the frequency division multiple is greater than 2, the corresponding frequency multiplication circuit is complex, high in cost and not suitable for a digital integrated circuit.

As an implementable embodiment:

the frequency doubling circuit comprises a first pulse generating circuit, a second pulse generating circuit and a pulse integrating circuit, wherein the first pulse generating circuit is respectively connected with the pulse integrating circuit and the clock tree, and the second pulse generating circuit is respectively connected with the pulse integrating circuit and the clock tree;

the first pulse generating circuit is used for generating a first pulse signal with time delay, and the first pulse signal corresponds to the rising edge of the output signal;

the second pulse generating circuit is used for generating a second pulse signal with time delay, and the second pulse signal corresponds to the falling edge of the output signal;

the time delay of the first pulse signal is the same as that of the second pulse signal;

the pulse integration circuit is used for integrating the first pulse signal and the second pulse signal to obtain a corresponding frequency multiplication signal.

The frequency doubling circuit is a digital circuit, has a simple structure and a small volume compared with the existing frequency doubling circuit which realizes frequency doubling by utilizing an analog circuit, and can be integrated in a chip.

As an implementable embodiment:

the first pulse generating circuit comprises a first inverter, a first AND gate and a buffer circuit;

the input end of the first inverter is connected with the clock tree through a buffer circuit;

and the first input end of the first AND gate is connected with the output end of the first phase inverter, the second input end of the first AND gate is connected with the input end of the first phase inverter, and the output end of the first AND gate is connected with the pulse integration circuit.

The first AND gate is a two-input AND gate, and the delay time of the first inverter can be automatically adjusted according to actual needs, so that the pulse width of the first pulse signal is controlled.

As an implementable embodiment:

the second pulse generating circuit comprises a second inverter, a second AND gate and an inverting buffer circuit, and the time delay of the inverting buffer circuit is equal to that of the buffer circuit;

the input end of the second inverter is connected with the clock tree through an inverting buffer circuit;

and the first input end of the second AND gate is connected with the output end of the second phase inverter, the second input end of the second AND gate is connected with the input end of the second phase inverter, and the output end of the second AND gate is connected with the pulse integration circuit.

The second AND gate is also a two-input AND gate, and the delay time lengths of the first inverter and the second inverter are consistent.

As an implementable embodiment:

the buffer circuit comprises a plurality of buffers which are sequentially connected in series;

the inverting buffer circuit comprises an odd number of inverters which are sequentially connected in series.

Because the signal input by the first input end of the second and gate in the second pulse generating circuit needs to be inverted for even times, the signal input by the second input end needs to be inverted for odd times, and a delay is added in the inverting process, a buffer circuit and an inverting buffer circuit need to be designed to enable the delay of the first pulse signal to be the same as that of the second pulse signal.

As an implementable embodiment:

the pulse integration circuit is a two-input OR gate.

The invention also provides a clock signal transmission method, which adopts the clock network structure, and comprises the following steps:

the frequency division circuit receives an initial clock signal from a clock source, divides the frequency of the initial clock signal and transmits a generated frequency division signal to a clock tree;

the clock tree receives the frequency division signal and outputs corresponding output signals to each frequency multiplication circuit;

and the frequency doubling circuit performs frequency doubling processing on the received output signal to obtain a corresponding frequency doubling signal and outputs the frequency doubling signal, wherein the clock frequency of the frequency doubling signal is equal to that of the initial clock signal.

As an implementable embodiment:

the clock source comprises a test clock and a functional clock;

the clock selection circuit collects operation data of a user, takes a clock signal generated by a test clock or a functional clock as an initial clock signal based on the operation data, and sends the initial clock signal to the frequency division circuit.

Due to the adoption of the technical scheme, the invention has the remarkable technical effects that:

the clock frequency of the clock tree and the register and the combinational logic driven by the clock tree are the same frequency, the power consumption of the clock tree has a larger ratio in the power consumption of the whole chip, the clock frequency of the clock source of the clock tree is reduced by adding a frequency dividing circuit at the root of the clock tree, and thus the clock frequency of the whole clock tree is halved; and then, a frequency multiplication circuit is added at the tail end of the clock tree branch, so that the clock frequency is restored, the clock frequency reaching the register and the logic combination is the same as the clock frequency generated by the clock source, and the normal work of a chip where the clock network structure is located is ensured.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a clock network architecture according to the present invention;

FIG. 2 is a circuit diagram of a frequency doubling circuit according to the present invention;

FIG. 3 is a schematic diagram of the first pulse generating circuit of FIG. 2 generating a first pulse signal;

FIG. 4 is a schematic diagram of the second pulse generating circuit of FIG. 2 generating a second pulse signal;

FIG. 5 is a schematic diagram of the pulse integration circuit of FIG. 2 integrating a frequency-multiplied signal;

fig. 6 is a schematic structural diagram of a clock network structure in embodiment 2.

Detailed Description

The present invention will be described in further detail with reference to examples, which are illustrative of the present invention and are not to be construed as being limited thereto.

Embodiment 1, a clock network structure, which is respectively connected to a clock source and a sequential device, and a clock signal generated by the clock source is transmitted to each sequential device through a clock network result, as shown in fig. 1, the clock network structure includes a frequency dividing circuit 100, a clock tree 200, and a plurality of frequency multiplying circuits 300, where the clock tree 200 is respectively connected to the frequency dividing circuit 100 and each frequency multiplying circuit 300;

the frequency dividing circuit 100 is configured to receive an initial clock signal from a clock source, divide the frequency of the initial clock signal, and send an obtained frequency-divided signal to the clock tree 200;

the frequency doubling circuit 300 is configured to receive an output signal output by the clock tree 200, perform frequency doubling on the output signal, and output a frequency doubled signal, where the frequency doubled signal is used to drive a register and a combinational logic (i.e., a sequential device), and the frequency doubled signal is consistent with the frequency of the initial clock signal.

In the present embodiment, a frequency dividing circuit 100 is added to the root of the clock tree 200 to reduce the clock frequency of the clock source of the clock tree 200, so as to reduce the clock frequency of the whole clock tree 200 by half. Then, the frequency multiplier circuit 300 is added to the end of the branch of the clock tree 200, so as to restore the clock frequency, so that the clock frequency reaching the register and the logic combination is the same as the clock frequency generated by the clock source, thereby ensuring the normal operation of the chip where the clock network structure is located in the embodiment.

As can be seen from the above, in the present embodiment, through the design of the frequency dividing circuit 100 and the frequency multiplying circuit 300, on the premise of ensuring the normal operation of the chip where the clock network structure is located, the clock frequency on the clock tree 200 can be reduced to reduce the power consumption of the clock tree 200, so as to greatly reduce the power consumption of the corresponding chip.

A person skilled in the art can select the frequency dividing circuit 100 and the frequency multiplying circuit 300 with appropriate multiples according to actual needs, the value of the multiple is 2, when the multiple is less than 2, the frequency dividing effect is not good, the purpose of reducing power consumption cannot be achieved, and when the multiple is greater than 2, the corresponding frequency dividing circuit 100 and the corresponding frequency multiplying circuit 300 are complex and are not suitable for the field of integrated circuits.

In the present embodiment, the frequency halving circuit 100 and the frequency doubling circuit 300 are adopted, which is the optimal solution.

Because the conventional frequency doubling circuit 300 is often an analog circuit, and has a complex structure and a large volume, which is difficult to be implemented in a digital integrated circuit, the frequency doubling circuit 300 is further improved in this embodiment:

the frequency doubling circuit 300 comprises a first pulse generating circuit, a second pulse generating circuit and a pulse integrating circuit 330, wherein the first pulse generating circuit is respectively connected with the pulse integrating circuit 330 and the clock tree 200, and the second pulse generating circuit is respectively connected with the pulse integrating circuit 330 and the clock tree 200;

the first pulse generating circuit is used for generating a first pulse signal with time delay, and the first pulse signal corresponds to the rising edge of the output signal;

the second pulse generating circuit is used for generating a second pulse signal with time delay, and the second pulse signal corresponds to the falling edge of the output signal;

the time delay of the first pulse signal is the same as that of the second pulse signal;

the pulse integration circuit 330 is configured to integrate the first pulse signal and the second pulse signal to obtain a corresponding frequency-doubled signal.

In this embodiment, the first pulse generating circuit generates a corresponding high-level pulse based on the detection result by detecting a rising edge of the output signal, and the second pulse generating circuit generates a corresponding high-level pulse based on the detection result by detecting a falling edge of the output signal, and those skilled in the art can set the width of the high-level pulse according to actual needs.

Referring to fig. 2, the first pulse generating circuit includes a first inverter 312, a first and gate 313 and a buffer circuit 311, wherein the first and gate 313 is a two-input and gate;

the input terminal of the first inverter 312 is connected to the clock tree 200 through the buffer circuit 311;

a first input terminal (i.e., terminal a) of the first and gate 313 is connected to the output terminal of the first inverter 312, a second input terminal (i.e., terminal B) is connected to the input terminal of the first inverter 312, and an output terminal (i.e., terminal Z) is connected to the pulse integration circuit 330.

The buffer circuit 311 is configured to adjust the delay of the first pulse signal to be consistent with the delay of the second pulse signal, in this embodiment, the buffer circuit 311 includes m buffers connected in series, m is a positive integer, and a person skilled in the art can set the delay time of each buffer and the number of the buffers according to actual needs.

The signal received by the a terminal of the first and gate 313 is the inverted signal of the output signal after passing through the buffer circuit 311 and the first inverter 312, and the signal is added with the delay of the buffer circuit 311 and the first inverter 312;

the signal received by the terminal B of the first and gate 313 is the output signal after passing through the buffer circuit 311, and the signal is only delayed by the buffer circuit 311;

referring to fig. 3, it can be seen that when the signals received by the a and B terminals of the first and gate 313 are both high level, a high level is output, and the signal input by the a terminal of the first and gate 313 additionally adds the delay time of the first inverter 312, so that the Z terminal of the first and gate 313 outputs a high level pulse, i.e., a first pulse signal, which is additionally delayed by the inverter, after the output signal is a rising edge, and the pulse width of the first pulse signal is determined by the delay of the first inverter 312, and those skilled in the art can adjust the delay of the first inverter 312 according to actual conditions.

Referring to fig. 2, the second pulse generating circuit includes a second inverter 322, a second and gate 323, and an inverting buffer circuit 321, where the delays of the inverting buffer circuit 321 and the buffer circuit 311 are equal, and the second and gate 323 also adopts a two-input and gate;

the input end of the second inverter 322 is connected to the clock tree 200 through an inverting buffer circuit 321;

a first input terminal (i.e., terminal a) of the second and gate 323 is connected to an output terminal of the second inverter 322, a second input terminal (i.e., terminal B) is connected to an input terminal of the second inverter 322, and an output terminal (i.e., terminal Z) is connected to the pulse integration circuit 330.

The inverting buffer circuit 321 is used for inverting and delaying the output signal, and in the embodiment, the time delays of the inverting buffer circuit 321 and the buffer circuit 311 are equal, so that the pulse frequency doubling can be accurately realized after the second pulse signal is integrated with the first pulse signal.

In the embodiment, the inverting buffer circuit 321 includes n inverters connected in series, where n is a positive integer and is an odd number, and a person skilled in the art can set the delay time of each inverter and the number of the inverters according to actual needs.

The signal received by the a terminal of the second and gate 323 is the output signal after passing through the inverting buffer circuit 321 and the second inverter 322, and adds the delay of the inverting buffer circuit 321 and the second inverter 322, where the second inverter 322 is used to restore the inverted signal of the inverting buffer circuit 321;

the signal received by the B terminal of the second and gate 323 is the inverted signal of the output signal after passing through the inverting buffer circuit 321, and the signal is only delayed by the inverting buffer circuit 321;

referring to fig. 4, it can be seen that, when the signals received by the a and B terminals of the second and gate 323 are both high level, a high level is output, and the signal input by the a terminal of the second and gate 323 adds the delay time of the second inverter 322, so that the Z terminal of the second and gate 323 outputs a high level pulse based on the inverter delay after the output signal is a falling edge, that is, the second pulse signal, like the first pulse signal, and the pulse width of the second pulse signal is determined by the delay time of the second inverter 322, and in this embodiment, the delay times of the first inverter 312 and the second inverter 322 are equal.

In this embodiment, the pulse integration circuit 330 employs a two-input or gate, which outputs a high level when any one of the input signals is a high level.

Referring to fig. 2 and 5, the two-input or gate has a first input terminal (i.e., a terminal a) to which the first pulse signal is input, a second input terminal (i.e., a terminal B) to which the second pulse signal is input, and an output terminal (i.e., a terminal Z) to which the frequency-doubled signal is output.

In summary, in the present embodiment, the digital circuit constructed by the inverter, the inverter and the gate circuit is used to realize frequency multiplication of the clock frequency, and compared with the existing frequency multiplier for realizing frequency multiplication based on an analog circuit, the frequency multiplier has a simple structure and is suitable for the field of digital integration.

The clock transmission method based on the clock network structure provided by the embodiment comprises the following steps:

s110, an external clock source generates a clock signal, and the clock signal is used as an initial clock signal;

s120, the frequency dividing circuit 100 receives the initial clock signal, divides the frequency of the initial clock signal, and transmits the generated frequency-divided signal to the clock tree 200.

S130, the clock tree 200 receives the frequency-divided signal and outputs a corresponding output signal to each frequency-doubling circuit 300;

the clock tree 200 has an input terminal and a plurality of output terminals, the output terminals correspond to the frequency doubling circuits 300 one by one, the input terminal inputs the frequency division signal, and the output terminals output the output signal after the hierarchical transmission by the clock tree 200 to the corresponding frequency doubling circuits 300.

The frequency dividing circuit 100 halves the clock frequency of the initial clock signal, and at this time, the whole clock tree 200 works based on the frequency dividing signal, so that the power consumption of the clock tree 200 is greatly reduced due to the lower clock frequency of the frequency dividing signal;

s130, the frequency doubling circuit 300 performs frequency doubling on the received output signal to obtain a corresponding frequency doubled signal, and outputs the frequency doubled signal, where the frequency doubled signal is equal to the clock frequency of the initial clock signal.

In this embodiment, the clock tree 200 drives an external sequential device, e.g., drives an external register, through the frequency multiplier circuit 300.

Because the output signal reaches the corresponding sequential device after the clock frequency is restored by the frequency multiplier circuit 300, the chip on which the output signal is located except the clock tree 200 part, other logics all work under the clock frequency generated by the clock source, and the power consumption of the clock tree 200 accounts for a larger proportion in the power consumption of the whole chip, so that the power consumption of the chip can be effectively reduced on the premise of ensuring the normal work of the chip by designing the clock network structure.

Embodiment 2, and embodiment 1, add the clock selection circuit 400, the others are the same as embodiment 1;

the clock source is connected to the frequency dividing circuit 100 through the clock selecting circuit 400, and the clock source in this embodiment includes a test clock and a functional clock, that is, the clock selecting circuit 400 is connected to the test clock, the functional clock and the frequency dividing circuit 100 respectively;

as shown in fig. 6, the frequency dividing circuit 100 obtains an initial clock signal from the test clock or the functional clock through the clock selection circuit 400.

In this embodiment, the clock network structure provided in this embodiment can be used for a testability chip by designing the clock selection circuit 400; the clock selection circuit 400 collects operation data of a user, takes a clock signal generated by a test clock or a functional clock as an initial clock signal based on the operation data, and transmits the initial clock signal to the frequency dividing circuit 100.

The method comprises the following specific steps:

when the chip normally operates, the clock signal generated by the functional clock is outputted as an initial clock signal through the clock selection circuit 400 and enters the frequency division circuit 100.

As described in embodiment 1, the clock signal generated by the functional clock is converted into a frequency-divided signal with a lower frequency by the frequency dividing circuit 100 to reduce the power consumption of the clock tree 200, and the frequency of the output signal output by the clock tree 200 is doubled by the frequency doubling circuit 300, and the obtained frequency-doubled signal is transmitted to the register and combinational logic driven by the clock tree 200 network, so as to ensure the frequency of the data and the functional clock to be consistent, and ensure the normal operation of the chip.

When the chip needs to be tested, a clock signal generated by the test clock is output as an initial clock signal through the clock selection module, and enters the frequency division circuit 100.

In the same way as the clock transmission method for normal operation of the chip, the clock signal generated by the test clock is converted into a frequency-divided signal with a lower frequency, thereby reducing the power consumption of the test clock tree 200. The output signal is restored through the frequency multiplier circuit 300, so that the synchronization of the test vector and the test clock frequency is satisfied, and the normal ATE test is not affected.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It should be noted that:

reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

In addition, it should be noted that, in the embodiments described in the present specification, names and the like of circuit modules may be different. All equivalent or simple changes of the structure, the characteristics and the principle of the invention which are described in the patent conception of the invention are included in the protection scope of the patent of the invention. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.