阅读说明：本技术 一种弱能量收集用肖特基二极管的制备方法 (Preparation method of Schottky diode for weak energy collection ) 是由 左瑜 于 2020-12-14 设计创作，主要内容包括：本发明公开了一种弱能量收集用肖特基二极管的制备方法,包括：选取<110>晶向的Si衬底；在Si衬底的上表面形成第一Ge缓冲层；在第一Ge缓冲层的上表面形成n～+Ge层；在n～+Ge层上表面的第一区域内形成n～-Ge层；在n～-Ge层内形成倒梯形的凹槽,倒梯形的斜边与法线夹角为40～60°；在倒梯形的凹槽内形成第一电极,并在n～+Ge层上表面的第二区域形成第二电极。本发明选用高电子迁移率的<110>晶向Ge,设置凹槽增加金半接触面积,降低SBD串联电阻,提高整流效率；凹槽侧边为<100>晶向,增大了金半接触区域半导体电子亲和能,因此能够提高2.45GHz弱能量密度下SBD的整流效率。(The invention discloses a preparation method of a Schottky diode for weak energy collection, which comprises the following steps: selecting<110>A Si substrate of a crystal orientation; forming a first Ge buffer layer on the upper surface of the Si substrate; forming n on the upper surface of the first Ge buffer layer + A Ge layer; at n + Forming n in the first region of the upper surface of the Ge layer ‑ A Ge layer; at n ‑ Forming a reverse trapezoidal groove in the Ge layer, wherein the included angle between the inclined edge of the reverse trapezoidal groove and the normal is 40-60 degrees; forming a first electrode in the inverted trapezoidal groove at n + A second region of the upper surface of the Ge layer forms a second electrode. The invention selects the materials with high electron mobility<110>The crystal orientation Ge is provided with a groove to increase the contact area of the gold and the semiconductor, reduce the series resistance of the SBD and improveThe rectification efficiency is high; the side of the groove is<100>The crystal orientation increases the electron affinity of the semiconductor in the gold half-contact area, so that the rectification efficiency of the SBD under the weak energy density of 2.45GHz can be improved.)

1. A preparation method of a Schottky diode for weak energy collection is characterized by being applied to 2.45GHz weak energy density collection, and comprises the following steps:

selecting a Si substrate with a <110> crystal orientation;

forming a first Ge buffer layer on the upper surface of the Si substrate;

forming n on the upper surface of the first Ge buffer layer⁺A Ge layer;

at said n⁺Forming n in the first region of the upper surface of the Ge layer^-A Ge layer;

at said n^-Forming a reverse trapezoidal groove in the Ge layer, wherein an included angle between the inclined edge of the reverse trapezoidal groove and the normal is 40-60 degrees;

forming a first electrode in the inverted trapezoidal groove and in the n⁺A second region of the upper surface of the Ge layer forms a second electrode.

2. The method of forming a schottky diode for weak energy collection according to claim 1, wherein the forming a first Ge buffer layer on the upper surface of the Si substrate comprises:

and (3) generating Ge with the thickness of 0.15-0.2 mu m on the upper surface of the Si substrate at 275-325 ℃ by using an RPCVD process as a first Ge buffer layer.

3. The method of forming a schottky diode for weak energy collection according to claim 1, wherein the n is formed on the upper surface of the first Ge buffer layer⁺A Ge layer comprising:

generating a second Ge buffer layer with the thickness of 0.4-0.5 mu m on the surface of the first Ge buffer layer at the temperature of 500-850 ℃ by using an RPCVD (plasma chemical vapor deposition) process;

and carrying out ion implantation on the second Ge buffer layer to form an n + Ge layer.

4. The method of manufacturing a schottky diode for weak energy collection according to claim 3, wherein the ion implantation of the second Ge buffer layer to form an n + Ge layer comprises:

use ofIon implantation process at pH₃Implanting P ions into the second Ge buffer layer as P doping source to form a doping concentration of 2.0 × 10²⁰N of (A) to (B)⁺And a Ge layer.

5. The method of forming a weak energy collecting schottky diode as claimed in claim 1, wherein said n is⁺Forming n in the first region of the upper surface of the Ge layer^-A Ge layer comprising:

at said n⁺Growing a third Ge layer on the upper surface of the Ge layer;

ion implantation is carried out on the third Ge layer to form n^-A Ge layer;

etching off the n⁺N on the upper surface of the Ge layer except the first region^-And a Ge layer.

6. The method of forming a weak energy collecting schottky diode as claimed in claim 5, wherein said n is⁺And growing a third Ge layer on the upper surface of the Ge layer, wherein the third Ge layer comprises:

using a PRCVD process at a temperature of 300 ℃ at said n⁺And a third Ge layer with the thickness of 1 mu m is grown on the upper surface of the Ge layer.

7. The method of claim 5, wherein the ion implantation of the third Ge layer to form n is performed to form n^-A Ge layer comprising:

by ion implantation at pH₃Is a P doping source, and P ions are implanted into the third Ge layer to form a doping concentration of 3.0 × 10¹⁷N of (A) to (B)^-And a Ge layer.

8. The method of forming a weak energy collecting schottky diode as claimed in claim 1, wherein said n is^-Forming a reverse trapezoidal groove in the Ge layer, including:

using a plasma etching process at said n^-An inverted trapezoidal groove with the depth of 400-600 nm is formed in the Ge layer.

9. The method of manufacturing a schottky diode for weak energy collection according to claim 1 or 8, wherein the inclined side of the inverted trapezoid forms an angle of 45 ° with the normal.

10. The method as claimed in claim 1, wherein a first electrode is formed in the inverted trapezoidal groove and a second electrode is formed in the n-shaped groove⁺A second region of the Ge layer upper surface forms a second electrode comprising:

depositing a metal W in the inverted trapezoidal groove to form a first electrode, wherein W protrudes from n^-The thickness of the Ge layer surface is 50 nm;

at said n⁺Depositing Al metal in a second region of the Ge layer surface to form a second electrode, wherein the Al protrudes from the n⁺The thickness of the Ge layer surface was 30 nm.

Technical Field

The invention belongs to the field of semiconductors, and particularly relates to a preparation method of a Schottky diode for weak energy collection.

Background

The microwave wireless energy collection system can capture radio frequency signals in the environment through a microwave receiving antenna, a rectification circuit in the system utilizes a core element Schottky diode to rectify the energy of the radio frequency signals, the radio frequency energy is converted into direct current energy, and the direct current energy is supplied to a receiving load, so that power is supplied to electronic equipment. The microwave wireless energy collection technology has the advantages of non-contact, wide coverage range and the like.

By monitoring the energy density of the environment, radio frequency signals in a 2.45GHz (2.38 GHz-2.45 GHz) Wi-Fi frequency band are main radio frequency signal sources in the environment, the radio frequency signal sources may come from wireless terminals such as a Wi-Fi router, a notebook computer and a tablet personal computer, but the power density of the radio frequency signal sources is less than-20 dBm, and the radio frequency signal sources belong to the category of weak energy density. Aiming at the 2.45GHz weak energy density Wi-Fi waveband, an energy collection technology is adopted for energy collection, the range of energy collection can be expanded, and meanwhile, the method also accords with the era theme of environmental protection. Research shows that how to improve the rectification efficiency is a key technology for realizing energy collection aiming at a 2.45GHz weak energy density Wi-Fi waveband wireless energy collection system. As is known in the art, a schottky diode is used as a core device in a rectifying circuit, and the performance of the schottky diode directly determines the upper limit of the rectifying efficiency of the microwave wireless energy collecting system.

At present, for a 2.45GHz weak energy density Wi-Fi band wireless energy collection system, the rectification efficiency of the 2.45GHz weak energy density Wi-Fi band wireless energy collection system based on an Agilent HSMS-2850Ge semiconductor Schottky diode (SBD) is the highest, but the rectification efficiency is still less than 10% under the condition of-20 dBm power density. At such low rectification efficiency, commercial application of 2.45GHz weak energy density Wi-Fi band wireless energy harvesting cannot be achieved at all.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a preparation method of a Schottky diode for weak energy collection. The technical problem to be solved by the invention is realized by the following technical scheme:

a preparation method of a Schottky diode for weak energy collection is applied to 2.45GHz weak energy density collection and comprises the following steps:

selecting a Si substrate with a <110> crystal orientation;

forming a first Ge buffer layer on the upper surface of the Si substrate;

forming n on the upper surface of the first Ge buffer layer⁺A Ge layer;

at said n⁺Forming n in the first region of the upper surface of the Ge layer^-A Ge layer;

at said n^-Forming a reverse trapezoidal groove in the Ge layer, wherein an included angle between the inclined edge of the reverse trapezoidal groove and the normal is 40-60 degrees;

forming a first electrode in the inverted trapezoidal groove and in the n⁺A second region of the upper surface of the Ge layer forms a second electrode.

In an embodiment of the present invention, the forming a first Ge buffer layer on the upper surface of the Si substrate includes:

and (3) generating Ge with the thickness of 0.15-0.2 mu m on the upper surface of the Si substrate at 275-325 ℃ by using an RPCVD process as a first Ge buffer layer.

In one embodiment of the present invention, said forming n on the upper surface of said first Ge buffer layer⁺A Ge layer comprising:

generating a second Ge buffer layer with the thickness of 0.4-0.5 mu m on the surface of the first Ge buffer layer at the temperature of 500-850 ℃ by using an RPCVD (plasma chemical vapor deposition) process;

and carrying out ion implantation on the second Ge buffer layer to form an n + Ge layer.

In an embodiment of the present invention, the ion implanting the second Ge buffer layer to form an n + Ge layer includes:

using an ion implantation process at pH₃Implanting P ions into the second Ge buffer layer as P doping source to form a doping concentration of 2.0 × 10²⁰N of (A) to (B)⁺And a Ge layer.

In one embodiment of the present invention, said n is⁺Forming n in the first region of the upper surface of the Ge layer^-A Ge layer comprising:

at said n⁺Growing a third Ge layer on the upper surface of the Ge layer;

ion implantation is carried out on the third Ge layer to form n^-A Ge layer;

etching off the n⁺N on the upper surface of the Ge layer except the first region^-And a Ge layer.

In one embodiment of the present invention, said n is⁺And growing a third Ge layer on the upper surface of the Ge layer, wherein the third Ge layer comprises:

using a PRCVD process at a temperature of 300 ℃ at said n⁺And a third Ge layer with the thickness of 1 mu m is grown on the upper surface of the Ge layer.

In one embodiment of the present invention, the ion implantation of the third Ge layer forms n^-A Ge layer comprising:

by ion implantation at pH₃Is a P doping source, and P ions are implanted into the third Ge layer to form a doping concentration of 3.0 × 10¹⁷N of (A) to (B)^-And a Ge layer.

In one embodiment of the present invention, said n is^-Forming a reverse trapezoidal groove in the Ge layer, including:

using a plasma etching process at said n^-An inverted trapezoidal groove with the depth of 400-600 nm is formed in the Ge layer.

In one embodiment of the invention, the inclined side of the inverted trapezoid forms an angle of 45 ° with the normal.

In an embodiment of the invention, the first electrode is formed in the inverted trapezoidal groove and is positioned on the n⁺A second region of the Ge layer upper surface forms a second electrode comprising:

depositing a metal W in the inverted trapezoidal groove to form a first electrode, wherein W protrudes from n^-The thickness of the Ge layer surface is 50 nm;

at said n⁺Depositing Al metal in a second region of the Ge layer surface to form a second electrode, wherein the Al protrudes from the n⁺The thickness of the Ge layer surface was 30 nm.

Compared with the prior art, in the embodiment of the invention, the device main body material is selected from the material with high electron mobility<110>The crystal orientation Ge can reduce the series resistance of the device and improve the SBD rectification efficiency; at said n^-The upper surface of the Ge layer is provided with a groove, so that the gold-half contact area can be increased, the SBD series resistance is further reduced, and the rectification is improvedEfficiency; and, specifically set up the recess into down trapezoidal, the hypotenuse is 40 ~ 60 with the normal contained angle, forms the side in fact<100>Direction of crystal and normal line<110>The reverse trapezoidal inclined groove structure of the crystal direction is characterized in that the side edge of the groove is<100>Crystal orientation with electron affinity greater than<110>The crystal orientation can further improve the SBD rectification efficiency by increasing the electron affinity of the semiconductor in the gold half-contact area. Therefore, the embodiment of the invention can improve the rectification efficiency of the SBD under the weak energy density of 2.45 GHz.

In addition, a cathode is provided at n⁺On the Ge layer, n can be avoided⁺The lower dislocation density of the Ge layer is high, and the interface difference between the first Ge buffer layer and the Si substrate causes the problems of large leakage and poor reliability of the SBD device; the Schottky device is prepared on the Si substrate, and the Schottky device has the advantages of low cost and low process realization difficulty.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a weak energy collecting schottky diode according to an embodiment of the present invention;

fig. 2a to fig. 2k are schematic diagrams illustrating a method for manufacturing a weak energy collecting schottky diode according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a schottky diode for weak energy collection according to an embodiment of the present invention, where the method is applied to 2.45GHz weak energy density collection, as shown in fig. 1, the method for manufacturing a schottky diode for weak energy collection according to an embodiment of the present invention includes the following steps:

s101, selecting a Si substrate with a crystal orientation of <110 >;

s102, forming a first Ge buffer layer on the upper surface of the Si substrate;

s103, forming n on the upper surface of the first Ge buffer layer⁺A Ge layer;

s104, in the n⁺Forming n in the first region of the upper surface of the Ge layer^-A Ge layer;

s105, in the n^-Forming a reverse trapezoidal groove in the Ge layer, wherein an included angle between the inclined edge of the reverse trapezoidal groove and the normal is 40-60 degrees;

s106, forming a first electrode in the inverted trapezoidal groove and arranging the first electrode in the n⁺A second region of the upper surface of the Ge layer forms a second electrode.

The following is a detailed description:

in the embodiment of the invention, the Si substrate is selected because of its low cost and easy peeling property, which can ensure the efficiency and yield of the schottky diode produced subsequently. The Si substrate with the <110> crystal orientation is specifically used to grow Ge with the <110> crystal orientation thereon. The reason is that Ge of <110> crystal orientation has high electron mobility and low series resistance, and according to the research of the inventors, reducing the series resistance can improve the rectification efficiency of the SBD, so that the rectification efficiency of the SBD can be improved by specifically selecting the device body material to be <110> crystal orientation Ge.

In the embodiment of the invention, n is^-The upper surface of the Ge layer is provided with an inverted trapezoidal groove which can be arranged in the n^-The center of the upper surface of the Ge layer can be close to the n^-Either end of the upper surface of the Ge layer.

The inventor researches and discovers that n is^-The grooves are formed in the upper surface of the Ge layer, so that the gold-semiconductor contact area can be enlarged, the current intensity is improved, the series resistance is reduced, and the rectifying efficiency of the SBD can be improved.

In addition, in the embodiment of the present invention, an included angle between the oblique side of the inverted trapezoid and the normal is 40 to 60 °, and with respect to a groove with both the left and right sides being rectangular, the oblique side in the angle range of the embodiment of the present invention can convert the crystal orientation of Ge on the left and right vertical sides from the original <110> crystal orientation to a <100> crystal orientation, that is, a side <100> crystal orientation and a normal <110> crystal orientation are formed. Since Ge semiconductors have anisotropic electron affinity, the electron affinity values along different crystal orientations are different, Ge of <100> crystal orientation has an electron affinity of 4.272eV, and Ge of <110> crystal orientation has an electron affinity of 4.163 eV. According to the research result of the inventor, the rectification efficiency of the SBD under the weak energy density can be improved by increasing the electron affinity, so that the embodiment of the invention introduces the <100> crystal orientation on the side of the groove by specifically setting the inclination angle of the groove, and the electron affinity of the groove is greater than the original <110> crystal orientation, so that the rectification efficiency of the SBD under the weak energy density of 2.45GHz can be improved by increasing the semiconductor electron affinity of the metal-semiconductor contact region. The specific principles related to this section are described later in connection with the inventive concept.

In the embodiment of the invention, n is^-Ge layer and said n⁺The Ge layer forms a step structure with a high step and a low step, wherein the first electrode is an anode, and the n at the higher part is positioned^-The second electrode is a cathode and is positioned in the n of the lower part in the inverted trapezoidal groove on the upper surface of the Ge layer⁺A Ge layer upper surface; the cathode is arranged at n⁺The Ge upper layer can prevent the problems of large SBD leakage and poor reliability caused by high-density dislocation, and can also avoid the problem of device performance degradation caused by the interface difference between the first Ge buffer layer and the Si substrate.

In the embodiment of the invention, the main body material of the device is selected to have high electron mobility<110>The crystal orientation Ge can reduce the series resistance of the device and improve the SBD rectification efficiency; at said n^-The grooves are formed in the upper surface of the Ge layer, so that the gold-semiconductor contact area can be increased, the SBD series resistance is further reduced, and the rectification efficiency is improved; and, specifically set up the recess into down trapezoidal, the hypotenuse is 40 ~ 60 with the normal contained angle, forms the side in fact<100>Direction of crystal and normal line<110>The reverse trapezoidal inclined groove structure of the crystal direction is characterized in that the side edge of the groove is<100>Crystal orientation with electron affinity greater than<110>The crystal orientation can further improve the SBD rectification efficiency by increasing the electron affinity of the semiconductor in the gold half-contact area. Therefore, under the combined action of the above aspects, when the schottky diode provided by the embodiment of the invention is applied to the rectifying circuit of the 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collection in the weak energy density environment can be realizedThe application is as follows.

In addition, a cathode is provided at n⁺On the Ge layer, n can be avoided⁺The lower dislocation density of the Ge layer is high, and the interface difference between the first Ge buffer layer and the Si substrate causes the problems of large leakage and poor reliability of the SBD device; the Schottky device is prepared on the Si substrate, and the Schottky device has the advantages of low cost and low process realization difficulty.

Specific principles regarding embodiments of the present invention are described below in conjunction with the inventive concepts.

The above process steps are specifically described below.

Referring to fig. 2a to 2k, fig. 2a to 2k are schematic diagrams illustrating a method for manufacturing a weak energy collecting schottky diode according to an embodiment of the present invention. The preparation method is specifically described in the following steps and detailed parameters. The method comprises the following steps:

s201, selecting a Si substrate 001 with a <110> crystal orientation; as shown in fig. 2 a;

s202, cleaning; cleaning the surface of a Si substrate 001 by using dilute hydrofluoric acid to remove substrate water vapor, O, C and other impurity atoms;

s203, preparing a first Ge buffer layer 002; as shown in fig. 2b, Ge with a thickness of 0.15-0.2 μm is generated on the upper surface of the Si substrate 001 as a first Ge buffer layer 002 by using an RPCVD process at a low temperature of 275-325 ℃;

s204, preparing a second Ge buffer layer; as shown in fig. 2c, a second Ge buffer layer 0031 with a thickness of 0.4-0.5 μm is formed on the surface of the first Ge buffer layer 002 by using an RPCVD process at a high temperature of 500-850 ℃; the two Ge buffer layers are prepared on the Si substrate by adopting a high-low temperature two-step method, so that the problem of lattice mismatch existing between silicon and germanium can be solved, mismatch dislocation is reduced, a flat surface is obtained, the processing technology difficulty of a device is reduced, the technology cost of the device is reduced, and the subsequent growth of a high-quality germanium tin layer is facilitated. Meanwhile, tensile stress can be generated in the Ge layer in the process, so that the direct band gap of Ge is reduced, the absorption coefficient is enhanced, and the preparation of the high-performance Schottky diode is facilitated.

S205, ion implantation to form n⁺A Ge layer 003; as shown in fig. 2d, an ion implantation process is usedAt pH of₃P ions are implanted into the second Ge buffer layer 0031 as a P doping source to form a P-doped layer having a doping concentration of 2.0 × 10²⁰N of (A) to (B)⁺A Ge layer 003; n is⁺The Ge layer 003 is highly doped to facilitate subsequent ohmic contact formation.

S206, annealing; performing four times of circular annealing by adopting a circular annealing process at 780-900 ℃;

s207, preparing a third Ge layer; as shown in fig. 2e, using a PRCVD process at a temperature of 300 ℃, at said n⁺Ge with the thickness of 1 μm is grown on the surface of the Ge layer 003 to serve as a third Ge layer 0041;

s208, preparation n^-A Ge layer; as shown in fig. 2f, using an ion implantation process at PH₃P ions are implanted into the third Ge layer 0041 as a P doping source to form a doping concentration of 3.0 × 10¹⁷N of (A) to (B)^-A Ge layer 004; n is^-The Ge layer 004 is lightly doped to facilitate subsequent schottky contact formation.

S209, annealing; carrying out four times of cyclic annealing in an N atmosphere by adopting a cyclic annealing process at 780-900 ℃;

s210, cleaning; using deionized water to circularly clean n^-A Ge layer 004;

s211, coating photoresist; as shown in FIG. 2g, in said n^-Photoresist 007 is coated on the surface of the Ge layer 004;

s211, exposing and etching; exposure of n by means of a photolithographic process^-The photoresist 007 on the surface of the Ge layer 004 except for a first region, which can be a region of the photoresist 007 near one end; for example, the first region may be a left half region of the photoresist 007; cleaning with photoresist to remove n^-The photoresist 007 on the surface of the Ge layer 004 except for the first region; at CF₄And SF₆Etching to n by using plasma etching process in gas environment⁺Forming a step structure on the surface of the Ge layer 003; as shown in fig. 2 h;

s213, as shown in FIG. 2i, removing n^-Photoresist 007 on the surface of the Ge layer 004; it is understood that the step structure is followed by the step structure with the higher surface portion beingN is^-A Ge layer 004 with said n on the lower surface⁺A Ge layer 003;

s214, as shown in FIG. 2j, using the plasma etching process to n^-The Ge layer 004 is etched to form an inverted trapezoidal notch 008. The included angle between the inclined edge of the inverted trapezoid and the normal is 40-60 degrees, preferably 45 degrees, and the angle can accurately enable Ge to be collected from the surface of the glass substrate<110>Transformation of crystal orientation<100>A crystal orientation; the depth of the groove 008 is 400-600 nm, the depth of the inclined groove is 400-600 nm, the breakdown voltage of the device can be improved, and the performance of the device is improved.

S215, coating photoresist on the groove 008, and exposing the photoresist by using a photoetching process;

s216, preparing an electrode; as shown in FIG. 2k, using molecular beam evaporation process, at n respectively⁺Depositing metal Al and W on the surface of the Ge layer 003 and the surface of the inverted trapezoidal groove 008, wherein the W is filled in the inverted trapezoidal groove 008; and W protrudes from n^-The thickness of the surface of the Ge layer 004 is 50 nm; al protrusion from n⁺The thickness of the surface of the Ge layer 003 was 30 nm. Then, the metal in the designated region is etched by an etching process to form the first electrode 005 and the second electrode 006. The first electrode 005 is an anode, and the second electrode 006 is a cathode.

Through the above process steps, the structure of the prepared silicon-based hybrid crystal orientation inclined groove germanium schottky diode is shown in fig. 2 k. The method specifically comprises the following steps:

<110>a Si substrate 001 of crystal orientation; the first Ge buffer layer 002; n is⁺A Ge layer 003; n is^-A Ge layer 004; the first electrode 005; and a second electrode 006.

To facilitate an understanding of the structure and benefits of the silicon-based hybrid crystal orientation sloped trench ge schottky diode of the embodiments of the present invention, the inventors' inventive concepts are briefly introduced herein and the foregoing principles are described.

The inventor researches the rectification efficiency, and the formula of the rectification efficiency is as follows:

in the formula (1), P_DCCorresponding power, P, of the direct current output after rectification_RFFor the power of the radio-frequency signal in the environment of the input before rectification, eta_MTo match efficiency, η_pIs the efficiency, η, related to parasitic parameters₀Is the conversion efficiency, η, in a nonlinear device_{DC_transfer}Is the efficiency with which direct current is transferred from the circuit to the load.

In the formula (1), the first and second groups,

q is a quality factor, Q_CTo match the quality factors of network elements, to make the matching efficiency eta_MMaximum, usually Q<<Q_C。

In the formula (1), the first and second groups,

R_jis junction resistance, R_sIs a series resistance, C_jIs the junction capacitance and f is the frequency.

In the formula (1), the first and second groups,

P_inis the power that is going into the rectifier,is zero-bias current responsivity, R_LIs a load resistance.

In the formula (1), the first and second groups,

therefore, the expression of the rectification efficiency η obtained by integrating the expressions (1), (2), (3), (4) and (5) is:

where ω is 2 · pi · f.

As can be seen from equation (6), the junction capacitance C is reduced at high frequencies_jSeries resistance R_sJunction resistance R_jThe rectification efficiency can be improved. Meanwhile, the zero bias current responsivity of the device is increasedRectification efficiency can also be improved.

Thus, in one aspect, the inventors contemplate reducing the junction capacitance C_jSeries resistance R_sJunction resistance R_jThe angle of (2) improves the rectification efficiency of the SBD at weak energy density. On the other hand, the inventors expect the zero-bias current responsivity of the device to be increasedAnd the rectification efficiency of the SBD under the weak energy density is improved.

Thus, the inventors further demonstrated zero-bias current responsivity to SBDThe formula of zero-bias current responsivity is shown in the following formula (7):

wherein i⁽¹⁾(V) and i⁽²⁾(V) are the first and second derivative functions of current versus voltage, respectively. The current formula is shown below (8) (considering the effects of mirror force and tunneling):

the first derivative function and the second derivative function of the current versus the voltage obtained from equation (8) are expressed by the following equations (9) and (10), respectively:

substituting (9) and (10) into equation (7), the SBD zero-bias current responsivityComprises the following steps:

in the formula (11), the reaction mixture is,other symbolic physical meanings are described in the literature "semiconductor device physics". Since the correction term in equation (11), i.e., the third term, is either positive or zero-biasedSmall, so SBD zero-bias current responsivity can be simplified to equation (12):

as can be seen from equation (12), the SBD zero-bias current responsivity is mainly determined by the SBD ideality factor n. The smaller the value of n, the zero-bias current responsivityThe larger the rectification efficiency of the SBD. Where the ideality factor n is the first partial derivative of the voltage V with respect to the current J, and is expressed as:

because of the lnI-V curveCan be characterized asThus, the formula (13) shows that the steeper the slope of the lnI-V curve, i.e., the slopeThe larger, theThe smaller the n value is, the larger the zero-bias current responsivity of the SBD is, and the larger the rectification efficiency of the SBD is. That is, increaseThe zero-bias current responsivity can be improved, and the circuit rectification efficiency under weak energy density can be improved. It is to be emphasized here that the value of n in equation (13) is not an ideal factor extracted from the normal operating state of the SBD I-V curve, but an ideal factor extracted from the weak energy rectification region.

The inventor researches and discovers that the slope of an lnI-V curve of an SBD weak energy rectification areaAnd effective physical constantsBarrier height phi of metal side_nsClosely related, see the following formula (14), wherein ∈ indicates a proportional relationship.

As can be seen from the formula (14) Phi_nsThe exponential term in equation (14) is understood to decrease φ_nsCan be remarkably increasedThus, the inventors aimed at_nsFurther studies found that:

φ_ns＝W_m-χ (15)

wherein, W_mChi is the metal work function and the semiconductor electron affinity. From the formula (15), W is reduced_mOr increasing χ may decrease φ_nsThereby realizing the zero bias current responsivity under the condition of increasing the weak energy densityThe purpose of improving the SBD rectification efficiency under weak energy density.

In particular, in the silicon-based mixed crystal orientation inclined groove germanium Schottky diode for weak energy collection, on one hand, the device main body material is selected to be high in electron mobility<110>The crystal orientation Ge reduces the series resistance of the device by improving the electron mobility, and improves the SBD rectification efficiency; on the other hand, in said n^-The grooves are formed in the upper surface of the Ge layer, so that the gold-semiconductor contact area can be increased, the SBD series resistance is further reduced, and the rectification efficiency is improved, so that the rectification efficiency can be greatly improved in the two aspects; on the other hand, specifically set up the recess into down trapezoidal, the hypotenuse is 40 ~ 60 with the normal contained angle, compares in both sides and is the recess of perpendicular side, and through this angle, this scheme changes the side crystal orientation into<100>Crystal orientation with electron affinity greater than<110>Crystal orientation, substantially forming side edges<100>Direction of crystal and normal line<110>And (4) crystal orientation. Thus, the introduced side edges<100>The crystal orientation increases the electron affinity of the semiconductor in the gold semi-contact area, can improve the zero-bias current responsivity and improve the rectification efficiency of the SBD under weak energy density. Therefore, under the combined action of the above aspects, when the schottky diode provided by the embodiment of the invention is applied to a rectifying circuit of a 2.45GHz weak energy density collecting system, the rectifying efficiency of the whole system can be effectively improved, and the energy collecting application in the weak energy density environment is realized.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.