阅读说明：本技术 一种mos管的sgt制造工艺 (SGT manufacturing process of MOS (metal oxide semiconductor) tube ) 是由 黄亚军 黎忠瑾 于 2020-11-17 设计创作，主要内容包括：本发明公开了一种MOS管的SGT制造工艺,包括半导体衬底,所述半导体衬底内置源级、阱区和阱隔离区,阱区位于半导体衬底的正中处,阱区的数量为两组依次位于阱区的两侧,半导体衬底上位于阱区的两侧依次设置有源级与漏级,半导体衬底氧化层顶部通过化学生成栅氧化层,栅氧化层的顶部设置有多晶硅层,多晶硅层呈凸字状。该MOS管的SGT制造工艺,通过采用掺杂工艺定量的在源极和漏极区域形成N阱,对其掺杂的浓度与量均得到控制,从而一定程度上能够有效的避免晶体管栅极阈值电压因为掺杂的浓度的无法控制而产生的波动,同时也一定程度上避免了晶体管在开通状态时栅极电压不稳定的现象,大大提高了晶体管的稳定性能。(The invention discloses an SGT (silicon germanium transistor) manufacturing process of an MOS (metal oxide semiconductor) transistor, which comprises a semiconductor substrate, wherein a source electrode, a well region and a well isolation region are arranged in the semiconductor substrate, the well region is positioned in the middle of the semiconductor substrate, the number of the well regions is two, the two well regions are sequentially positioned on two sides of the well region, the source electrode and the drain electrode are sequentially arranged on two sides of the well region on the semiconductor substrate, a gate oxide layer is chemically generated on the top of an oxide layer of the semiconductor substrate, a polycrystalline silicon layer is arranged on the top of. According to the SGT manufacturing process of the MOS transistor, the N wells are formed in the source electrode region and the drain electrode region quantitatively by adopting the doping process, and the doping concentration and doping amount of the N wells are controlled, so that fluctuation of the threshold voltage of the grid electrode of the transistor due to uncontrollable doping concentration can be effectively avoided to a certain extent, meanwhile, the phenomenon that the grid electrode voltage of the transistor is unstable in the on state is avoided to a certain extent, and the stability of the transistor is greatly improved.)

1. The utility model provides a SGT manufacturing process of MOS pipe, includes semiconductor substrate (7), a serial communication port, semiconductor substrate (7) embeds source (1), well region (5) and well isolation region (6), well region (5) are located the centre department of semiconductor substrate (7), the quantity of well region (5) is two sets of both sides that are located well region (5) in proper order, the both sides that are located well region (5) on semiconductor substrate (7) have set gradually source (1) and drain-source, chemical generation gate oxide (8) are passed through at semiconductor substrate (7) oxide layer top, the top of gate oxide (8) is provided with polycrystalline silicon layer (4), polycrystalline silicon layer (4) are the dogbone form, the lateral wall oxidation of polycrystalline silicon layer (4) generates polycrystalline silicon grid (2), the top of polycrystalline silicon layer (4) is provided with alloy-layer (3).

2. The SGT process for MOS transistor according to claim 1, wherein the semiconductor substrate (7) is made of silicon, germanium or silicon-on-insulator, and the top of the semiconductor substrate (7) is oxidized to form an oxide region.

3. An SGT process for MOS transistors according to claim 1, characterized in that said source (1) and drain are both located in the oxide layer of the semiconductor substrate (7).

4. The SGT manufacturing process for MOS transistors according to claim 1, wherein the well isolation region (6) is a trench isolation structure, the trench is defined as SGT, and the trench is filled with borosilicate glass material.

5. An SGT process for MOS transistors according to claim 1, wherein the main material of the alloy layer (3) is aluminum.

6. The SGT manufacturing process for MOS transistors according to claim 1, comprising the following steps:

s1: oxidizing the surface of the semiconductor substrate to form a protective film which can be used as a doped barrier and is called a field oxide layer;

s2: forming concave holes on the field oxide layer by a photoetching process to define the specific positions of a source electrode, a grid electrode and a drain electrode of the transistor;

s3: carrying out oxidation reaction processing on the semiconductor substrate and silicon dioxide, wherein an oxide film can grow on the exposed silicon surface of the semiconductor substrate and can be used as a grid oxide layer;

s3: depositing a layer of polycrystalline silicon on a semiconductor substrate to serve as a grid structure;

s4: etching two openings in the oxide layer or the polysilicon layer according to the circuit pattern, wherein the two openings define a source electrode area and a drain electrode area of the transistor;

s5: forming N wells in the source electrode region and the drain electrode region quantitatively by adopting a doping process, etching two openings in an oxide layer or a polycrystalline silicon layer according to a circuit pattern, wherein two groups of openings are positioned at two sides of the source electrode and the drain electrode and are defined as well isolation regions, namely SGTs;

s6: adding an oxide film in the source and drain regions;

s7: respectively etching holes, called contact holes, formed in the source electrode region, the grid electrode region and the drain electrode region by adopting a photoetching process;

s8: a layer of conductive metal, typically an alloy of aluminum, is deposited over the surface of the semiconductor substrate.

7. The SGT process for MOS transistors according to claim 6, wherein the S9: the remaining part of the metal film on the surface of the semiconductor substrate connects each component of the chip to each other without fail according to the design requirements.

8. The SGT process for making MOS transistors according to claim 6, wherein said layer of conductive metal bit alloy.

Technical Field

The invention relates to the technical field of MOS (metal oxide semiconductor) tubes, in particular to an SGT (silicon germanium transistor) manufacturing process of an MOS tube.

Background

Increasing the integration density of electronic devices by reducing the physical size of the electronic devices is a major development trend to improve the performance of the electronic devices. The development of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has also followed this development. The MOSFET structure includes source and drain electrodes and a semiconductor channel region, and a gate electrode composed of a metal layer and an oxide layer. With the continuous reduction of the size of the MOS transistor to the nanometer level, the phenomenon of gate tunneling leakage can occur due to the excessively small thickness of the oxide layer, so that the MOSFET fails, but the regulation and control effect of the gate voltage on the FET in the channel region can be weakened due to the larger thickness of the oxide layer.

When most of existing transistors are generated, low-concentration random doping in a channel region of the transistor can cause the threshold voltage of a gate of the transistor to fluctuate, and can cause the gate voltage of the transistor in an on state to be unstable, so that the performance of the transistor is unstable.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides an SGT manufacturing process of an MOS transistor, which solves the problems that when most of the existing transistors are generated, low-concentration random doping in a channel region of the transistor can cause the fluctuation of the threshold voltage of the gate of the transistor, can cause the instability of the gate voltage of the transistor in an opening state, and can cause the instability of the performance of the transistor.

In order to achieve the purpose, the invention adopts the following technical scheme:

the utility model provides a SGT manufacturing process of MOS pipe, includes the semiconductor substrate, built-in source level, well region and well isolation region of semiconductor substrate, well region are located the centre department of semiconductor substrate, and well region's quantity is two sets of both sides that are located well region in proper order, and the both sides that are located well region on the semiconductor substrate have set gradually source level and drain-source cascade, and the gate oxide layer is passed through chemical generation at semiconductor substrate oxide layer top, and the top of gate oxide layer is provided with the polycrystalline silicon layer, and the polycrystalline silicon layer is the dogbone form, and the lateral wall oxidation of polycrystalline silicon layer generates the polycrystalline silicon grid.

Preferably, the main material of the semiconductor substrate is a semiconductor substrate such as silicon, germanium or silicon-on-insulator, and the top of the semiconductor substrate is oxidized to form an oxide layer region.

Preferably, the source and the drain are both located in an oxide layer of the semiconductor substrate.

Preferably, the well isolation region is a trench isolation structure, the trench is defined as an SGT, and the trench is filled with a borosilicate glass material.

Preferably, the main material of the alloy layer is aluminum.

An SGT manufacturing process of a MOS tube comprises the following steps:

s1: oxidizing the surface of the semiconductor substrate to form a protective film which can be used as a dopant

A miscellaneous barrier, called field oxide;

s2: forming concave holes on the field oxide layer by a photoetching process to define the specific positions of a source electrode, a grid electrode and a drain electrode of the transistor;

s3: carrying out oxidation reaction processing on the semiconductor substrate and silicon dioxide, wherein an oxide film can grow on the exposed silicon surface of the semiconductor substrate and can be used as a grid oxide layer;

s3: depositing a layer of polycrystalline silicon on a semiconductor substrate to serve as a grid structure;

s4: etching two openings in the oxide layer or the polysilicon layer according to the circuit pattern, wherein the two openings define a source electrode area and a drain electrode area of the transistor;

s5: forming N wells in the source electrode region and the drain electrode region quantitatively by adopting a doping process, etching two openings in an oxide layer or a polycrystalline silicon layer according to a circuit pattern, wherein two groups of openings are positioned at two sides of the source electrode and the drain electrode and are defined as well isolation regions, namely SGTs;

s6: adding an oxide film in the source and drain regions;

s7: respectively etching holes, called contact holes, formed in the source electrode region, the grid electrode region and the drain electrode region by adopting a photoetching process;

s8: depositing a layer of conductive metal, typically an alloy of aluminum, over the surface of the semiconductor substrate;

preferably, the step of S9: the remaining part of the metal film on the surface of the semiconductor substrate connects each component of the chip to each other without fail according to the design requirements.

Preferably, the conductive metal bit alloy layer.

Compared with the prior art, the invention has the beneficial effects that:

according to the SGT manufacturing process of the MOS transistor, the N wells are formed in the source electrode region and the drain electrode region quantitatively by adopting the doping process, and the doping concentration and doping amount of the N wells are controlled, so that fluctuation of the threshold voltage of the grid electrode of the transistor due to uncontrollable doping concentration can be effectively avoided to a certain extent, meanwhile, the phenomenon that the grid electrode voltage of the transistor is unstable in the on state is avoided to a certain extent, and the stability of the transistor is greatly improved.

Drawings

Fig. 1 is a schematic diagram of a MOS transistor structure according to the present invention.

In the figure: 1 source level, 2 polysilicon grid electrodes, 3 alloy layers, 4 polysilicon layers, 5 well regions, 6 well isolation regions, 7 semiconductor substrates and 8 gate oxide layers.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to achieve the above purpose, as shown in fig. 1, the present invention adopts the following technical solutions: an SGT manufacturing process of an MOS tube comprises a semiconductor substrate 7, wherein the semiconductor substrate 7 is mainly made of silicon, germanium or silicon on insulator and the like, the top of the semiconductor substrate 7 is subjected to oxidation to form an oxide layer area, a source 1, a well 5 and a well isolation area 6 are arranged in the semiconductor substrate 7, the well 5 is positioned in the center of the semiconductor substrate 7, the number of the well 5 is two, the two sets of the well 5 are sequentially positioned on two sides of the well 5, the source 1 and a drain are sequentially arranged on the semiconductor substrate 7 on two sides of the well 5, the source 1 and the drain are both positioned in the oxide layer of the semiconductor substrate 7, the well isolation area 6 is of a groove isolation structure, a groove is defined as SGT, borosilicate glass material is filled in the groove, a gate oxide layer 8 is chemically generated on the top of the oxide layer of the semiconductor substrate 7, a polycrystalline silicon layer 4 is arranged on the top of, oxidizing the outer side wall of the polycrystalline silicon layer 4 to generate a polycrystalline silicon grid 2, wherein an alloy layer 3 is arranged at the top of the polycrystalline silicon layer 4, and the alloy layer 3 is mainly made of aluminum;

an SGT manufacturing process of a MOS tube comprises the following steps:

s1: oxidizing the surface of the semiconductor substrate to form a protective film which can be used as a doped barrier and is called a field oxide layer;

s2: forming concave holes on the field oxide layer by a photoetching process to define the specific positions of a source electrode, a grid electrode and a drain electrode of the transistor;

s3: carrying out oxidation reaction processing on the semiconductor substrate and silicon dioxide, wherein an oxide film can grow on the exposed silicon surface of the semiconductor substrate and can be used as a grid oxide layer;

s3: depositing a layer of polycrystalline silicon on a semiconductor substrate to serve as a grid structure;

s4: etching two openings in the oxide layer or the polysilicon layer according to the circuit pattern, wherein the two openings define a source electrode area and a drain electrode area of the transistor;

s5: forming N wells in the source electrode region and the drain electrode region by adopting a doping process, etching two openings in the oxide layer or the polycrystalline silicon layer according to a circuit pattern, wherein two groups of openings are positioned at two sides of the source electrode and the drain electrode and are defined as well isolation regions, namely SGTs;

s6: adding an oxide film in the source and drain regions;

s7: respectively etching holes, called contact holes, formed in the source electrode region, the grid electrode region and the drain electrode region by adopting a photoetching process;

s8: a layer of conductive metal, typically an alloy of aluminum, is deposited over the surface of the semiconductor substrate.

In summary, the following steps: according to the SGT manufacturing process of the MOS transistor, the N wells are formed in the source electrode 1 and the drain electrode region quantitatively by adopting the doping process, and the doping concentration and doping amount of the N wells are controlled, so that fluctuation of the threshold voltage of the grid electrode of the transistor due to uncontrollable doping concentration can be effectively avoided to a certain extent, meanwhile, the phenomenon that the grid electrode voltage of the transistor is unstable in the on state is avoided to a certain extent, and the stability of the transistor is greatly improved.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.