阅读说明：本技术 一种碳化硅mosfet器件jfet区自对准掺杂工艺 (Self-aligned doping process for JFET (junction field effect transistor) area of silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) device ) 是由 陈允峰 黄润华 李士颜 刘昊 刘强 柏松 于 2020-11-29 设计创作，主要内容包括：本发明公开了一种碳化硅MOSFET器件JFET区自对准掺杂工艺,采用自对准的方法实现注入掺杂,对具体的自对准加工工艺,又细分为两种实现路线,一种是通过表面平整化的工艺方案,另一种是设计合适的JFET区宽度和多晶硅掩膜厚度比例,从而直接通过全片刻蚀工艺实现JFET区和p阱区的自对准。本发明能够在有效降低JFET区域电阻的同时,避免JFET区未注入完整,或者单边沟道被注入导致性能差异的风险。(The invention discloses a self-aligned doping process of a JFET (junction field effect transistor) area of a silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) device, which is characterized in that injection doping is realized by adopting a self-aligned method, and a specific self-aligned processing process is subdivided into two realization routes, wherein one is a process scheme of surface flattening, and the other is a process scheme of designing proper JFET area width and polysilicon mask thickness ratio, so that the self-alignment of the JFET area and a p-well area is directly realized by a full-wafer etching process. The invention can effectively reduce the resistance of the JFET area and simultaneously avoid the risk that the JFET area is not completely injected or a unilateral channel is injected to cause performance difference.)

1. A self-aligned doping process for a JFET region of a silicon carbide MOSFET device is characterized by comprising the following steps of:

s1: growing and depositing a mask medium on the surface of the silicon carbide epitaxial wafer;

s2: removing the mask medium on the surface of the JFET area;

s3: carrying out n-type ion implantation on the JFET area on the surface of the silicon carbide;

s4: depositing a polycrystalline silicon mask medium on the surface of the whole silicon carbide wafer;

s5: polishing and removing the polysilicon mask medium on the surface of the wafer except the JFET area by adopting a surface flattening process;

or, the polysilicon layer on the surface of the wafer is subjected to whole etching until the surface of the mask medium is etched, and the polysilicon medium is reserved in the JFET area;

s6: removing the previous mask medium through an etching process, and reserving a part of the mask medium by using photoresist as a mask through a photoetching process for a terminal area of the device;

s7: carrying out p-type p-well ion implantation on the surface of the silicon carbide;

s8: by self-aligned methods, i.e. covering the whole wafer with SiO₂The medium is etched and removed integrally, thereby reserving partial SiO of the side wall of the polysilicon medium₂A medium; or directly self-acting on polysilicon mediumAn oxidation growth process;

s9: carrying out n + type ion implantation on the silicon carbide surface so as to form a channel in a self-aligned manner in the p-well region;

s10: and removing all the mask media to complete the whole set of self-alignment process, and continuing the subsequent process of the SiC wafer.

2. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in S1, the mask medium is SiO₂SiN, variable component Si_xN_1-xSiON, the thickness of the mask medium is 0.5um to 5 um.

3. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in the step S2, the method for removing the medium in the JFET area is hydrofluoric acid wet etching or BOE wet etching, and side etching allowance with the same width is reserved according to the thickness of the medium.

4. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in the step S2, a dry etching process is adopted, and the thickness of the residual part of the medium is less than 500 angstroms.

5. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in S3, a single implantation is performed on the JFET region through the mask dielectric, or a maskless dielectric is selected for implantation in a whole wafer, or the mask dielectric is directly removed after the implantation is completed, i.e., a self-aligned process is not used.

6. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in S4, the polysilicon layer is deposited to a thickness of 0.5um to 5 um.

7. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: and in S5, when the polycrystalline silicon mask medium on the surface of the wafer except the JFET area is removed by polishing, the requirement on the uniformity of the surface-flattened wafer inside the wafer is required, and the thickness is at least within plus or minus 0.5 um.

8. The silicon carbide MOSFET device JFET region self-aligned doping process of claim 1, wherein: in the S5 step, the polysilicon layer on the surface of the wafer is integrally etched until SiO is etched₂The surface of a mask medium, and a JFET area with polysilicon medium reserved, wherein the thickness of the polysilicon layer adopted in the scheme is larger than that of SiO₂The thickness of the mask medium; the JFET area width is less than 2 um; polysilicon and SiO₂The etching ratio is more than 3: 1.

Technical Field

The invention relates to the field of semiconductor devices, in particular to a self-aligned doping process for a JFET (junction field effect transistor) region of a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) device.

Background

The silicon carbide material has the advantages of large forbidden band width, high breakdown electric field, high saturation drift velocity and high thermal conductivity, and the excellent properties of the materials enable the materials to become ideal materials for manufacturing high-power, high-frequency, high-temperature-resistant and anti-radiation devices. The silicon carbide MOSFET device has a series of advantages of high breakdown voltage, large current density and a drive circuit similar to a silicon IGBT, so the development prospect is very wide.

Typical parameter performance indicators for silicon carbide MOSFET devices include blocking voltage, operating current, threshold voltage, and on-resistance, among others. The on-resistance is composed of a substrate resistance, a drift layer resistance, a JFET area resistance, a channel resistance, a contact resistance and the like. With the increasing performance requirements of the device, the size of the unit cell of the device is continuously reduced, so that the size of the JFET area is reduced, and the resistance of the JFET area connected in series in the device conducting circuit is continuously increased. Thus, doping the JFET region to achieve a lower resistance of the JFET region becomes a viable and efficient solution. A common JFET region doping scheme is to integrally dope the entire MOSFET active region, but this scheme introduces additional damage to other regions of the device due to unnecessary implantation processes. It is therefore desirable to achieve doping of only the JFET region where possible.

Disclosure of Invention

The invention aims to provide a self-aligned doping process for a JFET (junction field effect transistor) area of a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) device, which is used for realizing the doping of the JFET area of the device by a self-aligned process method, so that the resistance of the JFET area is reduced, and other parasitic effects are not introduced.

The technical solution for realizing the purpose of the invention is as follows: a self-aligned doping process for a JFET region of a silicon carbide MOSFET device comprises the following steps:

s1: growing and depositing a mask medium on the surface of the silicon carbide epitaxial wafer;

s2: removing the mask medium on the surface of the JFET area;

s3: carrying out n-type ion implantation on the JFET area on the surface of the silicon carbide;

s4: depositing a polycrystalline silicon mask medium on the surface of the whole silicon carbide wafer;

s5: polishing and removing the polysilicon mask medium on the surface of the wafer except the JFET area by adopting a surface flattening process;

or, the polysilicon layer on the surface of the wafer is etched integrally until SiO is etched₂Masking the surface of the medium, wherein the JFET area is reserved with a polysilicon medium;

s6: removing the previous mask medium through an etching process, and reserving a part of the mask medium by using photoresist as a mask through a photoetching process for a terminal area of the device;

s7: carrying out p-type p-well ion implantation on the surface of the silicon carbide;

s8: by self-aligned methods, i.e. covering the whole wafer with SiO₂The medium is etched and removed integrally, thereby reserving partial SiO of the side wall of the polysilicon medium₂A medium; or directly carrying out an autoxidation growth process on the polycrystalline silicon medium;

s9: carrying out n + type ion implantation on the silicon carbide surface so as to form a channel in a self-aligned manner in the p-well region;

s10: and removing all the mask media to complete the whole set of self-alignment process, and continuing the subsequent process of the SiC wafer.

Compared with the prior art, the invention has the following remarkable advantages: the invention adopts a self-aligned injection scheme for the JFET area injection process of the silicon carbide MOSFET device, and integrates the scheme into the original silicon carbide MOSFET channel self-aligned injection process; according to the scheme, the risk that the JFET area is not completely implanted or a unilateral channel is implanted to cause performance difference can be avoided while the resistance of the JFET area is effectively reduced. Meanwhile, the integration of the scheme reduces the process difficulty to a certain extent.

Drawings

FIG. 1 shows an example of the deposition of SiO mask dielectric on a SiC surface₂Schematic representation of (a).

FIG. 2 is a diagram illustrating the removal of SiO from the surface mask dielectric of the JFET area in the embodiment of the present invention₂Schematic representation of (a).

Fig. 3 is a schematic diagram of n-type ion implantation in the JFET region in an embodiment of the invention.

Fig. 4 is a schematic diagram of a blanket polysilicon layer deposited over the entire surface after completing the JFET region implantation in an embodiment of the invention.

Figure 5 is a schematic illustration of the present invention with a planarized surface to remove polysilicon dielectric outside the JFET area.

Fig. 6 is a schematic diagram of the JFET region implantation completed in the embodiment of the invention, and then a thicker polysilicon layer is deposited on the whole surface of the JFET region, so that the polysilicon layer surface of the JFET region is higher than other positions.

FIG. 7 is a diagram of SiO removing the redundant mask dielectric in the embodiment of the present invention₂Schematic representation of (a).

Fig. 8 is a schematic diagram of ion implantation to form a p-well region in an embodiment of the invention.

FIG. 9 is a diagram illustrating the formation of SiO on the sidewall of the polysilicon layer by a self-aligned process according to an embodiment of the present invention₂Schematic representation of the thin layer.

Fig. 10 is a schematic diagram of ion implantation to form n + region, p-well channel in the embodiment of the invention.

FIG. 11 is a schematic diagram of the self-aligned process completed by removing all the mask dielectric in the embodiment of the present invention.

Detailed Description

In the standard preparation process of the silicon carbide MOSFET device, a self-aligned pattern is formed by a common polysilicon mask autoxidation method, so that a p-well channel is formed by injection, the width of the channel is less than 1um, and the width of the channel is accurately controlled by accurately controlling the autoxidation time. Thus, an attempt was made to achieve the JFET region implantation process also by a self-aligned method. The self-alignment method can also avoid the risk of using a photoetching method to prepare the JFET area implantation mask, particularly, the lateral deviation causes that part of the JFET area is not implanted, or a unilateral channel is implanted to cause performance difference, and the like.

The invention provides a self-aligned doping process for a JFET (junction field effect transistor) area of a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) device, which comprises the following steps of:

s1: growing and depositing a mask medium on the surface of the silicon carbide epitaxial wafer;

s2: removing the mask medium on the surface of the JFET area through photoetching and etching (or corrosion) processes;

s3: carrying out n-type ion implantation on the JFET area on the surface of the silicon carbide;

s4: depositing a polycrystalline silicon mask medium on the surface of the whole silicon carbide wafer;

s5-1: polishing and removing the polysilicon mask medium on the surface of the wafer except the JFET area by adopting process schemes such as surface planarization (CMP), which is the core process of the whole JFET area self-aligned doping process;

s5-2: in another process scheme, when the JFET area of the silicon carbide MOSFET device is narrow and a thicker polycrystalline silicon mask medium is selected to be deposited in the step S4, the height of the polycrystalline silicon layer in the JFET area can be higher than that of the polycrystalline silicon layer at other positions of the wafer, and the polycrystalline silicon layer on the surface of the wafer can be selected to be subjected to whole etching until SiO is etched₂Masking the surface of the medium, wherein the JFET area is reserved with a polysilicon medium;

s6: removing the previous mask medium by a corrosion (or etching) process, wherein for the terminal area of the device, a part of the mask medium can be reserved by using photoresist as a mask through a photoetching process so as to ensure that the terminal of the device is not influenced by subsequent p-well injection and n + injection;

s7: carrying out p-type p-well ion implantation on the surface of the silicon carbide;

s8: then covering the whole wafer with SiO by a self-alignment method₂The medium is etched and removed integrally, thereby reserving partial SiO of the side wall of the polysilicon medium₂A medium; or directly carrying out an autoxidation growth process on the polycrystalline silicon medium;

s9: carrying out n + type ion implantation on the silicon carbide surface so as to form a channel in a self-aligned manner in the p-well region;

s10: and removing all the mask media to complete the whole set of self-alignment process, and continuing the subsequent process of the SiC wafer.

Further, in the step S1, the mask medium is preferably SiO₂SiN or Si of various compositions may be used_xN_1-xSiON and other media, the thickness of the mask medium is 0.5um to 5um, the reason is that the mask is required to be used as the mask when injecting the area outside the JFET, and meanwhile, the working efficiency is also consideredCost and difficulty of the process.

Further, in step S2, the method for removing the dielectric in the JFET region may be hydrofluoric acid (or BOE) wet etching, and at this time, a lateral etching margin with the same width needs to be left according to the thickness of the dielectric; or a dry etching process is adopted, part of the medium can be remained at the moment, the thickness is less than 500 angstroms, the silicon carbide surface is prevented from being damaged, meanwhile, the injection energy of the JFET is slightly improved, and the injection depth is ensured.

Further, in the step S3, a single implantation is formed on the JFET region through the mask dielectric, where a non-mask dielectric may be selected to be implanted entirely, or the mask dielectric may be directly removed after the implantation is completed, that is, a self-aligned process is not adopted, so that the purpose of doping the JFET region can be achieved, but an additional risk is introduced.

Further, in the step S4, the deposited polysilicon layer has a thickness of 0.5um to 5um, which is enough to meet the mask requirement for the subsequent p-well implantation.

Further, in step S5-1, the requirement for the uniformity of the surface-flattened wafer is that the polysilicon layer outside the JFET region is required to be removed to be clean within at least plus or minus 0.5um, and part of the SiO layer may be additionally subtracted₂Masking, but to ensure that the remaining (polysilicon) thickness meets the implant mask requirements.

Further, in the step S5-2, the polysilicon layer used in this scheme has a thicker thickness than SiO₂The thickness of the mask medium; the method is more suitable for the situation of a narrow JFET area, and the finger width is less than 2 um; the method of etching polysilicon in a whole wafer also requires higher polysilicon and SiO₂Etching ratio, greater than 3: 1, ensuring that no polysilicon residue exists in the non-JFET region by over-etching in a certain proportion; finally, the scheme also requires that the polysilicon layer of the JFET area still remains after the etching.

Further, in the step S6, the remaining SiO is removed₂In the process of (2), the polysilicon layer and the silicon carbide surface are not damaged. For the preparation of the device terminal structure, the invention is realized in the subsequent p + layer injection process, so that the mask medium is reserved for the terminal area by default and ions are not injected.

Further, in the steps S7-S9, a standard process for implantation formation of the p-well, the channel and the n + region of the sic is described, and the main innovation of the present invention is to put the JFET region implantation process before the process, so as to achieve self-alignment of the JFET region, the p-well and the n + region. The practical scheme flow is equivalent to aligning the JFET area by using a p-well and then aligning the p-well by using an n + area.

The technical scheme of the invention is further explained below by combining the attached drawings.

Examples

The invention discloses a self-aligned doping process method for a JFET (junction field effect transistor) area of a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) device, which comprises the following steps of:

s1: growing and depositing a mask medium on the surface of the silicon carbide epitaxial wafer, wherein the mask medium is made of SiO₂As shown in fig. 1;

s2: removing the masking medium on the surface of the JFET area, as shown in figure 2;

s3: carrying out n-type ion implantation on the JFET area on the silicon carbide surface, as shown in figure 3;

s4: depositing a polysilicon mask medium on the surface of the whole silicon carbide wafer, as shown in FIG. 4;

s5-1: by adopting a surface planarization process scheme, polishing and removing the polysilicon mask medium on the surface of the wafer except the JFET area, as shown in figure 5, which is the core process of the whole JFET area self-aligned doping process;

s5-2: in yet another process scheme, when the JFET region of the silicon carbide MOSFET device is narrow and a thick polysilicon mask medium is selectively deposited in step S4, the polysilicon layer in the JFET region can be made to have a height higher than that of the polysilicon layer at other positions of the wafer, as shown in fig. 6, and the polysilicon layer on the surface of the wafer can be selectively etched entirely until SiO is etched₂Masking the surface of the medium, wherein the JFET area is reserved with a polysilicon medium;

s6: removing the SiO of the mask medium by an etching process₂As shown in FIG. 7, in this case, for the termination region of the device, a portion of the mask dielectric can be remained by using a photoresist as a mask through a photolithography process to ensure that the device termination is not damagedThe effects of subsequent p-well and n + implants;

s7: carrying out p-type p-well ion implantation on the silicon carbide surface, as shown in FIG. 8;

s8: then covering the whole wafer with SiO by a self-alignment method₂The medium is etched and removed integrally, thereby reserving partial SiO of the side wall of the polysilicon medium₂Media, as shown in FIG. 9;

s9: performing n + type ion implantation on the silicon carbide surface, thereby forming a channel in a p-well region in a self-aligned manner, as shown in fig. 10;

s10: and removing all the mask media to finish the whole set of self-alignment process, and continuing the subsequent process of the SiC wafer as shown in FIG. 11.