阅读说明：本技术 一种提高uis能力的超结mosfet制造方法 (Super junction MOSFET manufacturing method for improving UIS capability ) 是由 秦芳莉 韩廷瑜 何云 梁路 陈会治 罗顶 于 2021-02-20 设计创作，主要内容包括：本发明涉及一种提高UIS能力的超结MOSFET制造方法,该方法首先在衬底的外延层上形成P型柱和P型体区,在形成源区之前先从注入窗口处注入高剂量的P型杂质但并不退火作业,然后按现有工艺方法注入N型杂质形成源区；由于在源区形成前注入窗口没有隔离侧墙横向遮挡,有利于高剂量被注入的P型杂质横向扩散,借助源区形成时的退火作业将第二次注入的P型杂质向深度方向推进,这样就增大了高浓度P型杂质的面积分布,有利于降低BJT的基区电阻；在源区以及栅极侧壁的隔离侧墙形成后,第三次注入高剂量的P型杂质并退火,先后第二次和第三次P型杂质的注入增加了基区的掺杂浓度,也可以令基区电阻显著降低,达到提高器件UIS能力的目的。(The invention relates to a super junction MOSFET manufacturing method for improving UIS capability, which comprises the steps of firstly forming a P-type column and a P-type body region on an epitaxial layer of a substrate, injecting high-dose P-type impurities from an injection window without annealing operation before forming a source region, and then injecting N-type impurities according to the existing process method to form the source region; because the injection window is not transversely shielded by the isolation side wall before the source region is formed, the high-dose injected P-type impurities can be transversely diffused, and the second-time injected P-type impurities are pushed to the depth direction by virtue of the annealing operation during the formation of the source region, so that the area distribution of the high-concentration P-type impurities is increased, and the base region resistance of the BJT can be reduced; after the isolation side walls of the source region and the side wall of the grid electrode are formed, high-dose P-type impurities are injected for the third time and annealed, the doping concentration of the base region is increased by injecting the P-type impurities for the second time and the third time, the resistance of the base region can be obviously reduced, and the purpose of improving the UIS (integrated optical system) capability of the device is achieved.)

1. A super junction MOSFET manufacturing method for improving UIS capability is characterized in that: the method comprises the following steps:

step 1: forming a second conductive type epitaxial layer on the surface of the second conductive type substrate, and forming a plurality of spaced first conductive type columns extending from the surface to the depth direction in the second conductive type epitaxial layer;

step 2: sequentially forming a gate oxide layer and a polycrystalline silicon layer on the surface of the second conductive type epitaxial layer, etching the polycrystalline silicon layer to form a grid, forming a first injection window between adjacent grids, and performing first-time injection of first conductive type impurities through the first injection window and first-time annealing to form a first conductive type body region;

and step 3: implanting the first conductive type impurity for the second time through the first implantation window without performing an annealing operation;

and 4, step 4: coating photoresist and forming a photoresist pattern, wherein the photoresist pattern and the side wall of the grid electrode form a second injection window, injecting second conductive type impurities through the second injection window and carrying out second annealing to form a source region, and the second annealing enables the second injected first conductive type impurities to be diffused;

and 5: removing the photoresist;

step 6: forming an isolation side wall on the side wall of the grid;

and 7: forming a metal electrode.

2. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 1 wherein: and forming a third injection window between the isolation side walls on the two sides of the first injection window in the step 6, and injecting the first conductive type impurities for the third time through the third injection window and carrying out third annealing.

3. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 2 wherein: the third-time injected first conductivity type impurity concentration is greater than or equal to the second-time injected first conductivity type impurity concentration.

4. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 1 wherein: the second implantation has a higher concentration of the first conductive type impurity than the first implantation.

5. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 1 wherein: the doping concentration of the second conduction type epitaxial layer is lower than that of the second conduction type substrate.

6. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 1 wherein: the second conductive type substrate is an N-type silicon substrate, the second conductive type epitaxial layer is an N-type silicon epitaxial layer, and the first conductive type is a P type.

7. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 1 wherein: the isolation side wall is a silicon oxide layer.

8. A method of manufacturing a super junction MOSFET to increase UIS capability of claim 2 wherein: the implantation energy of the second implantation of the first conductive type impurities is less than that of the first implantation of the first conductive type impurities, and the implantation energy of the third implantation of the first conductive type impurities is less than that of the second implantation of the first conductive type impurities.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a super junction MOSFET manufacturing method for improving UIS (ultra-junction metal oxide semiconductor field effect transistor) capability.

Background

UIS (unshielded Inductive switching), that is, "unclamped Inductive load switching process", UIS capability is an important index for measuring reliability of power devices. It is required for the power device to have a high avalanche tolerance in UIS, i.e., a high capability of resisting UIS avalanche breakdown, because the energy stored in the inductive load under UIS condition is required to be fully released by the power MOS transistor when being turned off, and then the high current stress in the circuit easily causes the device to fail.

Research shows that a natural parasitic triode (BJT) is arranged in the MOSFET, taking an N-type MOSFET as an example, an N-type epitaxial layer, a P + active region and an N + active region form an NPN-type triode, and the P + active region positioned between the N-type epitaxial layer and the N + active region is used as a base region of the triode. As can be seen from the research and analysis of UIS failure modes and mechanisms, one of the reasons for avalanche damage to the device UIS is the damage caused by the conduction of the parasitic BJT. The opening of the parasitic BJT can continuously amplify avalanche breakdown current in the device, so that junction temperature is increased, and finally the device is burnt out and fails. Therefore, suppressing the parasitic BJT from turning on is an important measure to improve the reliability of the power MOSFET.

The super junction MOSFET device is an important power device appearing in recent years, the basic principle of the super junction MOSFET device is a charge balance principle, and the compromise relation between the on-resistance and the breakdown voltage of a common MOSFET is greatly improved by introducing a super junction structure of a P column and an N column which are spaced in a drift region of the common power MOSFET. The UIS failure resistance is also an important index for evaluating the reliability of a super-junction MPSFET device, and the common mode for improving the UIS failure resistance of the super-junction MOSFET is to reduce the base resistance of a parasitic BJT (bipolar junction transistor), namely, the resistance of a P-body region (P-body) under an N + source region of a power MOSFET is reduced by injecting high-energy boron or deeply diffusing, and the injected high-energy boron forms a P + deep body region in the P-body region, so that the base resistance of the parasitic BJT is reduced, and the starting of the parasitic BJT is inhibited.

When the base resistance is reduced, increasing the doping concentration and area of the P + deep body region is an effective method, but usually the P + deep body region is formed after forming an isolation side wall (usually, the isolation side wall is referred to as Spacer for short) on the side wall of the gate, due to the existence of the Spacer, an injection window becomes small, the lateral extension of the P + deep body region is limited under the influence of the lateral size of the Spacer, the area of the P + deep body region cannot reach an ideal state, and thus the UIS capability of the super-junction MOSFET is limited. In view of the above, the inventor has improved the manufacturing process of the super junction MOSFET, and eliminated the influence of Spacer lateral dimension by process adjustment, so that the UIS capability is improved, and thus the present application is brought forward.

Disclosure of Invention

The invention discloses a super-junction MOSFET manufacturing method for improving UIS capability, which improves the UIS capability of a super-junction MOSFET on the premise of not changing the area of a device and not influencing other parameters of the super-junction MOSFET.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a super junction MOSFET manufacturing method for improving UIS capability comprises the following steps:

step 1: forming a second conductive type epitaxial layer on the surface of the second conductive type substrate, and forming a plurality of spaced first conductive type columns extending from the surface to the depth direction in the second conductive type epitaxial layer;

step 2: sequentially forming a gate oxide layer and a polycrystalline silicon layer on the surface of the second conductive type epitaxial layer, etching the polycrystalline silicon layer to form a grid, forming a first injection window between adjacent grids, and performing first-time injection of first conductive type impurities through the first injection window and first-time annealing to form a first conductive type body region;

and step 3: implanting the first conductive type impurity for the second time through the first implantation window without performing an annealing operation;

and 4, step 4: coating photoresist and forming a photoresist pattern, wherein the photoresist pattern and the side wall of the grid electrode form a second injection window, injecting second conductive type impurities through the second injection window and carrying out second annealing to form a source region, and the second annealing enables the second injected first conductive type impurities to be diffused;

and 5: removing the photoresist;

step 6: and forming an isolation side wall on the side wall of the grid.

Further, a third injection window is formed between the isolation side walls on the two sides of the first injection window in the step 6, and the first conductive type impurity is injected for the third time through the third injection window and third annealing is performed.

Further, the third implantation concentration of the first conductive type impurities is greater than or equal to the second implantation concentration of the first conductive type impurities.

Further, the concentration of the second-time implanted first conductive type impurities is higher than that of the first-time implanted first conductive type impurities.

Further, the doping concentration of the second conductive type epitaxial layer is lower than that of the second conductive type substrate.

Further, the second conductive type substrate is an N-type silicon substrate, the second conductive type epitaxial layer is an N-type silicon epitaxial layer, and the first conductive type is a P-type.

Further, the isolation side wall is a silicon oxide layer.

Further, the implantation energy of the second implantation of the first conductive type impurity is less than that of the first implantation, and the implantation energy of the third implantation of the first conductive type impurity is less than that of the second implantation of the first conductive type impurity.

According to the super junction MOSFET manufacturing method disclosed by the invention, after the first conductive type impurity is injected for the first time and annealed to form the P-type body region, the ion injection of the source region is not carried out, but the second first conductive type impurity injection is carried out through the first injection window, and the annealing operation is not carried out, at the moment, the isolation side wall of the grid side wall is not formed yet, and the transverse shielding cannot be formed, the first injection window is larger, so that the transverse distribution of the second injected first conductive type impurity is facilitated, the second injected first conductive type impurity is diffused by the annealing operation during the formation of the source region, the distribution area of the high-concentration first conductive impurity is increased, and the resistance of a parasitic BJT base region is facilitated to be reduced; in the invention, the doping concentration of the parasitic BJT base region is further increased by injecting the first conductive type impurities twice in sequence when the P-type body region is formed, and the resistance of the parasitic BJT base region can also be obviously reduced. The manufacturing method disclosed by the invention is designed on the premise of not changing the area of the device and not increasing the annealing operation times, and achieves the purposes of reducing the resistance of the base region of the parasitic BJT, not obviously increasing the manufacturing cost and improving the UIS capability of the super-junction MOSFET device.

Drawings

FIG. 1 is a schematic view of the device structure after the P-pillar and P-type body regions are completed by the manufacturing method of the present invention;

FIG. 2 is a schematic view of the device structure after the second implantation of P-type impurities;

FIG. 3 is a schematic diagram of the device structure after forming an N-type source region;

FIG. 4 is a schematic view of the device structure after the third P-type impurity implantation;

fig. 5 is a flowchart of a super junction MOSFET manufacturing method in an embodiment of the invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

The embodiment discloses a super junction MOSFET manufacturing method for improving UIS capability, wherein part of the conventional process links for manufacturing the super junction MOSFET in the prior art are omitted, and the embodiment only focuses on the process links related to the invention purpose. The superjunction MOSFET mentioned in this embodiment is a planar gate deep trench superjunction MOSFET, and its manufacturing process is shown in fig. 5, and device structures formed at different stages in the manufacturing process are shown in fig. 1 to 4.

First, a semiconductor substrate 1 is selected, and then an epitaxial layer 2 having the same conductivity type as that of the substrate 1 is formed on the surface of the substrate 1, the doping concentration of the epitaxial layer 2 is lower than that of the substrate 1, and in this embodiment, an N-type silicon substrate and an N-type silicon epitaxial layer are selected as an example for explanation. The manufacturing method of the plane gate deep groove super junction MOSFET comprises the following steps:

step 1): forming a P-type pillar.

An N-type epitaxial layer is formed on the surface of a substrate 1, and a plurality of P-type columns 3 are formed in the N-type epitaxial layer at intervals extending in the depth direction from the surface.

In this embodiment, the P-type pillar 3 does not penetrate through the N-type epitaxial layer, and the P-type pillar may be formed by conventional deep trench epitaxial filling or multiple epitaxial implantation of a P-type region on the substrate 1 by annealing, both of which are conventional processes in the art and are not described herein.

Step 2): and carrying out first injection of P-type impurities to form a body region.

Sequentially forming a gate oxide layer and a polysilicon layer on the surface of the N-type epitaxial layer, etching the polysilicon layer to form a grid 5, forming a first injection window 11 between adjacent grids 5, injecting P-type impurities for the first time through the first injection window 11, and annealing for the first time to form a P-type body region 4.

In the embodiment, the width of the first implantation window 11 is the same as that of the P-type column, but the invention is not limited thereto, and the width of the first implantation window may be slightly larger or smaller than that of the P-type column according to the arrangement of the device structure, and preferably, the implantation energy of the first P-type impurity is 60kev to 100 kev.

The steps 1) to 2) are conventional process procedures of the conventional planar gate deep groove super junction MOSFET, and the structure of the device after the steps are completed is shown in FIG. 1. According to the existing manufacturing method, the formation process of the N-type source region is required to be carried out, and the subsequent process steps are adjusted, namely before the source region is formed, the doping concentration of the P-type body region 4 is further improved by ion implantation of high-concentration P-type impurities, and the subsequent steps are as follows:

step 3): and carrying out second P-type impurity injection without annealing operation.

After the P-type body region 4 is formed, P-type impurities are implanted for the second time through the first implantation window 11, preferably, the implantation energy of the P-type impurities for the second time is less than that of the P-type impurities for the first time, preferably, the implantation energy of the P-type impurities for the second time is 40-80 kev, and preferably, the concentration of the P-type impurities implanted in the second time is higher than that of the P-type impurities implanted in the first time. After the P-type impurity is injected for the second time, annealing operation is not performed, so that the cost increase caused by increasing the annealing times is avoided, the influence on device parameters caused by additionally increasing the thermal process is also avoided, and the structure of the device after the step is completed is shown in fig. 2.

The first injection window 11 is selected to inject the high-concentration P-type impurity, considering that the isolation side wall 9 is not formed on the side wall of the gate 5 at the moment, the first injection window 11 has a large transverse size and is not transversely shielded, so that the transverse expansion of the injected high-concentration P-type impurity in subsequent annealing is facilitated, and even if the longitudinal advancing depth of the high-concentration P-type impurity is kept unchanged under the original process condition, compared with the existing process, the area of the finally formed second injection P-type impurity region 6 is increased, so that the resistance of the parasitic BJT in the super junction MOSFET is reduced. In addition, in this embodiment, the purpose of improving the device UIS is achieved by the first implantation window 11 of the P-type body region 4, and it is also considered that a process of forming an implantation window is not additionally added, so that a method of intentionally enlarging an implantation window is not adopted, and it is considered that the area of the original device is not changed and the characteristic parameters of the device are not affected.

Step 4): and implanting N-type impurities and annealing to form a source region.

And coating a photoresist 7 and forming a photoresist pattern, wherein the photoresist pattern and the side wall of the grid electrode form a second injection window 12, injecting N-type impurities through the second injection window 12 and carrying out second annealing to form a source region 8, and the second annealing enables the second injected P-type impurities to be diffused. The device structure after this step is shown in fig. 3.

The second injection window may be specifically formed by coating the photoresist 7 on the entire surface of the wafer, and at this time, the first injection window 11 is also filled with the photoresist 7, and needs to be removed by a photolithography method, that is, only the photoresist 7 located in the middle of the first injection window 11 is remained, the photoresists 7 on both sides are completely removed, and the second injection window 12 is formed between the photoresist 7 in the middle and the sidewalls of the gates 5 on both sides.

Step 5): and forming an isolation side wall on the side wall of the grid.

Step 5.1): and removing the photoresist.

The photoresist 7 on the surface of the gate 5 is removed together with the photoresist 7 remaining at the first implantation window 11.

Step 5.2): and forming an isolation side wall on the side wall of the grid.

Isolation layers are formed on the surface and the side wall of the gate 5, the isolation layer on the side wall of the gate 5 serves as an isolation side wall 9, and the isolation side wall 9 in this embodiment is a silicon oxide layer. In the existing plane gate super junction MOSFET technology, high-concentration P-type impurities are doped after the isolation side wall 9 is formed, so that the concentration of a P-type body region 4 is improved, and because the lateral distribution of the injected high-concentration P-type impurities is blocked due to the lateral shielding of the isolation side wall 9, the improvement effect of the existing technology on the UIS capacity of a device is not ideal. The invention has completed the injection link of the high concentration P-type impurity before the formation of the source region 8, and after the step 5) is completed, the conventional process is to form a metal contact hole region and deposit a metal layer on the metal contact hole region so as to form a metal electrode. However, the purpose of the present invention is to improve UIS capability of the device, and therefore, after step 5) is performed, the third implantation of high concentration P-type impurities is performed, i.e., step 6) is performed before the metal electrode is formed.

Step 6): and implanting and annealing the P-type impurity for the third time.

After the isolation side walls 9 are formed, third injection windows 13 are formed between the isolation side walls 9 on the two sides of the first injection window 11, and P-type impurities are injected for the third time through the third injection windows 13 and annealing is carried out for the third time. And forming a third-time-implanted P-type impurity region 10 in the second-time-implanted P-type impurity region 6, wherein the implantation energy of the third-time P-type impurity is preferably less than that of the second-time P-type impurity, the implantation energy of the third-time P-type impurity is preferably 30-60 kev, and the concentration of the third-time-implanted P-type impurity is preferably greater than or equal to that of the second-time-implanted P-type impurity. And diffusing the third implanted P-type impurity through third annealing. The invention can further improve the doping concentration and the area of the P-type impurity distribution region through three times of injection of the high-concentration P-type impurity, and can further reduce the base resistance of the parasitic BJT, so that the UIS capability improvement effect of the device becomes obvious. The device structure after this step is completed is shown in fig. 4.

Step 7): the metal electrode formation is completed according to the existing process.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.