阅读说明：本技术 一种用于延迟锁相环的鉴频鉴相器 (Phase frequency detector for delay phase-locked loop ) 是由 王欢 黎飞 苗澎 王聪 于 2020-12-16 设计创作，主要内容包括：本发明公开了一种用于延迟锁相环的鉴频鉴相器,包括充电模块、放电模块、时钟模块；充电模块的输入端接有DLL环路参考时钟CLK-REF、数字控制信号RST,输出端为高电平脉冲UP、低电平脉冲UPN；放电模块的输入端接有DLL环路反馈时钟CLK-FB、数字控制信号RST,输出端为高电平脉冲DOWN、低电平脉冲DOWNN；时钟模块的输入端分别接入DLL环路参考时钟CLK-REF、DLL环路反馈时钟CLK-FB,输出端第一反相时钟REF-N、第一正相时钟REF-P分别与充电模块相连,第二反相时钟FB-N、第二正相时钟FB-P分别与放电模块相连。本发明实现了对延迟一个周期的延迟锁相环完成了鉴相。(The invention discloses a phase frequency detector for a delay locked loop, which comprises a charging module, a discharging module and a clock module, wherein the charging module is used for charging a phase of a phase locked loop; the input end of the charging module is connected with a DLL loop reference clock CLK _ REF and a digital control signal RST, and the output end of the charging module is a high-level pulse UP and a low-level pulse UPN; the input end of the discharging module is connected with a DLL loop feedback clock CLK _ FB and a digital control signal RST, and the output end of the discharging module is a high-level pulse DOWN and a low-level pulse DOWNNN; the input end of the clock module is respectively connected with a DLL loop reference clock CLK _ REF and a DLL loop feedback clock CLK _ FB, the output end of the clock module is respectively connected with a first reverse phase clock REF _ N and a first normal phase clock REF _ P, and the output end of the clock module is respectively connected with a charging module, and the second reverse phase clock FB _ N and the second normal phase clock FB _ P are respectively connected with a discharging module. The invention realizes the phase discrimination of the delay phase-locked loop which delays one period.)

1. A phase frequency detector for a delay locked loop, comprising: the device comprises a charging module (1), a discharging module (2) and a clock module (3); wherein:

the input end of the charging module (1) is connected with a DLL loop reference clock CLK _ REF and a digital control signal RST, the output end of the charging module (1) is a high-level pulse UP and a low-level pulse UPN, and the high-level pulse UP and the low-level pulse UPN are respectively connected with a charge pump;

the input end of the discharging module (2) is connected with a DLL loop feedback clock CLK _ FB and a digital control signal RST, the output end of the discharging module (2) is a high-level pulse DOWN and a low-level pulse DOWNNN, and the high-level pulse DOWN and the low-level pulse DOWNNN are respectively connected with a charge pump;

the input end of the clock module (3) is respectively connected with a DLL loop reference clock CLK _ REF and a DLL loop feedback clock CLK _ FB, the output end of the clock module (3) is a first reverse phase clock REF _ N, a first normal phase clock REF _ P, a second reverse phase clock FB _ N and a second normal phase clock FB _ P, the first reverse phase clock REF _ N and the first normal phase clock REF _ P are respectively connected with the charging module (1), and the second reverse phase clock FB _ N and the second normal phase clock FB _ P are respectively connected with the discharging module (2).

2. A phase frequency detector for a delay locked loop as claimed in claim 1, wherein: the charging module (1) comprises a first D flip-flop DFF1, a second D flip-flop DFF2, a first Delay inverter Delay1 AND a first AND gate 1; wherein:

the signal of the DLL loop reference clock CLK _ REF at the input terminal of the charging module (1) is input to the CLK terminal of the first D flip-flop DFF1, the output Q terminal of the first D flip-flop DFF1 is connected to the input terminal of the first Delay inverter Delay1, the output terminal of the first Delay inverter Delay1 is connected to the Reset terminal of the first D flip-flop DFF1 AND one input terminal of the first AND gate 1, the other input terminal of the first AND gate AND1 is connected to the external input signal RST, the output terminal of the first AND gate AND1 is connected to the Reset terminal of the second D flip-flop DFF2, AND the output terminal of the second D flip-flop DFF2 is connected to the first transmission gate TG1, wherein the output terminal Q of the second D flip-flop DFF2 is connected to the positive enable signal terminal of the first transmission gate TG1, AND the output terminal QN of the second D flip-flop DFF2 is connected to the negative enable signal terminal of the first transmission gate TG 1.

3. A phase frequency detector for a delay locked loop as claimed in claim 1, wherein: the discharging module (2) comprises a third D flip-flop DFF3, a fourth D flip-flop DFF4, a second Delay inverter Delay2 AND a second AND gate 2; wherein:

the DLL loop feedback clock CLK _ FB signal at the input terminal of the clock module (3) is input to the CLK terminal of the third D flip-flop DFF3, the output Q terminal of the third D flip-flop DFF3 is connected to the input terminal of the second Delay inverter Delay2, the output terminal of the second Delay inverter Delay2 is connected to the Reset terminal of the third D flip-flop DFF3 AND one input terminal of the second AND gate AND2, the other input terminal of the second AND gate 2 is connected to the external input signal RST2, the output terminal of the second AND gate AND2 is connected to the Reset terminal of the fourth D flip-flop DFF4, AND the output terminal of the fourth D flip-flop DFF4 is connected to the second transmission gate TG2, wherein the output terminal Q of the fourth D flip-flop DFF4 is connected to the positive enable signal terminal of the second transmission gate TG2, AND the output terminal QN of the fourth D flip-flop DFF4 is connected to the negative enable signal terminal of the second transmission gate TG 2.

4. A phase frequency detector for a delay locked loop as claimed in claim 1, wherein: the clock module (3) comprises four inverters, namely a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV 4; wherein:

the first inverter INV1 and the third inverter INV3 shape the input clock, the first inverter INV1 and the third inverter INV3 output clock pulses REF _ N and FB _ N to the D terminal of the second D flip-flop DFF2 of the charging module (1), the input terminal of the second inverter INV2 of the clock module (3), the D terminal of the fourth D flip-flop DFF4 of the discharging module (2), and the input terminal of the fourth inverter INV4 of the clock module (3), and the second inverter INV2 and the fourth inverter INV4 output pulses REF _ P to the CLK terminal of the fourth D flip-flop DFF4 of the discharging module (2) and the CLK terminal of the second D flip-flop DFF2 of the charging module (1).

5. A delay locked loop, characterized by: comprising a phase frequency detector according to any one of claims 1 to 4.

Technical Field

The invention belongs to the field of semiconductor integrated circuits, and particularly relates to the field of delay locked loop phase frequency detector circuits.

Background

A Phase Frequency Detector (PFD) is a circuit that can compare phase differences and convert them into pulse signals with adjustable pulse widths. The phase difference between the reference frequency signal and the output signal of the frequency divider is compared, the width of the pulse signal is used for representing the magnitude of the phase difference, and the output pulse signal is converted into the charge-discharge current on the loop filter. Two design indexes of phase discrimination range and phase discrimination precision are mainly concerned in the design process of the frequency and phase discriminator. Firstly, the phase discrimination is ensured to have no dead zone, and the phase discrimination range is improved as much as possible on the premise of meeting the condition. In order to meet the design requirements, a suitable circuit design structure needs to be selected.

For a classical PFD architecture, as shown in fig. 1, the circuit consists of two D flip-flops, an and gate, a delay unit for eliminating dead zones, and a buffer circuit for driving a charge pump. fref and DIV are respectively a reference clock signal and a frequency divider output signal, when any one of the two rises, the corresponding D flip-flop is set to be 1, and when both the two flip-flops are set to be 1, the Reset end Reset of the D flip-flop is effective. When fref and DIV are in the same frequency and phase, the UP end and the DW end of the PFD output pulse signals with the same pulse width, so that the charge and discharge switches of the CP are simultaneously turned on, and the current output by the CP is still zero. A problem with such a circuit is that the phase detection range, which is shown in fig. 2, is not satisfactory for a delay locked loop.

Therefore, the classic structure can only control the charge pump to charge and discharge within the phase difference of (-2 pi, 2 pi), but the delay locked loop needs to charge and discharge the charge pump within the phase difference of (pi, 3 pi), the classic PFD structure can only charge within the phase difference, the phase discrimination range does not meet the design requirement of the DLL, and the technical problem to be solved by technical personnel in the field is urgently needed.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide the phase frequency detector for the delay locked loop, which realizes phase detection of the delay locked loop delaying for one period by utilizing a method for comparing a reference clock in a DLL loop with a loop feedback clock, and has the advantages of simple circuit structure and easy realization.

In order to achieve the purpose, the invention adopts the technical scheme that:

a phase frequency detector for a delay locked loop comprises a charging module, a discharging module and a clock module; wherein:

the input end of the charging module is connected with a DLL loop reference clock CLK _ REF and a digital control signal RST, the output end of the charging module is a high-level pulse UP and a low-level pulse UPN, and the high-level pulse UP and the low-level pulse UPN are respectively connected with the charge pump;

the input end of the discharging module is connected with a DLL loop feedback clock CLK _ FB and a digital control signal RST, the output end of the discharging module is a high-level pulse DOWN and a low-level pulse DOWNN, and the high-level pulse DOWN and the low-level pulse DOWNN are respectively connected with a charge pump;

the input end of the clock module is respectively connected with a DLL loop reference clock CLK _ REF and a DLL loop feedback clock CLK _ FB, the output end of the clock module is a first reverse phase clock REF _ N, a first normal phase clock REF _ P, a second reverse phase clock FB _ N and a second normal phase clock FB _ P, the first reverse phase clock REF _ N and the first normal phase clock REF _ P are respectively connected with the charging module, and the second reverse phase clock FB _ N and the second normal phase clock FB _ P are respectively connected with the discharging module.

The charging module comprises a first D flip-flop DFF1, a second D flip-flop DFF2, a first Delay inverter Delay1 AND a first AND gate AND 1; wherein:

the signal of the DLL loop reference clock CLK _ REF at the input terminal of the charging module is input to the CLK terminal of the first D flip-flop DFF1, the output Q terminal of the first D flip-flop DFF1 is connected to the input terminal of the first Delay inverter Delay1, the output terminal of the first Delay inverter Delay1 is connected to the Reset terminal of the first D flip-flop DFF1 AND one input terminal of the first AND gate AND1, the other input terminal of the first AND gate 1 is connected to the external input signal RST, the output terminal of the first AND gate AND1 is connected to the Reset terminal of the second D flip-flop DFF2, AND the output terminal of the second D flip-flop DFF2 is connected to the first transmission gate TG1, wherein the output terminal Q of the second D flip-flop DFF2 is connected to the positive enable signal terminal of the first transmission gate TG1, AND the output terminal QN of the second D flip-flop DFF2 is connected to the negative enable signal terminal of the first transmission gate TG 1.

The discharging module comprises a third D flip-flop DFF3, a fourth D flip-flop DFF4, a second Delay inverter Delay2 AND a second AND gate AND 2; wherein:

the DLL loop feedback clock CLK _ FB signal at the input terminal of the clock module is input to the CLK terminal of the third D flip-flop DFF3, the output Q terminal of the third D flip-flop DFF3 is connected to the input terminal of the second Delay inverter Delay2, the output terminal of the second Delay inverter Delay2 is connected to the Reset terminal of the third D flip-flop DFF3 AND one input terminal of the second AND gate 2, the other input terminal of the second AND gate 2 is connected to the external input signal RST, the output terminal of the second AND gate 2 is connected to the Reset terminal of the fourth D flip-flop DFF4, AND the output terminal of the fourth D flip-flop DFF4 is connected to the second transmission gate TG2, wherein the output terminal Q of the fourth D flip-flop DFF4 is connected to the positive enable signal terminal of the second transmission gate TG2, AND the output terminal QN of the fourth D flip-flop DFF4 is connected to the negative enable signal terminal of the second transmission gate TG 2.

The clock module comprises four inverters, namely a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV 4; wherein:

the first inverter INV1 and the third inverter INV3 shape an input clock, the first inverter INV1 and the third inverter INV3 output clock pulses REF _ N and FB _ N to the D terminal of the second D flip-flop DFF2 of the charging module, the input terminal of the second inverter INV2 of the clock module, the D terminal of the fourth D flip-flop DFF4 of the discharging module, and the input terminal of the fourth inverter INV4 of the clock module, and the second inverter INV2 and the fourth inverter INV4 output pulse REF _ P to the CLK terminal of the fourth D flip-flop DFF4 of the discharging module and the CLK terminal of the second D flip-flop DFF2 of the charging module.

Another object of the present invention is to provide a delay locked loop including the phase frequency detector.

Has the advantages that: according to the phase frequency detector for the delay locked loop, the clock module integrates the reference clock CLK _ REF and the feedback clock CLK _ FB of the DLL loop, and then outputs the reversed phase REF _ N, the normal phase REF _ P, the reversed phase FB _ N and the normal phase FB _ P to the charging module and the discharging module, so that the PFD can control the CP to charge and discharge the filter capacitor within (pi, 3 pi) of the phase difference, and no phase detection dead zone exists.

Drawings

Fig. 1 is a schematic diagram of a phase frequency detector of a phase locked loop in the prior art;

fig. 2 is a schematic diagram of a phase detection range of a phase-locked loop phase frequency detector in the prior art;

FIG. 3 is a schematic diagram of a phase frequency detector suitable for use in a delay locked loop according to the present invention;

fig. 4 shows the relationship between the phase detection range of the phase frequency detector and the control of the charge and discharge of the charge pump.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

As shown in fig. 3, a phase frequency detector for a delay locked loop includes a charging module 1, a discharging module 2, and a clock module 3; wherein:

the input end of the charging module 1 is connected with a DLL loop reference clock CLK _ REF and a digital control signal RST, the output end of the charging module 1 is a high-level pulse UP and a low-level pulse UPN, and the high-level pulse UP and the low-level pulse UPN are respectively connected with a charge pump;

the input end of the discharging module 2 is connected with a DLL loop feedback clock CLK _ FB and a digital control signal RST, the output end of the discharging module 2 is a high-level pulse DOWN and a low-level pulse DOWNN, and the high-level pulse DOWN and the low-level pulse DOWNN are respectively connected with a charge pump;

the input end of the clock module 3 is respectively connected to the DLL loop reference clock CLK _ REF and the DLL loop feedback clock CLK _ FB, the output end of the clock module 3 is a first reverse phase clock REF _ N, a first normal phase clock REF _ P, a second reverse phase clock FB _ N and a second normal phase clock FB _ P, the first reverse phase clock REF _ N and the first normal phase clock REF _ P are respectively connected to the charging module 1, and the second reverse phase clock FB _ N and the second normal phase clock FB _ P are respectively connected to the discharging module 2.

The charging module 1 comprises a first D flip-flop DFF1, a second D flip-flop DFF2, a first Delay inverter Delay1, a first AND gate AND 1; wherein: the signal of the DLL loop reference clock CLK _ REF at the input terminal of the charging module 1 is input to the CLK terminal of the first D flip-flop DFF1, the output Q terminal of the first D flip-flop DFF1 is connected to the input terminal of the first Delay inverter Delay1, the output terminal of the first Delay inverter Delay1 is connected to the Reset terminal of the first D flip-flop DFF1 AND one input terminal of the first AND gate AND1, the other input terminal of the first AND gate 1 is connected to the external input signal RST, the output terminal of the first AND gate AND1 is connected to the Reset terminal of the second D flip-flop DFF2, AND the output terminal of the second D flip-flop DFF2 is connected to the first transmission gate TG1, wherein the output terminal Q of the second D flip-flop DFF2 is connected to the positive enable signal terminal of the first transmission gate TG1, AND the output terminal QN of the second D flip-flop DFF2 is connected to the negative enable signal terminal of the first transmission gate TG 1.

The discharging module 2 comprises a third D flip-flop DFF3, a fourth D flip-flop DFF4, a second Delay inverter Delay2, AND a second AND gate AND 2; wherein: the DLL loop feedback clock CLK _ FB signal at the input terminal of the clock module 3 is input to the CLK terminal of the third D flip-flop DFF3, the output Q terminal of the third D flip-flop DFF3 is connected to the input terminal of the second Delay inverter Delay2, the output terminal of the second Delay inverter Delay2 is connected to the Reset terminal of the third D flip-flop DFF3 AND one input terminal of the second AND gate 2, the other input terminal of the second AND gate 2 is connected to the external input signal RST, the output terminal of the second AND gate 2 is connected to the Reset terminal of the fourth D flip-flop DFF4, AND the output terminal of the fourth D flip-flop DFF4 is connected to the second transmission gate TG2, wherein the output terminal Q of the fourth D flip-flop DFF4 is connected to the positive enable signal terminal of the second transmission gate TG2, AND the output terminal QN of the fourth D flip-flop DFF4 is connected to the negative enable signal terminal of the second transmission gate TG 2.

The clock module 3 includes four inverters, namely a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV 4; wherein: the first inverter INV1 and the third inverter INV3 shape the input clock, the first inverter INV1 and the third inverter INV3 output clock pulses REF _ N and FB _ N to the D terminal of the second D flip-flop DFF2 of the charging module 1, the D terminal of the second inverter INV2 of the clock module 3, the D terminal of the fourth D flip-flop DFF4 of the discharging module 2, and the fourth inverter INV4 of the clock module 3, and the second inverter INV2 and the fourth inverter INV4 output pulse REF _ P to the CLK terminal of the fourth D flip-flop DFF4 of the discharging module 2 and the CLK terminal of the second D flip-flop DFF2 of the charging module 1.

Correspondingly, the invention also provides a delay phase-locked loop which comprises the phase frequency detector.

In the phase frequency detector, a classical PFD structure is divided into two parts, wherein one part is used for controlling a charge switch of a charge pump, and the other part is used for controlling a discharge switch of the charge pump; in addition, the D end of the D trigger in the PFD with the traditional structure is connected with a constant voltage '1', and the D end input which is specially considered is adopted by the phase frequency detector in the invention for the purpose of charging and discharging.

When the charge pump needs to be charged, the terminal D of the second D flip-flop DFF2 triggering the charge pump to be charged in the phase frequency detector is the inverted signal REF _ N of the reference clock, and the clock terminal of the second D flip-flop DFF2 is connected to the clock FB _ P of the feedback clock passing through the two inverters, by such a connection, it is obtained that only when the phase difference between CLK _ FB and CLK _ REF is within ((2k-1) pi, 2k pi), the second D flip-flop DFF2 will trigger the high level to open the first transmission gate TG1, since the D terminal of the fourth D flip-flop DFF4 is FB _ N, the CLK terminal is REF _ P, therefore, the fourth D flip-flop DFF4 still outputs 0 at the Q terminal when the rising edge of the CLK terminal triggers, does not open the second transmission gate TG2, therefore, when the phase difference between CLK _ FB and CLK _ REF is within ((2k-1) pi and 2k pi), the phase frequency detector controls the charge pump to charge.

When the charge pump needs to discharge, the D terminal of the fourth D flip-flop DFF4 triggering the charge pump to discharge in the phase frequency detector is the inverted signal FB _ N of the feedback clock, and the CLK terminal of this fourth D flip-flop DFF4 is clocked into the clock REF _ P of the reference clock through two inverters, by such a connection, it is obtained that only when the phase difference between CLK _ FB and CLK _ REF is within (2k pi, (2k +1) pi), the fourth D flip-flop DFF4 will trigger the high level to open the second transmission gate TG2, since the D terminal of the second D flip-flop DFF2 is REF _ N, the CLK terminal is FB _ P, therefore, the second D flip-flop DFF2 still outputs 0 at the Q terminal when the rising edge of the CLK terminal triggers, does not open the first transmission gate TG1, therefore, when the phase difference between CLK _ FB and CLK _ REF is within (2k pi, (2k +1) pi), the phase frequency detector will control the charge pump to discharge.

Within the phase discrimination range (pi, 3 pi) required by the delay phase-locked loop, the phase frequency detector controls the CP to be charged to increase the VCDL delay when the phase difference is within (pi, 2 pi), and the phase frequency detector controls the CP to be discharged to decrease the VCDL delay when the phase difference is within (2 pi, 3 pi).

Through delaying the first inverter Delay1, second inverter Delay2 for the phase frequency detector outputs two pairs of pulses the same, makes the charge pump open or close simultaneously, can eliminate the phase discrimination dead zone of phase difference when 2 pi after the Delay phase-locked loop locks.

In the above example, the first Delay inverter Delay1 is used to change the RST11 output from the first Delay inverter Delay1 from high to low after a Delay occurs after a high level is triggered at the rising edge of the CLK end of the first D flip-flop, AND the low level resets the Reset end of the first D flip-flop DFF1 to zero, so that the first D flip-flop DFF1 generates a high level pulse signal, AND further the RST11 generates a low level pulse signal after the first Delay inverter Delay1, one end of the first AND gate 1 is connected to the RST11, the other end of the first AND gate is connected to an enable signal RST, AND the RST is constant to 1 after the frequency detector starts to operate, so that the RST12 output from the first AND gate 1 will output a low level pulse signal. After the delay locked loop completes locking, CLK _ FB is delayed by one clock cycle from CLK _ REF, so that CLK _ FB and CLK _ REF trigger simultaneously, and further, in order to eliminate the phase detection dead zone of the phase frequency detector after the delay locked loop is locked, the falling edge of RST12 is delayed from the rising edge of FB _ P, so that a high level pulse is generated at the Q terminal of the second D flip-flop DFF 2. The second Delay inverter Delay2 is used to make the output RST21 of the second Delay inverter Delay2 change from high level to low level after generating high level by triggering at the rising edge of the CLK end of the third D flip-flop DFF3, AND the low level will set the Reset end of the third D flip-flop DFF3 to zero, so that the third D flip-flop DFF3 generates a high level pulse signal, AND further after passing through the second Delay inverter Delay2, the RST21 generates a low level pulse signal, one end of the second AND gate AND2 is connected to the RST21, AND the other end is connected to an enable signal RST, after the frequency AND phase detector starts to work, the RST is constantly 1, so the first AND gate AND1 outputs the RST22 to output a low level pulse signal. After the delay locked loop completes locking, CLK _ FB is delayed by one clock cycle from CLK _ REF, so that CLK _ FB and CLK _ REF trigger simultaneously, and further, in order to eliminate the phase detection dead zone of the phase frequency detector after the delay locked loop is locked, the falling edge of RST22 is delayed from the rising edge of REF _ P, so that a high level pulse is generated at the Q terminal of the fourth D flip-flop DFF 4. From the above example analysis, it can be seen that the size of the delay inverter is strictly selected, which is too large to affect the phase detection range, and too small to actually eliminate the dead zone.

The phase frequency detector for the delay locked loop controls the charge and discharge of the charge pump according to the working principle as follows:

after the phase frequency detector starts to work, when the CLK _ REF rises for the charging module 1, the first D flip-flop DFF1 is set to 1, the Reset end Reset of the first D flip-flop DFF1 is set to 0 after passing through an inverter for time Delay, the first D flip-flop DFF1 outputs 0, and the Reset end Reset of the first D flip-flop DFF1 is set to 1 after passing through the first Delay inverter Delay1, so that the output end of the DFF1 can be triggered again when the CLK _ REF rises next time. When the first D flip-flop DFF1 resets terminal 0, the second D flip-flop DFF2 also resets terminal 0, and the falling edge of the reset terminal UP _ RST of the second D flip-flop DFF2 is delayed by td1 with respect to the rising edge of CLK _ REF. When CLK _ FB is delayed within (pi, 2 pi) from CLK _ REF by Δ θ, the rising edge of FB _ P is aligned with the high level of REF _ N, the output UP of the second D flip-flop DFF2 is set to 1, the rising edge of UP is set to td2 with respect to CLK _ FB, the UP terminal is set to 1 and then set to 0 by the UP _ RST set 0 signal triggered by the next period CLK _ REF, and a UP high level pulse is formed with a width of (2 pi + t)_d1)-(△θ+t_d2) Due to the fact thatTherefore, the higher the pulse width of the high level, the smaller Δ θ, the more the filter capacitor is charged per cycle. In the same way, whenWhen the pulse width of the high level at the DOWN end is (delta theta + t)_d1)-(2π+t_d2) At this time, the larger Δ θ, the larger the high-level pulse width, that is, the larger Δ θ, the more the filter capacitor is discharged per cycle. When [ Delta ] theta is 2 pi, the high-level pulse width of UP and DOWN is t_d1-t_d2Thus, CP charges and discharges at the same time, the output current is zero, and the filter capacitor is not charged or discharged. Thus, although the current exists, the power consumption is increasedBut the dead zone can be eliminated. t is t_d1Composed of phase inverter with large delay and an AND gate with one phase inverter_d2Is composed of two inverters t_d1-t_d2The size is strictly controlled, too large affects the phase discrimination range, and too small may not really eliminate the dead zone. As can be seen from the simulation results of the circuit, the setup time and hold time of the second D flip-flop DFF2 and the fourth D flip-flop DFF4 are 200pS, and therefore, when Δ θ is 2 pi, the output terminal of the corresponding D flip-flop can be set to 1. Considering that the requirement of the phase frequency detector on symmetry is very high, the sizes of the upper and lower devices are completely the same. The phase detection range of the phase frequency detector of the invention obtained by circuit simulation is shown in fig. 4. The phase frequency detector structure provided by the invention can control the charge pump to charge and discharge in the phase difference (pi, 3 pi) so as to control the phase delay of the delay phase-locked loop, so that the delay phase-locked loop can complete phase locking.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.