阅读说明：本技术 计算机系统及其电源管理方法 (Computer system and power management method thereof ) 是由 侯冠宇 傅子瑜 于 2019-09-27 设计创作，主要内容包括：本发明提供一种计算机系统及其电源管理方法。计算机系统包括存储装置及处理器。处理器耦接存储装置,并经组态以执行下列步骤：取得存储装置的状态转换时间。状态转换时间是存储装置进入电源状态及离开此电源状态所花费的时间。依据状态转换时间改变转换容许时间。反应于闲置逾时,处理器依据转换容许时间与电源状态的状态转换时间的比较结果决定存储装置是否进入电源状态。藉此,可改善功耗及效能。(The invention provides a computer system and a power management method thereof. The computer system includes a storage device and a processor. The processor is coupled to the storage device and configured to execute the following steps: a state transition time of the storage device is obtained. The state transition time is the time it takes for the memory device to enter a power state and leave that power state. The transition allowance time is changed according to the state transition time. In response to the idle timeout, the processor determines whether the memory device enters the power state based on a comparison of the transition allowance time and a state transition time of the power state. Therefore, the power consumption and the efficiency can be improved.)

1. A power management method, adapted for use in a computer system, wherein the computer system includes a storage device, the power management method comprising:

obtaining a state transition time for the storage device, wherein the state transition time is the time it takes for the storage device to enter a power state and exit the power state; and

changing a transition allowance time according to the state transition time, wherein

In response to an idle timeout, determining whether the memory device enters the power state based on a comparison of the transition allowance time and the state transition time of the power state.

2. The power management method of claim 1, wherein the step of varying the transition allowance time in accordance with the state transition time comprises:

and increasing the transition allowable time to be larger than the state transition time.

3. The power management method of claim 1, wherein the step of varying the transition allowance time in accordance with the state transition time comprises:

setting the transition permission time to be changed to a driver of the storage device by a login command.

4. The power management method of claim 1, wherein the computer system further comprises a second storage device, and the step of changing the transition allowance time depending on the state transition time comprises:

comparing the state transition times of the storage device and the second storage device; and

and changing the transition allowable time according to the maximum state transition time.

5. The power management method of claim 1, wherein the storage device is based on the non-volatile memory express (NVMe) specification and the driver for controlling the storage device is microsoft standard non-volatile memory express driver (StorNVM).

6. A computer system, comprising:

a storage device; and

a processor coupled to the storage device and configured to perform:

obtaining a state transition time for the storage device, wherein the state transition time is the time it takes for the storage device to enter a power state and exit the power state; and

changing a transition allowance time according to the state transition time, wherein

In response to an idle timeout, determining whether the memory device enters the power state based on a comparison of the transition allowance time and the state transition time of the power state.

7. The computer system of claim 6, wherein the processor is configured to perform:

and increasing the transition allowable time to be larger than the state transition time.

8. The computer system of claim 6, wherein the processor is configured to perform:

setting the transition permission time to be changed to a driver of the storage device by a login command.

9. The computer system of claim 6, further comprising:

a second storage device coupled to the processor, wherein the processor is configured to perform:

comparing the state transition times of the storage device and the second storage device; and

and changing the transition allowable time according to the maximum state transition time.

10. The computer system of claim 6, wherein the storage device is based on NVMe specifications and a driver for controlling the storage device is StorNVM.

Technical Field

The invention relates to a storage device management technology, in particular to a computer system and a power management method for a storage device.

Background

Originally under Microsoft (Microsoft) systems, Non-Volatile Memory Express (NVMe) storage devices were not allowed to support the Auto Power State Transitions (APST) set function of NVMe due to security concerns. Therefore, Microsoft Standard NVM Express Driver (StorNVM/StorNVMe) has its own power management rules. Conceptually, the power management rule APST of StorNVM is almost the same. Under the condition of adopting the Power management rule of the APST, the NVMe storage device is required to enter a Power State 3(Power State 3, PS3) (shallow sleep) or a Power State 4(Power State 4, PS4) (deep sleep) only by a system end to command a driver, and the device end firmware can execute a specified command after receiving the command. However, StorNVM does not support APST, and therefore, StorNVM has a set of power management rules that are APST-like in functionality. The power management rule does not allow the user to instruct the forced device to enter a sleep stage directly at the system end, but only accept idle timeout (timeout) to enter sleep.

FIGS. 1A and 1B illustrate the power management mechanism of StorNVM. Referring to FIG. 1A, the original StorNVM has only one layer of sleep mechanism, i.e. only one layer of sleep mode is allowed in the same power state of the same system. For example, both Alternating Current (AC) mode and Direct Current (DC) mode only allow simultaneous access to either one of the power states PS3 or PS 4. As shown in FIG. 1A, the memory device enters PS4 in response to an idle timeout during the operation mode. Referring to FIG. 1B, the StorNVM has no permission to enter two stages of sleep until after the window (Windows) Redstone 4 (RS 4), i.e. two timeout mechanisms can enter two different levels of sleep respectively in the same system state. As shown in FIG. 1B, the memory device at PS3 enters PS4 in response to an idle timeout.

The microsoft power management mechanism only allows manufacturers to adjust proper parameters at present, and basically does not provide the users for changing after products leave the factory. Therefore, it is an important task for manufacturers to set and select a power management rule suitable for their products or devices. The power management not only directly affects the overall power consumption of the system side and the device side, but also indirectly affects the performance of the device side. Although the design concept of StorNVM is already quite similar to APST, it still has some limitations on its own use and is not as flexible as APST. The same system configuration is not necessarily applicable to all NVMe storage devices, which makes it difficult for manufacturers who manage multiple parts simultaneously to design a power management mechanism for all parts.

Disclosure of Invention

Embodiments of the present invention provide a computer system and a power management method thereof, which adjust a transition allowed time to ensure that a storage device can enter a sleep state.

The power management method of the embodiment of the invention is suitable for a computer system, and the computer system comprises a storage device. The power management method comprises the following steps: a state transition time of the storage device is obtained. The state transition time is the time it takes for the memory device to enter a power state and leave that power state. The transition allowance time is changed according to the state transition time. In response to the idle timeout, determining whether the memory device enters the power state according to a comparison result of the transition allowance time and the state transition time of the power state.

The computer system of the embodiment of the invention comprises a storage device and a processor. The processor is coupled to the storage device and configured to execute the following steps: a state transition time of the storage device is obtained. The state transition time is the time it takes for the memory device to enter a power state and leave that power state. The transition allowance time is changed according to the state transition time. In response to the idle timeout, the processor determines whether the memory device enters the power state based on a comparison of the transition allowance time and a state transition time of the power state.

In view of the above, the computer system and the power management method thereof according to the embodiment of the invention adjust the transition allowance time based on the time taken for the storage device to transition the power state (i.e., the state transition time). The memory device is allowed to enter the predetermined power state only when the transition allowance time is greater than the state transition time. Therefore, by adjusting the transition allowable time, the memory device can be switched to an appropriate power state, thereby improving the system energy consumption and the device performance.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIGS. 1A and 1B illustrate the power management mechanism of StorNVM.

FIG. 2A is a block diagram of components of a computer system according to one embodiment of the invention.

FIG. 2B is a diagram of the hardware and software architecture of a computer system according to an embodiment of the invention.

FIG. 3 is a flowchart of a power management method according to an embodiment of the invention.

FIG. 4 is a flowchart of a method for implementing power management according to an embodiment of the invention.

Description of reference numerals:

100: a computer system;

110: a storage device;

130: an input-output device controller;

150: a processor;

151: an operating system;

153: storing a device driver;

s310 to S330, S410 to S490: and (5) carrying out the following steps.

Detailed Description

FIG. 2A is a block diagram of the components of computer system 100 according to one embodiment of the present invention. Computer system 100 includes, but is not limited to, one or more storage devices 110, an input output device controller 130, and a processor 150. The computer system 100 may be an electronic device such as a desktop computer, a notebook computer, a server, an all in one machine (AIO), and the like.

The Storage device 110 may be a Solid-State Disk (SSD) having any type of non-volatile Memory (for example, a Memory having a non-volatile Storage characteristic, such as a NAND flash Memory (NAND), a Storage Class Memory (SCM), a persistent Memory (persistent), a 3D Xpoint Memory, or a Magnetoresistive Random Access Memory (MRAM)). In the embodiment of the invention, the storage device 110 is based on Non-Volatile Memory Express (NVMe) specification. However, in other embodiments, the transmission interface specification of the storage device 110 may be different, and the application may change itself.

The I/O device Controller 130 is coupled to the storage device 110, and the I/O device Controller 130 may be a Platform Path Controller (PCH), an input/output (I/O) path Controller (ICH), or the like for managing a bus interface, a network interface, a memory interface, or other peripheral device interfaces.

The processor 150 is coupled to the input output device controller 130. The Processor 150 may be a Central Processing Unit (CPU), or other programmable general purpose or special purpose Microprocessor (Microprocessor), Digital Signal Processor (DSP), programmable controller, Application-Specific Integrated Circuit (ASIC), or other similar components or combinations thereof. In the embodiment of the invention, the processor 150 is used for executing all operations of the computer system 100, and can load and execute the operating system, the software modules, the drivers, the files and the data recorded in the storage device 110.

FIG. 2B is a diagram illustrating the hardware and software architecture of the computer system 100 according to an embodiment of the present invention. Referring to fig. 2B, the processor 150 runs an operating system 151 and a storage device driver 153. In one embodiment, operating system 151 is a Microsoft Windows (Windows) system and storage driver 153 is StorNVM. The operating system 151 may run system programs or application programs and issue commands (e.g., related to power state switching, or parameter settings) to the storage device driver 153, which may control or set the power settings of the storage device 110 via the i/o device controller 130. It should be noted that in other embodiments, other variations are possible for the type of operating system 151 and storage device drivers 153.

To facilitate understanding of the operation flow of the embodiment of the present invention, the operation flow of the computer system 100 for power management in the embodiment of the present invention will be described in detail below with reference to various embodiments. The method of the present invention will be described with reference to the components and modules of the computer system 100. The various processes of the method may be adapted according to the implementation, and are not limited thereto.

FIG. 3 is a flowchart of a power management method according to an embodiment of the invention. Referring to fig. 3, the processor 150 obtains a state transition time of the storage device 110 (step S310). Specifically, the state transition time is the time it takes for memory device 110 to enter a certain power state and leave the power state. In microsoft StorNVM system, if the memory device 110 is to enter a Power phase after an Idle timeout (timeout), the Power State setting (defined herein as a Transition allowance time, e.g., NVMe Power State Transition Latency allowance (Power State Transition permission) in the Power option of the window system) must be larger than the time (NVMe limit allowance, i.e., the State Transition time defined herein) the memory device 110 needs to enter and leave the Power State. In other words, in response to the idle timeout of the storage device 110, the storage device driver 153 determines whether the storage device 110 enters the power state according to the comparison result of the transition allowance time and the state transition time of the power state. If the comparison result is that the transition allowed time is longer than the state transition time of the power state, the storage device driver 153 controls the storage apparatus 110 to enter the power state. If the comparison result is that the transition allowed time is not greater than the state transition time of the power state, the storage device driver 153 disables (disables)/does not enter the storage apparatus 110 into this power state (i.e., maintains the current power state).

The operating system 151 may query the storage 110 for state transition times at each power state through the storage driver 153. For example, a query Command for state transition time is issued through a Command Prompt character (Command Prompt)/Command line shell (PowerShell). The firmware of the storage device 110 may recover its own state transition time. In one embodiment, the memory device 110 may recover the delay time for entering a power state and the delay time for leaving the power state, and the processor 150 further uses the sum of the two delay (latency) times as the state transition time of the power state. Further, embodiments of the present invention are directed to state transition times for power states of sleep, low power or hibernate modes (e.g., PS3, PS4, etc., with (maximum) power consumption lower than normal modes).

Next, the processor 150 changes the transition allowable time according to the power transition time (step S330). Specifically, the comparison result of the transition allowable time and the power transition time affects whether the power state of the storage device 110 is switched or not. Table (1) is an example of power management settings. Assuming that the storage device of device number 1 is to enter PS3, the switching permission time must be set to be greater than 2 milliseconds (ms); if PS4 is to be entered, the transition allowance time must be set to be greater than 6 milliseconds (ms). However, the setting of the same conversion permission time is not necessarily applicable to all the storage devices. Assume that the transition allowed time in Alternating Current (AC) mode (general power supply) is 5 milliseconds (ms), and the transition allowed time in Direct Current (DC) mode (battery in use) is 15 milliseconds (ms). Based on this setting, the computer system cannot enter the sleep mode (e.g., PS3 or PS4) in the AC mode for the storage devices of device numbers 3 and 5, but the other storage devices are guaranteed to enter at least PS 3. On the other hand, in the DC mode, the setting of a single transition allowed time cannot uniformly cause different storage devices to enter the same power state/sleep mode.

Watch (1)

This lack of uniformity creates a significant problem. For example, energy star (energy star) requires that the system be able to reduce power consumption when idle to meet environmental regulations. However, in the AC mode, the storage devices of the device numbers 4 and 5 face a problem of failing to pass the specification. In the DC mode, if the computer system loads several different storage devices at the same time, the non-uniform sleep level may also cause the power consumption of the storage devices to be too high, and even fail to meet the battery life specification (battery life spec) of the platform.

To ensure that the memory device 110 enters another power state (or sleep mode) after the idle timeout, in one embodiment, the processor 150 increases the transition latency time and makes the transition latency time greater than the state transition time. The value for increasing the transition allowed time may be a fixed or unfixed value, and the value may change according to the difference between the original transition allowed time and the state transition time. The operating system 151 may execute a command prompt, PowerShell, or batch script (batch script), and set a changed transition allowance time to a driver of the storage 110 (i.e., the storage device driver 153) through a login (registry) command.

In one embodiment, the memory device 110 includes a first power state and a second power state, which correspond to two sleep modes, respectively, and the (maximum) power consumption of the second power state is lower than that of the first power state. For example, the maximum power consumption of PS4 is typically lower than PS 3. The storage device driver 153 provides setting of the switching allowance time of the AC mode and the DC mode. For the AC mode, the processor 150 sets its transition allowance time to be greater than the state transition time of the first power state. For the DC mode, the processor 150 sets its transition allowance time to be greater than the state transition time of the second power state. Thus, in response to the idle timeout of the storage device 110, the computer system 100 is guaranteed to enter the first power state in the AC mode and the second power state in the DC mode.

It should be noted that in other embodiments, the processor 150 may change the transition allowance time of the DC and AC modes only for the state transition time of the first power state or only for the state transition time of the second power state, or the processor 150 may change the transition allowance time of the DC and AC modes based on the weight ratio of the state transition times of the two power states.

In another embodiment, computer system 100 includes a second or more storage devices 110. The processor 150 compares the state transition times of the memory devices 110 and changes the transition allowance time according to the maximum state transition time. Specifically, assume that the computer system 110 only allows the setting of a single transition allowance time. To ensure that all memory devices 110 can enter another power state after the idle timeout, the processor 150 may set the transition allowance time to be greater than the maximum state transition time of the memory devices 110.

For example, table (2) and table (3) are power management settings of the two storage devices 110, respectively. The processor 150 queries the state transition times (14 milliseconds (10+4 milliseconds) and 2 milliseconds (1+1 millisecond), respectively) of the first non-operational state (e.g., PS3) of the two memory devices 110. The processor 150 determines the transition allowance time according to which the state transition time is the largest (i.e., 14 msec). For example, the transition allowable time is set to 15 msec.

Watch (2)

Watch (3)

To assist the reader in understanding the spirit of embodiments of the present invention, another embodiment will be described below.

FIG. 4 is a flowchart of a method for implementing power management according to an embodiment of the invention. Referring to fig. 4, the embodiment of the invention can be implemented by a detection program, and can be preset to start the detection program every time or respond to other conditions. After the computer system 100 is booted (step S410), the processor 150 checks whether the operating system 151 supports microsoft StroNVM (step S420) and whether the computer system 100 has NVMe storage (step S440) (the sequence of the two steps S420 and S440 is not limited). If both are not, the adjustment and setting of the transition allowable time are not required for the current environment, and the detection process may be ended (steps S430 and S450). If both of them are true, the processor 150 will start to query and obtain the state transition time (e.g., NVMe Idle permission) (step S460) of each NVMe storage device under the system, add one millisecond to the obtained state transition time (step S470) (which can be changed and the transition permission time increased), and send the calculated parameters (i.e., the result of adding one millisecond to the state transition time) to the storage device driver 153 (e.g., StorNVM) through the login command provided by microsoft (step S480), so as to complete the current operation of the detection program (step S490) and close the detection program. In this way, it can be ensured that the power management of the storage device 110 can be optimized every time the system is started, and the detection program is closed after the task is executed, so that the system load is not caused.

Table (4) is a simulation of power consumption and performance. By switching to the correct power state, not only can the power consumption of the system be balanced, but also significant performance improvements can be achieved.

Watch (4)

In summary, the computer system and the power management method thereof according to the embodiments of the invention change the transition allowed time for switching the power state determination criterion to be longer than the delay time for the storage device to enter the power state and leave the power state, so as to ensure that the storage device can enter another sleep mode, a low power mode or a sleep mode after the idle timeout, thereby improving power consumption and maintaining better performance.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.