阅读说明：本技术 一种基于并行路径的强臂锁存电压比较器 (Strong arm latch voltage comparator based on parallel path ) 是由 苏杰 李孙华 徐祎喆 朱勇 于 2020-12-14 设计创作，主要内容包括：本发明提供一种基于并行路径的强臂锁存电压比较器,属于电压比较器领域。本发明主要包括：行多路径输入模块、再生锁存模块以及主时钟控制模块；并行多路径输入模块包括同向并行多路径输入模块以及反向并行多路径输入模块用于输入差分对信号。主时钟控制模块用于输入主时钟信号,再生锁存模块用于锁存再生以及差分对信号的输出。本发明通过并行多路径输入的设置,增加了输出节点处的有效电导率,能够在减少电压比较器偏移的同时减少比较器的整体延迟,提高比较器速度。(The invention provides a strong arm latch voltage comparator based on a parallel path, and belongs to the field of voltage comparators. The invention mainly comprises the following steps: the device comprises a row multipath input module, a regeneration latch module and a master clock control module; the parallel multipath input module comprises a cocurrent parallel multipath input module and an inverse parallel multipath input module which are used for inputting differential pair signals. The master clock control module is used for inputting master clock signals, and the regeneration latch module is used for latching regeneration and the output of differential pair signals. According to the invention, through the arrangement of parallel multipath input, the effective conductivity at the output node is increased, the offset of the voltage comparator can be reduced, the integral delay of the comparator can be reduced, and the speed of the comparator can be improved.)

1. A parallel path based strong arm latched voltage comparator, comprising: the device comprises a parallel multipath input module, a regenerative latch module and a master clock control module;

the parallel multipath input module comprises a same-direction parallel multipath input module and a reverse parallel multipath input module which are used for inputting differential pair signals;

the same-direction parallel multipath input module comprises a first same-direction input transistor and at least one parallel same-direction input transistor group, wherein the first forward direction input transistor is connected with the at least one parallel forward direction input transistor group and is respectively connected with a forward direction input end of a forward direction signal in the differential pair signal and the regenerative latch; the reverse parallel multipath input module comprises a first reverse input transistor and at least one parallel reverse input transistor group, wherein the first reverse input transistor is connected with the at least one parallel reverse input transistor group and is respectively connected with a reverse input end of a reverse signal in the differential pair signal and the regenerative latch;

the master clock control module is used for inputting master clock signals, and the regeneration latch module is used for latching regeneration and the output of the differential pair signals.

2. The parallel path based strong arm latched voltage comparator according to claim 1, wherein the master clock control module comprises a first master clock control transistor, a second master clock control transistor and a third master clock control transistor.

3. The parallel path based strong arm latch voltage comparator according to claim 2, wherein the regenerative latch module comprises a first latch transistor, a second latch transistor, a third latch transistor, and a fourth latch transistor.

4. The parallel path based strong arm latch voltage comparator according to claim 3,

the parallel and same-direction input transistor group comprises a parallel and same-direction input transistor and a parallel and same-direction control transistor, and the parallel and reverse input transistor group comprises a parallel reverse input transistor and a parallel reverse control transistor;

wherein the parallel same-direction control transistor and the parallel reverse control transistor are used for inputting an auxiliary clock signal.

5. The parallel path based strong arm latch voltage comparator according to claim 4,

the grid electrode of the parallel same-direction input transistor is connected with a same-direction input end, the source electrode of the parallel same-direction input transistor is connected with the source electrode of the first same-direction input transistor and the drain electrode of the third main clock control transistor, the drain electrode of the parallel same-direction input transistor is connected with the source electrode of the parallel same-direction control transistor, the grid electrode of the parallel same-direction control transistor is connected with an auxiliary clock input end, and the drain electrode of the parallel same-direction control transistor is connected with the drain electrode of the first latch transistor, the drain electrode of the second latch transistor, the drain electrode of the first main clock control transistor, the grid electrode of the third latch transistor, the grid electrode of the fourth latch transistor and a forward output node;

the grid electrode of the parallel reverse input transistor is connected with a reverse input end, the source electrode of the parallel reverse input transistor is connected with the source electrode of the first reverse input transistor and the drain electrode of the third main clock control transistor, and the drain electrode of the parallel reverse input transistor is connected with the source electrode of the parallel reverse control transistor; the grid electrode of the parallel reverse control transistor is connected with the auxiliary clock input end, and the drain electrode of the parallel reverse control transistor is connected with the drain electrode of the third latch transistor, the drain electrode of the fourth latch transistor, the drain electrode of the second main clock control transistor, the grid electrode of the first latch transistor, the grid electrode of the second latch transistor and the reverse output node;

the grid electrode of the first non-inverting input transistor is connected with the non-inverting input end, and the drain electrode of the first non-inverting input transistor is connected with the source electrode of the first latch transistor; the grid electrode of the first reverse input transistor is connected with the reverse input end, and the drain electrode of the first reverse input transistor is connected with the source electrode of the third latch transistor;

a source of the second latch transistor is connected to an external power supply and a source of the first master clock control transistor, and a source of the fourth latch transistor is connected to the external power supply and the source of the second master clock control transistor;

the grid electrode of the first main clock control transistor, the grid electrode of the second main clock control transistor and the grid electrode of the third main clock control transistor are connected with an auxiliary clock input end, and the source stage of the third main clock control transistor is grounded.

6. The parallel path based strong arm latch voltage comparator according to claim 1,

the number of the at least one parallel same-direction input transistor group is the same as that of the at least one parallel reverse-direction input transistor group, and the number is set according to the size of the differential pair signal.

7. The parallel path based strong arm latch voltage comparator according to claim 4,

the pulse duration of the auxiliary clock signal is set according to the worst duration of the strong arm latch voltage comparator.

8. The parallel path based strong arm latch voltage comparator according to claim 4,

the first, second, third and fourth latch transistors are transistors of the same type, and the first, second, third, and fourth latch transistors are transistors of a type complementary to the first clock control transistor.

Technical Field

The invention relates to the field of voltage comparators, in particular to a strong arm latch voltage comparator based on a parallel path.

Background

In the prior art, in order to increase the speed of the voltage comparator, the threshold voltage of the regenerative latch is generally reduced, and due to the nonlinear effect of the voltage comparator, the offset voltage inherent to the voltage comparator is increased, so that the accuracy of the comparator is reduced. The offset voltage of the voltage comparator is reduced by increasing the effective transconductance of the input transistors, mainly due to input transistor mismatch, threshold mismatch and load capacitance mismatch, which can be achieved by increasing their width. If the offset voltage of the voltage comparator is reduced by increasing the effective transconductance of the input transistor, the overall delay of the voltage comparator cannot be reduced, and the purpose of increasing the speed of the comparator cannot be achieved.

Disclosure of Invention

The application provides a strong arm latch voltage comparator based on parallel paths, which reduces the integral delay of the comparator and improves the speed of the comparator while reducing the offset of the voltage comparator through the arrangement of parallel multipath input.

In order to achieve the above object, the present application adopts a technical solution that a parallel path-based strong arm latch voltage comparator is provided, including a parallel multipath input module, a regenerative latch module, and a master clock control module;

the parallel multipath input module comprises a cocurrent parallel multipath input module and an inverse parallel multipath input module which are used for inputting differential pair signals.

The syntropy parallel multipath input module comprises a first syntropy input transistor and at least one parallel syntropy input transistor group, wherein the first syntropy input transistor is connected with the at least one parallel syntropy input transistor group and is respectively connected with a syntropy input end of a syntropy signal in the differential pair signal and the regenerative latch.

The reverse parallel multipath input module comprises a first reverse input transistor and at least one parallel reverse input transistor group, wherein the first reverse input transistor is connected with the at least one parallel reverse input transistor group and is respectively connected with a reverse input end of a reverse signal in the differential pair signals and the regenerative latch.

The master clock control module is used for inputting master clock signals, and the regeneration latch module is used for latching regeneration and the output of differential pair signals.

The invention has the beneficial effects that: according to the invention, through the arrangement of parallel multipath input, the effective conductivity at the output node is increased, the offset of the voltage comparator can be reduced, the integral delay of the comparator can be reduced, and the speed of the comparator can be improved.

Drawings

FIG. 1 is a diagram of one embodiment of a parallel path based strong arm latch voltage comparator according to the present invention;

FIG. 2 is a schematic diagram of a prior art strong arm latch voltage comparator;

FIG. 3 is a schematic diagram of an input current input structure in an embodiment of a parallel path based strong arm latch voltage comparator according to the present invention;

FIG. 4 is a schematic diagram of one embodiment of a parallel path based strong arm latch voltage comparator according to the present invention;

FIG. 5 is a diagram of an embodiment of a parallel path based strong arm latch voltage comparator

The components in the figure are labeled as follows:

m1-first in-line input transistor, M2-first in-line input transistor, M3-first master clock control transistor, M4-second master clock control transistor, M5-first latch transistor, M6-second latch transistor, M7-third latch transistor, M8-fourth latch transistor, Mtail-third master clock control transistor, M1 p-parallel in-line input transistor, Mp-parallel in-line control transistor, M2 n-parallel in-line reverse input transistor, Mn-parallel reverse control transistor, VDD-external power supply, CLK-master clock signal, CLK 1-auxiliary clock signal, Vinp-forward signal, Vinm-reverse signal, I1.1-first forward current, Ip-forward parallel current, I2.1-first reverse current, im-reverse parallel current, I0-total current.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 2 is a schematic diagram illustrating an embodiment of a parallel path based strong arm latch voltage comparator according to the present invention.

In the specific embodiment shown in fig. 1, the present application is based on a parallel path strong arm latch voltage comparator comprising a block 101, a block 102, and a block 103.

The block 101 of fig. 1 shows a parallel multipath input block, which includes a cocurrent parallel multipath input block and an inverse parallel multipath input block for inputting a differential pair signal.

In a specific embodiment of the present invention, the cocurrent parallel multipath input module includes a first cocurrent input transistor M1 and at least one parallel set of cocurrent input transistors, the first forward input transistor is connected to the at least one parallel set of forward input transistors and respectively connected to the forward input of the forward signal in the differential pair signal and the regenerative latch; the inverse parallel multipath input module comprises a first inverse input transistor M2 and at least one parallel inverse input transistor group, and the first inverse input transistor M2 is connected with the at least one parallel inverse input transistor group and is respectively connected with an inverse input end of an inverse signal in the differential pair signal and the regenerative latch. The master clock control module is used for inputting a master clock signal CLK, the regeneration latch module is used for latching regeneration and the output of the differential pair signal

In the prior art strong-arm latch comparator as shown in fig. 2, the forward signal and the reverse signal are respectively input through one path, and the total current finally passing through the tail transistor is I0. In the present invention, as shown in fig. 3, each parallel forward input transistor group constitutes a parallel forward input branch, each parallel inverting input transistor group constitutes a parallel inverting input branch, the input differential signal is fed into all the parallel branches, and the sum of the current of all the parallel branches and the current passing through the first forward input transistor and the first inverting input transistor M2 is I0, i.e. the total current remains unchanged. At this time, if the total number of all the parallel branches is N, the transconductance of the output node will increase by √ N times, thereby reducing the delay, and the variation of the mismatch of the currents of the parallel branch transistors due to the increased transconductance of the parallel branch transistors to the parallel branch determines that the offset voltage of the voltage comparator is not related to the number of the parallel branches, thereby not only reducing the offset, but also reducing the overall delay of the comparator.

In a specific embodiment of the present application, the number of the at least one parallel equidirectional input transistor group is the same as the number of the at least one parallel inversed input transistor group, and the number is set according to the magnitude of the differential pair signal.

Fig. 4 shows a specific embodiment of the present application.

In one embodiment of the present application, as shown in FIG. 4, the master clock control module includes a first master clock control transistor M3, a second master clock control transistor M4, and a third master clock control transistor Mtail.

In one embodiment of the present application, as shown in fig. 4, the regenerative latch module includes a first latch transistor M5, a second latch transistor M6, a third latch transistor M7, and a fourth latch transistor M8.

In one embodiment of the present application, as shown in fig. 4, the set of parallel-to-parallel input transistors M1p includes a parallel-to-parallel input transistor M1p and a parallel-to-parallel control transistor Mp, and the set of parallel-to-inverting input transistors includes a parallel-to-inverting input transistor M2n and a parallel-to-inverting control transistor Mn; where a parallel equidirectional control transistor Mp and a parallel inversive control transistor Mn are used for inputting the auxiliary clock signal CLK 1. Once the output is generated, the conventional comparator has no current path from the external power supply VDD to ground, and thus has no static power consumption; however, in the voltage comparator structure of the present application, the additional branch dissipates power constantly even after the output is asserted. This problem may be solved by providing an additional auxiliary clock signal CLK 1.

In one embodiment of the present application, the pulse duration of the auxiliary clock signal CLK1 is set according to the worst duration of the strong-arm latch voltage comparator, so that the operation state of the strong-arm latch voltage comparator of the present application is kept accurately and stably.

In one particular embodiment of the present application, as shown in fig. 4, the gate of the parallel homodyne input transistor M1p is connected to the homodyne input, the source of the parallel same-direction input transistor M1p is connected to the source of the first same-direction input transistor M1 and the drain of the third master clock control transistor Mtail, the drain of the parallel syntropy input transistor M1p is connected to the source of the parallel syntropy control transistor Mp, the gate of the parallel same-direction control transistor Mp is connected with an auxiliary clock signal input terminal, and the drain of the parallel same-direction control transistor Mp is connected with the drain of the first latch transistor M5, the drain of the second latch transistor M6, the drain of the first master clock control transistor M3, the gate of the third latch transistor M7, the gate of the fourth latch transistor M8 and a forward output node;

the gate of the parallel inverting input transistor M2n is connected to the inverting input terminal, the source of the parallel inverting input transistor M2n is connected to the source of the first inverting input transistor M2 and the drain of the third master clock control transistor Mtail, and the drain of the parallel inverting input transistor M2n is connected to the source of the parallel inverting control transistor Mn; the gate of the parallel inversion control transistor Mn is connected to the auxiliary clock signal input terminal, and the drain of the parallel inversion control transistor Mn is connected to the drain of the third latch transistor M7, the drain of the fourth latch transistor M8, the drain of the second master clock control transistor M4, the gate of the first latch transistor M5, the gate of the second latch transistor M6, and the inversion output node;

the gate of the first non-inverting input transistor M1 is connected with the non-inverting input terminal, and the drain of the first non-inverting input transistor M1 is connected with the source of the first latch transistor M5; the gate of the first inverting input transistor M2 is connected with the inverting input terminal, and the drain of the first inverting input transistor M2 is connected with the source of the third latch transistor M7;

a source of the second latch transistor M6 is connected to an external power source VDD and a source of the first master clock control transistor M3, and a source of the fourth latch transistor M8 is connected to the external power source VDD and a source of the second master clock control transistor M4;

the gate of the first master clock control transistor M3, the gate of the second master clock control transistor M4, and the gate of the third master clock control transistor Mtail are connected to an auxiliary clock signal input terminal, and the source of the third master clock control transistor Mtail is grounded.

In one embodiment of the present application, as shown in fig. 4, the first master clock control transistor M3, the second master clock control transistor M4, the third latch transistor M7 and the fourth latch transistor M8 are transistors of the same type, and the first latch transistor M5, the second latch transistor M6, the first incom 1, the first inverting input transistor M2, the parallel incom input transistor M1p, the parallel incom control transistor Mp, the parallel inverting input transistor M2n, the parallel inverting control transistor Mn and the third master clock control transistor Mtail are transistors of a complementary type to the first clock control transistor.

The working principle of the invention is that the working mode in the reset stage is the same as that of the traditional comparator. During the regeneration phase, the capacitor begins to discharge through the parallel path. The input signal is fed to all N-parallel branches, each allowing a gm input current to pass through it. Thus, the total current from the load capacitor is discharged through the N +2 branch. However, the total current through the tail transistor remains unchanged. Furthermore, for the N parallel branch, the effective transconductance of the output node will increase by √ N times, when the main clock signal CLK is high, the input pair transistor conducting node starts to discharge from the external power VDD through the input pair transistor, the more the transistor, i.e., the more the current leakage path, the faster the falling threshold voltage makes the M5-M8 cross-coupled transistor conducting, and the delay is smaller until the regeneration phase starts, thereby reducing the delay.

Once the output is generated, the conventional comparator has no current path from the external power supply VDD to ground, and thus no static power consumption. However, in the proposed architecture, the additional branch continuously dissipates power even after the output is determined. This problem can be solved by providing an additional auxiliary clock signal CLK1, the time duration of the pulse depending on the worst case delay of the comparator, which is adjusted by the delay element. The addition of parallel paths reduces the overall delay of the proposed comparator.

Fig. 5 shows a specific example of the present application, and in the example shown in fig. 5, the number of the at least one parallel equidirectional input transistor group and the number of the at least one parallel inverting input transistor group are respectively 5.

In the embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, for example, the division of the units is only one division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in a typical, mechanical or other form.

The units described as separate but not illustrated may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.