阅读说明：本技术 存储单元和cmos反相器电路 (Memory cell and CMOS inverter circuit ) 是由 冨田学 于 2019-08-13 设计创作，主要内容包括：存储单元包括触发器电路,该触发器电路包括具有第1A晶体管TR-1和第1B晶体管TR-2的第一CMOS反相器电路以及具有第2A晶体管TR-3和第2B晶体管TR-4以及两个传输晶体管TR-5和TR-6的第二反相器电路。第1A晶体管TR-1和第2A晶体管TR-2连接到公共的第一电源线91,并且第1B晶体管TR-3和第2B晶体管TR-4连接到公共的第二电源线92。(The memory cell includes a flip-flop circuit including a 1A-th transistor TR 1 And a 1B transistor TR 2 And has a 2A-th transistor TR 3 And a 2B transistor TR 4 Andtwo transfer transistors TR 5 And TR 6 The second inverter circuit of (1). 1A transistor TR 1 And a 2A transistor TR 2 Connected to a common first power supply line 91, and a 1B transistor TR 3 And a 2B transistor TR 4 To a common second power supply line 92.)

1. A memory cell, comprising:

a flip-flop circuit including a first CMOS inverter circuit and a second inverter circuit; and

two pass transistors, wherein,

the first CMOS inverter comprises

A 1A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 1B transistor including an nMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer,

the second CMOS inverter circuit includes

A 2A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 2B transistor including an nMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer,

each of the transfer transistors includes a drain region, a channel formation region, and a source region stacked together, and further includes a gate electrode layer;

the drain region of the 1A-th transistor and the drain region of the 1B-th transistor are connected to a common first drain region-connection,

the drain region of the 2A transistor and the drain region of the 2B transistor are connected to a common second drain region-connection,

the gate electrode layer common to the 1A-th transistor and the 1B-th transistor is connected to the second drain region-connecting portion through a first gate electrode-connecting portion,

the gate electrode layer common to the 2A-th transistor and the 2B-th transistor is connected to the first drain region-connecting portion through a second gate electrode-connecting portion,

the source region of the 1A transistor and the source region of the 2A transistor are connected to a common first power supply line, and

the source region of the 1B transistor and the source region of the 2B transistor are connected to a common second power supply line.

2. The memory cell of claim 1,

the drain regions of the 1A, 1B, 2A and 2B transistors and one source/drain region of the first and second transfer transistors are formed on a substrate, and

the first drain region-connecting portion and the second drain region-connecting portion are formed on the substrate.

3. The memory cell of claim 2, wherein the first drain region-connecting portion and the second drain region-connecting portion each comprise a high concentration impurity region or a conductive material layer formed on the substrate.

4. The memory cell of claim 1,

the source regions of the 1A, 1B, 2A and 2B transistors and one source/drain region of the first and second transfer transistors are formed on a substrate, and

the first power line and the second power line are formed on the substrate.

5. The memory cell according to claim 4, wherein the first power supply line and the second power supply line each include a high-concentration impurity region or a conductive material layer formed on the substrate.

6. The memory cell of claim 1,

the other source/drain region of the first transfer transistor is connected to a first bit line,

the other source/drain region of the second pass transistor is connected to a second bit line,

one source/drain region of the first transfer transistor is connected to the first drain region-connecting portion, and

one source/drain region of the second transfer transistor is connected to the second drain region-connecting portion.

7. The memory cell of claim 6, wherein the first power supply line, the second power supply line, the first bit line, and the second bit line extend in a first direction.

8. The memory cell according to claim 1, wherein assuming that a direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend is a first direction, and assuming that a direction orthogonal to the first direction is a second direction, adjacent memory cells are arranged line-symmetrically with respect to a boundary line extending in the first direction, a boundary line extending in the second direction, or boundary lines extending in the first direction and the second direction.

9. The memory cell of claim 1, wherein the first and second CMOS inverter circuits are symmetrically arranged twice with respect to a central axis of the memory cell.

10. The memory cell of claim 1,

the gate electrode layer common to the first transfer transistor and the second transfer transistor also serves as a word line, and

the word line extends in a second direction different from a first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend.

11. The memory cell of claim 10,

an orthographic projection image of the first power supply line overlaps with a part of an orthographic projection image of the source region of the 1A-th transistor and also overlaps with a part of an orthographic projection image of the source region of the 2A-th transistor, and

an orthographic projection image of the second power supply line overlaps a part of an orthographic projection image of the source region of the 1B-th transistor, and also overlaps a part of an orthographic projection image of the source region of the 2B-th transistor.

12. The memory cell of claim 10, wherein an orthogonal projection image of the drain region, the channel formation region, and the source region of the 1A transistor and the drain region, the channel formation region, and the source region of the 1B transistor to a virtual plane perpendicular to a first direction is configured, an orthogonal projection image of the drain region, the channel formation region, and the source region of the 2A transistor and the drain region, the channel formation region, and the source region of the 2B transistor to a virtual plane perpendicular to the first direction is configured, an orthogonal projection image of one source/drain region, the channel formation region, and another source/drain region of the first transfer transistor to a virtual plane perpendicular to the first direction is configured, and an orthogonal projection image of one source/drain region, the channel formation region, and another source/drain region of the second transfer transistor to a virtual plane perpendicular to the first direction is configured, Orthogonal projection images of the channel formation region and the other source/drain region to a virtual plane perpendicular to the first direction do not substantially overlap with each other.

13. The memory cell of claim 10,

orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1A-th transistor to a virtual plane perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1B-th transistor to a virtual plane perpendicular to the second direction substantially overlap each other,

orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2A-th transistor to a virtual plane perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2B-th transistor to a virtual plane perpendicular to the second direction substantially overlap each other, and

an orthogonal projection image of configuring one source/drain region, the channel formation region, and the other source/drain region of the first transfer transistor to a virtual plane perpendicular to the second direction and an orthogonal projection image of configuring one source/drain region, the channel formation region, and the other source/drain region of the second transfer transistor to a virtual plane perpendicular to the second direction substantially overlap each other.

14. The memory cell of claim 10,

the first power supply line and the second power supply line are arranged in a first stage, and

the first bit line and the second bit line are arranged in a second level different from the first level.

15. The memory cell of claim 1,

the gate electrode layer common to the first and second transfer transistors is connected to a word line, and

the word line extends in a second direction different from a first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend.

16. The memory cell of claim 15, wherein orthographically projected images of the drain region, the channel formation region, and the source region of the 1A-th transistor to a virtual plane perpendicular to the second direction are configured, orthographically projected images of the drain region, the channel formation region, and the source region of the 1B-th transistor to a virtual plane perpendicular to the second direction are configured, and orthographically projected images of one source/drain region, the channel formation region, and the other source/drain region of the first transfer transistor are configured to substantially overlap each other, and

an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 2A-th transistor to a virtual plane perpendicular to the second direction, an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 2B-th transistor to a virtual plane perpendicular to the second direction, and an orthogonal projection image of one source/drain region, the channel formation region, and the other source/drain region configuring the second transfer transistor substantially overlap each other.

17. The memory cell of claim 15,

the first power supply line, the second power supply line, the first bit line, and the second bit line are arranged in a first stage, and

the word lines are arranged in a second level different from the first level.

18. A CMOS inverter circuit comprising:

a pMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer; and

an nMOS transistor comprising a drain region, a channel formation region and a source region stacked together, and further comprising a gate electrode layer, wherein,

the drain region of the pMOS transistor and the drain region of the nMOS transistor are connected to a common drain region-connecting portion,

the gate electrode layer common to the pMOS transistor and the nMOS transistor is connected to a common gate wiring portion formed on a substrate through a gate electrode-connecting portion,

the source region of the pMOS transistor is connected to a first power supply line, and

the source region of the nMOS transistor is connected to a second power supply line.

19. The CMOS inverter circuit of claim 18,

the drain region of the pMOS transistor and the drain region of the nMOS transistor are formed on the substrate, and

the common drain region-connecting portion is formed on the substrate.

20. The CMOS inverter circuit of claim 18,

the source region of the pMOS transistor and the source region of the nMOS transistor are formed on the substrate, an

The first power line and the second power line are formed on the substrate.

Technical Field

The present disclosure relates to a memory cell, and more particularly, to a memory cell including an SRAM (static random access memory) and a CMOS inverter circuit.

Background

For example, a semiconductor device including a CMOS inverter circuit including a pMOS transistor and an nMOS transistor having a channel formation region including a nanowire or a nanotube is known from japanese patent laid-open No. 2008-205168. In the CMOS inverter circuit disclosed in the above-mentioned japanese patent publication, the drains of the nMOS transistor and the pMOS transistor each include an n-type impurity region and a p-type impurity region formed on the surface of the semiconductor substrate, and the n-type impurity region and the p-type impurity region are ohmically connected by a connection region for ohmic connection between the n-type impurity region and the p-type impurity region. Further, a nanowire or nanotube is vertically disposed on the n-type impurity region and the p-type impurity region, and sources of the nMOS transistor and the pMOS transistor are formed at upper ends of the nanowire or nanotube, wherein gate electrodes of the nMOS transistor and the pMOS transistor are connected to each other through a gate electrode wiring. Here, the gate electrode includes a conductive film covering the periphery of the nanowire or nanotube with a gate insulating film interposed therebetween, and a gate electrode wiring extends from the gate electrode, and a via hole to be connected to the gate electrode wiring is formed on the gate electrode wiring.

Further, in the above japanese patent publication, an SRAM memory cell including a CMOS inverter circuit is also disclosed. Further, in fig. 10(b) of the japanese patent publication, the arrangement of the transistor and the via is shown, and when the area of the region occupied by the transistor and the via is Δ²When expressed, the area of the region occupied by one SRAM cell is 36 Δ²(═ 6 Δ × 6 Δ), as shown in fig. 52A. It should be noted that in order to clearly indicate the size of "Δ", grids are additionally depicted in fig. 52A and 52B. Further, reference numeral "TR" in fig. 52A and 52B₁”、“TR₂”、“TR₃”、“TR₄”、“TR₅"and" TR₆"respectively denotes the 1 st a transistor TR in the present disclosure described below₁1B transistor TR₂2A transistor TR₃2B transistor TR₄A first transfer transistor TR₅And a second transfer transistor TR₆The same transistors. Further, reference numeral "a" corresponds to the first gate electrode-connecting portion 73 in the memory cell of the present disclosure described below. Further, reference numeral "B" corresponds to the second gate electrode-connecting portion 74 in the memory cell of the present disclosure described below, and reference numeral "C" corresponds to the connecting holes 54 and 55 in the memory cell of the present disclosure described below, and reference numeral "D" corresponds to the connecting holes 64 and 65 in the memory cell of the present disclosure described below.

[ citation list ]

[ patent document ]

[ patent document 1]

Japanese patent laid-open No. 2008-205168

Disclosure of Invention

[ problem ] to

Incidentally, as shown in fig. 10(B) or fig. 52A of the japanese patent laid-open, a part of the gate electrode wiring 15A, the gate electrode wiring 15B, the gate electrode wiring 15C, and the gate electrode wiring 15D is formed in an oblique direction. However, in practice, with the miniaturization of transistors, it is difficult to form such wirings in an oblique direction as described above. In the case where the gate electrode wiring 15A, the gate electrode wiring 15B, the gate electrode wiring 15C, and the gate electrode wiring 15D shown in fig. 10(B) or fig. 52A of the japanese patent laid-open are formed as wirings which extend in the vertical direction and the horizontal direction and can be actually formed, the area of the region occupied by one SRAM memory cell is 48 Δ²(═ 6 Δ × 8 Δ), as shown in fig. 52B. Here, it is strongly demanded to further reduce the area of the SRAM memory cell in order to achieve high integration of the SRAM memory cell. Further, in the configuration shown in FIG. 52B, if one word line, two bit lines, one V are provided_ddPower supply line and a strip V_ssThe power supply line requires four wiring layers for providing the wiring. However, further reduction in the number of wiring layers is strongly demanded.

Therefore, an object of the present disclosure is to provide a memory cell which can be further reduced in area or can be further reduced in the number of wiring layers, and a CMOS inverter circuit configuring such a memory cell.

[ solution of problem ]

The memory cell of the present disclosure for achieving the above object is

A memory cell comprising a flip-flop circuit comprising a first CMOS inverter circuit and a second inverter circuit and two pass transistors, wherein

The first CMOS inverter comprises

A 1A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 1B transistor including an nMOS transistor including a drain region, a channel formation region and a source region stacked together and further including a gate electrode layer, and a second CMOS inverter circuit including

A 2A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 2B transistor including an nMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer,

each of the transfer transistors includes one source/drain region, a channel formation region, and another source/drain region stacked together, and further includes a gate electrode layer,

the drain region of the 1A-th transistor and the drain region of the 1B-th transistor are connected to a common first drain region-connection,

the drain region of the 2A-th transistor and the drain region of the 2B-th transistor are connected to a common second drain region-connection,

the gate electrode layer (first gate electrode layer) common to the 1A-th transistor and the 1B-th transistor is connected to the second drain region-connecting portion through the first gate electrode-connecting portion,

a gate electrode layer (second gate electrode layer) common to the 2A-th transistor and the 2B-th transistor is connected to the first drain region-connecting portion through a second gate electrode-connecting portion,

the source region of the 1A transistor and the source region of the 2A transistor are connected to a common first power supply line, and

the source region of the 1B-th transistor and the source region of the 2B-th transistor are connected to a common second power supply line.

The CMOS inverter circuit of the present disclosure for achieving the above object is a CMOS inverter circuit including

A pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, an

An nMOS transistor comprising a drain region, a channel formation region and a source region stacked together, and further comprising a gate electrode layer, wherein

The drain regions of the pMOS transistor and the drain regions of the nMOS transistor are connected to a common drain region-connecting portion,

a gate electrode layer common to the pMOS transistor and the nMOS transistor is connected to a common gate wiring portion formed on the substrate through a gate electrode-connecting portion,

the source region of the pMOS transistor is connected to a first power supply line, and

the source region of the nMOS transistor is connected to the second power supply line.

Drawings

Fig. 1 is a schematic perspective view of a part of a storage unit of working example 1.

Fig. 2 is an equivalent circuit diagram of a memory cell of working example 1.

Fig. 3A and 3B are a schematic perspective view of a part of the CMOS inverter circuit of working example 1 and an equivalent circuit diagram of the CMOS inverter circuit of working example 1, respectively.

Fig. 4A, 4B and 4C are schematic partial sectional views taken along arrow marks a-a, B-B and C-C of fig. 1 and 5 of the memory unit of working example 1.

Fig. 5 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 4A.

Fig. 6 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks B-B of fig. 4A.

Fig. 7 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks C-C of fig. 4A.

Fig. 8 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks D-D of fig. 4A.

Fig. 9 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks E-E of fig. 4A.

Fig. 10 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 1 when the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks F-F of fig. 4A.

Fig. 11 is a conceptual diagram of an arrangement state of components configuring the first modification of the storage unit of working example 1 when the first modification of the storage unit of working example 1 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 4A, and is a conceptual diagram similar to fig. 5.

Fig. 12 is a conceptual diagram of an arrangement state of components configuring the second modification of the storage unit of the working example 1 when the second modification of the storage unit of the working example 1 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 4A, and is a conceptual diagram similar to fig. 5.

Fig. 13A and 13B are schematic partial sectional views taken along arrow marks a-a and B-B of fig. 15 of the memory cell of working example 2.

Fig. 14 is an equivalent circuit diagram of a memory cell of working example 2.

Fig. 15 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 13A.

Fig. 16 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including arrow mark B-B of fig. 13A.

Fig. 17 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including arrow marks C-C of fig. 13A.

Fig. 18 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including arrow marks D-D of fig. 13A.

Fig. 19 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including arrow marks E-E of fig. 13A.

Fig. 20 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 2 when the storage unit of working example 2 is cut along a virtual horizontal plane including arrow marks F-F of fig. 13A.

Fig. 21A, 21B and 21C are schematic partial sectional views taken along arrow mark a-a, arrow mark B-B and arrow mark C-C of fig. 24 of the storage unit of working example 3.

Fig. 22A and 22B are schematic partial sectional views taken along arrow marks D-D and arrow marks E-E of fig. 24 of the memory cell of working example 3.

Fig. 23 is an equivalent circuit diagram of a memory cell of working example 3.

Fig. 24 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 3 when the storage unit of working example 3 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 21A.

Fig. 25 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 3 when the storage unit of working example 3 is cut along a virtual horizontal plane including arrow marks B-B of fig. 21A.

Fig. 26 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 3 when the storage unit of working example 3 is cut along a virtual horizontal plane including arrow marks C-C of fig. 21A.

Fig. 27 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 3 when the storage unit of working example 3 is cut along a virtual horizontal plane including arrow marks D-D of fig. 21A.

Fig. 28 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 3 when the storage unit of working example 3 is cut along a virtual horizontal plane including arrow marks E-E of fig. 21A.

Fig. 29 is a conceptual diagram of an arrangement state of components configuring the first modification of the storage unit of the working example 3 when the first modification of the storage unit of the working example 3 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 25A.

Fig. 30A and 30B are schematic partial sectional views taken along arrow marks a-a and B-B of fig. 32 of the storage unit of working example 4.

Fig. 31 is an equivalent circuit diagram of the memory cell of working example 4.

Fig. 32 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 30A.

Fig. 33 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including arrow marks B-B of fig. 30A.

Fig. 34 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including arrow marks C-C of fig. 30A.

Fig. 35 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including arrow marks D-D of fig. 30A.

Fig. 36 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including arrow marks E-E of fig. 30A.

Fig. 37 is a conceptual diagram of an arrangement state of components configuring the storage unit of working example 4 when the storage unit of working example 4 is cut along a virtual horizontal plane including arrow marks F-F of fig. 30A.

Fig. 38A, 38B and 38C are schematic partial sectional views taken along arrow marks a-a, B-B and C-C of fig. 39 of a third modification of the memory cell of working example 1.

Fig. 39 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including an arrow mark a-a of fig. 38A.

Fig. 40 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks B-B of fig. 38A.

Fig. 41 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks C-C of fig. 38A.

Fig. 42 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks D-D of fig. 38A.

Fig. 43 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks E-E of fig. 38A.

Fig. 44 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane including arrow marks F-F of fig. 38A.

Fig. 45 is a conceptual diagram of an arrangement state of components configuring a third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow mark a-a of fig. 38A.

Fig. 46 is a conceptual diagram of an arrangement state of components configuring a third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow marks B-B of fig. 38A.

Fig. 47 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow marks C-C of fig. 38A.

Fig. 48 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow marks D-D of fig. 38A.

Fig. 49 is a conceptual diagram of an arrangement state of components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow marks E-E of fig. 38A.

Fig. 50 is a conceptual diagram of an arrangement state of components configuring a third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along a virtual horizontal plane similar to the virtual horizontal plane including arrow marks F-F of fig. 38A.

Fig. 51 is a conceptual diagram of an arrangement state of components configuring the first modification of the storage unit of working example 2 when the first modification of the storage unit of working example 2 is cut along a virtual horizontal plane similar to that shown in fig. 17.

Fig. 52A and 52B are schematic diagrams showing the size of the SRAM memory disclosed in japanese patent laid-open No. 2008-205168.

Detailed Description

Hereinafter, although the present disclosure is described based on working examples with reference to the drawings, the present disclosure is not limited to the working examples, and various numerical values and materials in the working examples are exemplary. It should be noted that the description is given in the following order.

1. Description of the entire memory cell and CMOS inverter circuit of the present disclosure

2. Working example 1 (memory cell and CMOS inverter circuit of the present disclosure, memory cell of the first form of the present disclosure, memory cell of the first configuration of the present disclosure)

3. Working example 2 (modification of working example 1, memory cell of first form of the present disclosure, memory cell of second configuration of the present disclosure)

4. Working example 3 (another modification of working example 1, memory cell of the second form of the present disclosure, memory cell of the first configuration of the present disclosure)

5. Working example 4 (modification of working example 2, memory cell of the second form of the present disclosure, memory cell of the second configuration of the present disclosure)

6. Others

< description of the entire memory cell and CMOS inverter circuit of the present disclosure >

The memory cell of the present disclosure may be formed such that

Drain regions of the 1A, 1B, 2A, and 2B transistors and one source/drain region of the first and second transfer transistors are formed on (particularly directly above) the substrate; and is

The first drain region-connecting portion and the second drain region-connecting portion are formed on a substrate (particularly, a top surface portion of the substrate). It should be noted that for convenience of description, the memory cell of the present disclosure having such a form just described is sometimes referred to as "the memory cell of the first form of the present disclosure". Further, in this case, the memory cell of the present disclosure may be formed such that the first drain region-connecting portion and the second drain region-connecting portion each include a high concentration impurity region or a conductive material layer (e.g., a silicide layer, a salicide layer, or a layer made of a well-known conductive material) formed on the substrate. Further, it is sufficient if the first power supply line and the second power supply line are configured by a known wiring material.

Alternatively, the memory cell of the present disclosure may be formed such that

Source regions of the 1A, 1B, 2A, and 2B transistors and one source/drain region of the first and second transfer transistors are formed on (particularly directly above) the substrate; and is

The first power supply line and the second power supply line are formed on a substrate (particularly, a top surface portion of the substrate). It should be noted that for convenience of description, a memory cell of the present disclosure having such a form just described is sometimes referred to as a "memory cell of the second form of the present disclosure". Further, in this case, the memory cell of the present disclosure may be formed such that the first power supply line and the second power supply line each include a high concentration impurity region or a conductive material layer (e.g., a silicide layer, a salicide layer, or a layer made of a well-known conductive material) on the substrate. Further, it is sufficient if the first drain region-connecting portion and the second drain region-connecting portion are configured by a well-known wiring material.

The memory cell of the present disclosure including the various preferred forms described above may be formed such that

The other source/drain region of the first transfer transistor is connected to a first bit line,

the other source/drain region of the second pass transistor is connected to a second bit line,

one source/drain region of the first transfer transistor is connected to the first drain region-connecting portion, and

one source/drain region of the second transfer transistor is connected to the second drain region-connecting portion. Further, in this case, the memory cell of the present disclosure may be formed such that the first power line, the second power line, the first bit line, and the second bit line extend in the first direction. It is sufficient if the first bit line and the second bit line are configured by a known wiring material.

Further, the memory cell of the present disclosure including the various preferred forms described above may be formed such that the direction in which the first power line, the second power line, the first bit line, and the second bit line extend is a first direction, and the direction orthogonal to the first direction is a second direction, and adjacent memory cells are line-symmetrically arranged with respect to a boundary line (a boundary line extending in the first direction, a boundary line extending in the second direction, or a boundary line extending in the first and second directions).

Further, the memory cell of the present disclosure including the various preferred forms described above may be formed such that the first CMOS inverter circuit and the second inverter circuit are symmetrically arranged twice with respect to the central axis of the memory cell. The central axis of the storage unit is a straight line parallel to the normal direction of the substrate.

Further, the storage unit of the present disclosure including the various preferred forms described above may be configured such that

The gate electrode layer (third gate electrode layer) common to the first transfer transistor and the second transfer transistor also serves as a word line, and

the word line extends in a second direction (specifically, for example, in a second direction orthogonal to the first direction) different from the first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend. It should be noted that, for convenience of description, the memory cell of the present disclosure having such a form just described is sometimes referred to as "the memory cell of the first configuration of the present disclosure". Further, in this case, the storage unit of the present disclosure including the various preferred forms described above may be configured such that

The orthographic projection image of the first power supply line overlaps with a part of the orthographic projection image of the source region of the 1A-th transistor and also overlaps with a part of the orthographic projection image of the source region of the 2A-th transistor, and

the orthographic projection image of the second power supply line overlaps a part of the orthographic projection image of the source region of the 1B transistor, and also overlaps a part of the orthographic projection image of the source region of the 2B transistor. Further, the storage unit of the present disclosure including the various preferred forms described above may be formed such that, in the described configuration, the following orthogonal projection images do not substantially overlap with each other:

[A] configuring an orthographic projection image of the drain region, the channel formation region, and the source region of the 1A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction;

[B] configuring an orthographic projection image of the drain region, the channel formation region, and the source region of the 1B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction;

[C] configuring an orthographic projection image of the drain region, the channel formation region, and the source region of the 2A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction;

[D] configuring an orthographic projection image of the drain region, the channel formation region, and the source region of the 2B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction;

[E] configuring an orthographic projection image of one source/drain region, the channel formation region, and the other source/drain region of the first transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction; and

[F] an orthographic projection image of one source/drain region, the channel formation region, and the other source/drain region of the second transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction is configured. Further, the memory cell of the present disclosure, including the various preferred forms described above, may be formed such that, in the described configuration,

orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction substantially overlap each other,

orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction substantially overlap each other, and

an orthogonal projection image of the one source/drain region, the channel formation region, and the other source/drain region configuring the first transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction and an orthogonal projection image of the one source/drain region, the channel formation region, and the other source/drain region configuring the second transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction substantially overlap each other. Further, the memory unit of the present disclosure including the various preferred forms described above may be configured such that, in the described configuration,

the first power supply line and the second power supply line are arranged in a first stage, and

the first bit lines and the second bit lines are arranged in a second level different from the first level. The first stage may be positioned on the substrate side relative to the second stage, or the second stage may be positioned on the substrate side relative to the first stage. The word line corresponds to an extension of the third gate electrode layer common to the first transfer transistor and the second transfer transistor, and is configured of the same material as the third gate electrode layer. Orthogonal projection images that substantially overlap or do not overlap with each other are determined in consideration of variations in manufacturing of various transistors, and even if the orthogonal projection images do not slightly overlap with each other, they may be determined to overlap with each other, and even if the orthogonal projection images slightly overlap with each other, they may be determined not to overlap with each other. This similarly applies to the description given below.

The memory cells of the first configuration of the present disclosure may be formed such that the second power supply line to which the source region of the 1B-th transistor configuring one memory cell is connected to the source region of the 2B-th transistor configuring a memory cell adjacent to the one memory cell in the second direction (the memory cell is located on the boundary line extending in the first direction). In particular, the memory cell of the first configuration of the present disclosure may be formed such that the 1B-th transistor of one memory cell is configuredThe source region and the source region of the 2B-th transistor configuring a memory cell adjacent to one memory cell in the second direction are connected to the same second power supply line. For example, applying V to the first power line_ddAnd applying e.g. V to the second power supply line_ss。

Alternatively, the storage unit of the present disclosure including the various preferred forms described above may be configured such that

The gate electrode layer of the first transfer transistor and the gate electrode layer of the second transfer transistor are connected to a word line, and

the word lines extend in a second direction different from a first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend (specifically, for example, in a second direction orthogonal to the first direction). It should be noted that, for convenience of description, such a form of the memory cell of the present disclosure as just described is sometimes referred to as "a memory cell of the second configuration of the present disclosure". Further, in this case, the storage unit of the present disclosure may be configured such that

[a] An orthographic projection image of the drain region, the channel formation region and the source region of the 1A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction is configured,

[b] configuring an orthographic projection image of the drain region, the channel formation region and the source region of the 1B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction, an

[c] An orthographic projection image of one source/drain region, the channel formation region, and the other source/drain region configuring the first transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction substantially overlaps with each other, and

[d] an orthographic projection image of the drain region, the channel formation region and the source region of the 2A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction is configured,

[e] configuring an orthographic projection image of the drain region, the channel formation region and the source region of the 2B-th transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction, an

[f] Orthogonal projection images of the one source/drain region, the channel formation region, and the other source/drain region configuring the second transfer transistor to a virtual plane (virtual vertical plane) perpendicular to the second direction substantially overlap with each other. Furthermore, the memory cells of the present disclosure may be configured such that, in the described configuration,

the first power supply line, the second power supply line, the first bit line, and the second bit line are arranged in a first stage, and

the word lines are arranged in a second level different from the first level. The first stage may be positioned on the substrate side relative to the second stage, or the second stage may be positioned on the substrate side relative to the first stage.

Further, the memory cell of the present disclosure including the various preferred forms described above may be formed such that the first power supply line and the second power supply line are not disposed above the first transfer transistor and the second transfer transistor.

The CMOS inverter circuit of the present disclosure may be formed such that

Drain regions of the pMOS transistor and the nMOS transistor are formed on the substrate, and

the common drain region-connection portion is formed on the substrate, or the CMOS inverter circuit of the present disclosure may be formed such that

A source region of the pMOS transistor and a source region of the nMOS transistor are formed on the substrate, and

the first power line and the second power line are formed on the substrate.

In the memory cell or CMOS inverter circuit of the present disclosure (hereinafter collectively referred to as "memory cell of the present disclosure or the like" in some cases) including the various preferred forms and configurations described above, as substrates, a silicon semiconductor substrate, an SOI (Si on insulator) substrate, and an SGOI (SiGe on insulator) substrate can be cited.

The memory cell and the like of the present disclosure may be formed such that various transistors have a nanowire structure, a nanosheet structure, or a nanotube structure. Further, the memory cell and the like of the present disclosure may be formed such that the channel formation region is covered with the gate insulating film over the entire periphery thereof, and the gate electrode layer is formed in contact with (i.e., on) the gate insulating film. In particular, the various transistors are vertical-structure transistors having a GAA (all-around gate) structure. In various transistors, for convenience of description, a stacked body of a drain region, a channel formation region, and a source region is sometimes referred to as a "channel structure portion". It is sufficient if the number of channel structure portions configuring one transistor is one or two or more among various transistors in the memory cell and the like of the present disclosure. Examples of a method for forming the channel structure portion include an epitaxial CVD method, a plasma CVD method, and an atomic layer CVD method.

As a material for configuring the channel structure portion of the nMOS transistor and the pMOS transistor, Si or SiGe, Ge, and InGaAs are cited. In particular, the memory cell and the like of the present disclosure may be formed such that, in the nMOS transistor, the channel structure portion is configured of silicon (Si), and, in the pMOS transistor, the channel structure portion is configured of silicon germanium (SiGe), germanium (Ge), or InGaAs.

However, this is not limitative, and the memory cell and the like of the present disclosure may be formed such that

The channel structure portion of the nMOS transistor is configured by silicon germanium (SiGe), and

the channel structure portion of the pMOS transistor is configured of silicon (Si), germanium (Ge), or InGaAs, or may be configured such that

The channel structure portion of the nMOS transistor is configured by germanium (Ge), and

the channel structure portion of the pMOS transistor is configured of silicon (Si), silicon germanium (SiGe), or InGaAS, or may be formed such that

The channel structure portion of the nMOS transistor is configured of InGaAs, and

the channel structure portion of the pMOS transistor is configured of silicon (Si), silicon germanium (SiGe), or germanium (Ge).

Here, from the viewpoint of obtaining an optimum work function of each MOS transistor, whether the MOS transistor is of an n-channel type or a p-channel type is determined only by the selection of a material for configuring the gate electrode layer. In the case where the channel structure portion is configured by Si and the semiconductor device is to be made into an n-channel type semiconductor device, TiN, TaN, Al, TiAl, and W can be cited as materials configuring the gate electrode layer. Meanwhile, in the case where the channel structure portion is configured of SiGe and the semiconductor device is to be made into a p-channel semiconductor deviceTiN and W may be cited as materials for configuring the gate electrode layer. As materials for disposing the gate insulating film, SiN, SiON, and SiO are cited₂Mention may also be made of materials of high dielectric constant (generally known as high-k materials), such as HfO₂HfAlON and Y₂O₃。

Alternatively, the channel structure portions of the nMOS transistor and the pMOS transistor may be configured by silicon (Si). In this case, as a material for disposing the gate electrode layer of the nMOS transistor, any one of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, and W and a compound containing a metal may be cited, and as a material for disposing the gate electrode layer of the pMOS transistor, any one of Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Os, Ir, Pt, and Au and a compound containing a metal may be cited.

In the nanowire structure or the nanotube structure, a drain region and a source region (or one source/drain region and another source/drain region) extend from opposite ends of a channel formation region in the form of a wire or tube having a diameter of, for example, 5 to 10 nm. Meanwhile, in the nanosheet structure, the drain region and the source region (or one source/drain region and the other source/drain region) extend from opposite ends of the channel forming region, which is generally rectangular in cross section and has a width x thickness of, for example, (10 to 50nm) × (5 to 10 nm).

As the conductive material or wiring material, for example, silicon (Si), aluminum or aluminum-based alloys (e.g., pure aluminum, Al-Si, Al-Cu, Al-Si-Cu, Al-Ge and Al-Si-Ge), polycrystalline silicon, copper alloys, tungsten alloys, titanium alloys (including TiW, TiNW, TiN and TiAl), WSi₂、MoSi₂And TaN. In the case where a substrate is provided on a silicon semiconductor substrate, although a plurality of insulating layers or interlayer insulating layers are provided on or above the substrate, SiO may be used as a material for providing the insulating layers or interlayer insulating layers_XBase material (material provided with silicon-based oxide film), such as SiO₂NSG (undoped silicate glass), BPSG (boron-phosphorus-silicate glass), PSG, BSG, AsSG, SbSG, PbSG, SOG (spin-on-glass), LTO (low temperature oxide, low temperature CVD-SiO)₂) Low melting point glass or glass paste; SiN-based materialIncluding SiON-based materials such as SiN or SiON; SiOC; SiOF; and SiCN. Alternatively, inorganic insulating materials such as titanium oxide (TiO) may also be cited₂) Tantalum oxide (Ta)₂O₅) Alumina (Al)₂O₃) Magnesium oxide (MgO), chromium oxide (CrO)_x) Zirconium oxide (ZrO)₂) Niobium oxide (Nb)₂O₅) Tin oxide (SnO)₂) And Vanadium Oxide (VO)_x). Alternatively, various resins such as polyimide-based resins, epoxy-based resins, and acrylic resins, or low dielectric constant insulating materials such as SiOCH, organic SOG, and fluorine resins (for example, dielectric constant k (═ epsilon/epsilon)₀) For example, 3.5 or less, and particularly, for example, fluorocarbons, perfluorocyclo-polymers, benzocyclobutene, cyclic fluororesins, polytetrafluoroethylene, amorphous tetrafluoroethylene, polyallyl ether, allyl fluoroether, polyimide fluoride, amorphous carbon, Parilen (parylene) and fluorinated fullerene. Also exemplified are silk (which is a trademark of dow chemical co) and a coating type interlayer insulating film material of low dielectric constant), torch (which is a trademark of honeywell electronic materials co and a polyallyl ether (PAE)) based material). Further, they may be used alone or in an appropriate combination. The insulating layer or the interlayer insulating layer may be formed based on well-known methods such as various CVD methods, various coating methods, various PVD methods including a sputtering method and a vacuum deposition method, various printing methods such as a screen printing method, an electroplating method, an electrodeposition method, a dipping method, and a sol-gel method.

In the memory cell and the like of the present disclosure, the voltage to be applied to the gate electrode layer of each transistor is, for example, 0.5 to 0.8 v. The memory cell and the CMOS inverter circuit of the present disclosure are applicable not only to a digital circuit such as a logic circuit but also to a logic circuit for performing control on, for example, an imaging device or a driving circuit of an imaging device (light receiving device) for configuring the imaging device. However, they are not limiting.

Working example 1

Working example 1 relates to a memory cell and a CMOS inverter circuit of the present disclosure, and particularly relates to a memory cell of a first form of the present disclosure and a memory cell of a first configuration of the present disclosure.

A schematic perspective view of a part of the memory cell of working example 1 is depicted in fig. 1, and an equivalent circuit diagram of the memory cell of working example 1 is depicted in fig. 2. A schematic partial cross-sectional view of a memory cell of working example 1, taken along arrow mark a-a of fig. 1 and 5, is depicted in fig. 4A; a schematic partial cross-sectional view of the memory cell of working example 1 taken along arrow mark B-B of fig. 1 and 5 is depicted in fig. 4B; and a schematic partial cross-sectional view of the memory cell of working example 1 taken along the arrow mark C-C of fig. 1 and 5 is depicted in fig. 4C. Further, conceptual diagrams configuring the arrangement state of the components of the storage unit of working example 1 when the storage unit of working example 1 is cut along the vertical horizontal plane including arrow marks a-a of fig. 4A, the virtual horizontal plane including arrow marks B-B of fig. 4A, the virtual horizontal plane including arrow marks C-C of fig. 4A, the virtual horizontal plane including arrow marks D-D of fig. 4A, the virtual horizontal plane including arrow marks E-E of fig. 4A, and the virtual horizontal plane including arrow marks F-F of fig. 4A are depicted in fig. 5, 6, 7, 8, 9, and 10. Further, a schematic perspective view of a part of the CMOS inverter circuit of working example 1 is depicted in fig. 3A, and an equivalent circuit diagram is depicted in fig. 3B. It should be noted that partial hatching is omitted in fig. 4A, 4B, and 4C. Further, in fig. 5, 6, 7, 8, 9, and 10, nine memory cells are depicted, and boundary lines between the memory cells are indicated by broken lines.

Each of the memory cells of working example 1 or working examples 2 to 4 described hereinafter is a memory cell including a flip-flop circuit including first and second CMOS inverter circuits and two transfer transistors TR₅And TR₆. The first CMOS inverter circuit includes a 1A-th transistor TR₁And a 1B transistor TR₂And the second CMOS inverter circuit includes a 2A-th transistor TR₃And a 2B transistor TR₄. Here, the 1 st crystalBody duct TR₁A pMOS transistor is included which includes the drain region 11, the channel formation region 12, and the source region 13 stacked together, and further includes a gate electrode layer 81. In addition, a 1B transistor TR₂An nMOS transistor is included which includes the drain region 21, the channel formation region 22, and the source region 23 stacked together, and further includes a gate electrode layer 81. In addition, the 2A transistor TR₃A pMOS transistor is included which includes the drain region 31, the channel formation region 32, and the source region 33 stacked together, and further includes the gate electrode layer 82. In addition, a 2B-th transistor TR₄An nMOS transistor is included which includes the drain region 41, the channel formation region 42, and the source region 43, and also includes the gate electrode layer 82. Transfer transistor TR₅And TR₆Each of which includes one source/drain region 51 or 61, a channel formation region 52 or 62, and another source/drain region 53 or 63, which are stacked together and include an nMOS transistor. However, the transfer transistor TR may be configured by a pMOS transistor in addition₅And TR₆Each of which.

Further, in the memory cell of any one of working example 1 or working examples 2 to 4 below, the 1A-th transistor TR₁Drain region 11 and 1B-th transistor TR₂Is connected to a common first drain region-connection 71,

2A transistor TR₃And the 2B-th transistor TR and the drain region 31 of₄Is connected to a common second drain region-connection 72,

1A transistor TR₁And a 1B transistor TR₂The common gate electrode layer (first gate electrode layer) 81 is connected to the second drain region-connecting portion 72 through the first gate electrode-connecting portion (through hole or connecting hole) 73,

2A transistor TR₃And a 2B transistor TR₄The common gate electrode layer (second gate electrode layer) 82 is connected to the first drain region-connecting portion 71 through the second gate electrode-connecting portion (through hole or connecting hole) 74,

1A transistor TR₁And the 2A transistor TR and the source region 13 of₃Is connected to a common first power supply line 91, and

1B transistor TR₂Source region 23 and 2B-th transistor TR₄Is connected to a common second power supply line 92.

Alternatively, in the memory cell of working example 1 or working example 2 described below, the 1A-th transistor TR₁And the 2A transistor TR and the source region 13 of₃Is connected to the common first power supply line 91 through the connection holes 14 and 34, and the 1B-th transistor TR₂Source region 23 and 2B-th transistor TR₄The source region 43 is connected to the common second power supply line 92 through the connection holes 24 and 44.

Further, the CMOS inverter circuit of any one of working example 1 or working examples 2 to 4 described below is configured such that

The CMOS inverter circuit includes

pMOS transistor TR₁Including the drain region 11, the channel formation region 12, and the source region 13 stacked together, and further including a gate electrode layer 81, an

nMOS transistor TR₂Including the drain region 21, the channel formation region 22, and the source region 23 stacked together, and further including a gate electrode layer 81,

pMOS transistor TR₁Drain region 11 and nMOS transistor TR₂Is connected to a common first drain region-connection 71,

pMOS transistor TR₁And an nMOS transistor TR₂The common gate electrode layer 81 is connected to the common gate wiring section 72 formed on the substrate 70 (particularly on the top surface portion of the substrate 70) through the gate electrode-connecting section (through hole or connecting hole) 73,

pMOS transistor TR₁Is connected to the first power supply line 91; and

nMOS transistor TR₂Is connected to the second power supply line 92.

Alternatively, the CMOS inverter circuit of any one of working example 1 or working examples 2 to 4 described below is configured such that

The CMOS inverter circuit includes

pMOS transistor TR₃Including the drain region 31, the channel formation region 32, and the source region 33 stacked together, and further including the gate electrode layer 82, an

nMOS transistor TR₄Including the drain region 41, the channel formation region 42, and the source region 43 stacked together, and further including a gate electrode layer 82,

pMOS transistor TR₃Drain region 31 and nMOS transistor TR₄Is connected to a common drain-region-connection 72,

pMOS transistor TR₃And an nMOS transistor TR₄The common gate electrode layer 82 is connected to the common gate wiring section 71 formed on the substrate 70 (particularly on the top surface portion of the substrate 70) through the gate electrode-connecting section (through hole or connecting hole) 74,

pMOS transistor TR₃Is connected to the first power supply line 91, and

nMOS transistor TR₄Is connected to the second power supply line 92.

Further, in the CMOS inverter circuit of working example 1 or working example 2 described below, the pMOS transistor TR₁And TR₃Drain regions 11 and 31 and nMOS transistor TR₂And TR₄Are formed on the substrate 70 (particularly directly above the substrate 70), and the common drain region-connecting portions 71 and 72 are formed on the substrate 70 (particularly on the top surface portion of the substrate 70).

Further, in the memory cell of working example 1 or working example 2 described below, the 1A-th transistor TR₁1B transistor TR₂2A transistor TR₃And a 2B transistor TR₄And the first transfer transistor TR, and the drain regions 11, 21, 31, and 41 of the first transistor₅And a second transfer transistor TR₆Is formed on the substrate 70 (particularly directly above the substrate 70), and the first drain region-connection portion 71 and the second drain region-connection portion 72 are formed on the substrate 70 (particularly on the top surface portion of the substrate 70). The first drain region-connecting portion 71 and the second drain region-connecting portion 72 include a high concentration impurity formed on the substrate 70 (particularly on the top surface portion of the substrate 70)A region or a layer of conductive material, or a layer comprising a resistive component, such as a diffusion resistive layer or a layer of metallic material surrounded by a layer of insulating material, so as to be insulated from the surrounding environment.

In the memory cell of working example 1, the first transfer transistor TR₅Is connected to the first bit line 93(BL) through the connection holes 54 and 55, and the second transfer transistor TR₆Is connected to the second bit line 94(BL') through the connection holes 64 and 65. First transfer transistor TR₅Is connected to the first drain region-connection portion 71, and the second transfer transistor TR₆Is connected to the second drain region-connection 72. The first power supply line 91, the second power supply line 92, the first bit line 93, and the second bit line 94 extend in the first direction, and are configured by a well-known wiring material. It should be noted that although the second bit line 94 is generally denoted by a symbol BL to which "-" is added, it is sometimes denoted as "BL" in this specification.

In the memory cell of working example 1 or working example 3 described below, the first CMOS inverter circuit and the second inverter circuit are arranged symmetrically twice with respect to the central axis of the memory cell. In fig. 5 or fig. 15, the central axis of one storage unit is represented by a black circle "CA".

In the memory cell of working example 1 or working example 3 described below, the first transfer transistor TR₅And a second transfer transistor TR₆The common gate electrode layer (third gate electrode layer) 83 also functions as a word line WL. The word lines WL extend in a second direction different from the first direction (specifically, for example, in a second direction orthogonal to the first direction) and are connected to the peripheral circuit. As shown in FIG. 9, an orthographic projection image of the first power line 91 and the 1A-th transistor TR₁Overlaps with a part of the orthogonally projected image of the source region 13 of (a) and also with the 2A-th transistor TR₃A part of the orthogonal projection images of the source region 33 of (a) overlap. Orthographic projection image of the second power line 92 and the 1B-th transistor TR₂Overlaps with a part of the orthogonally projected image of the source region 23 of (a) and also with the 2B-th transistor TR₄A part of the orthogonal projection images of the source region 43 of (a) overlap. However, the following orthogonal projection images do not substantially overlap each other:

[A]configuring the 1A-th transistor TR₁A drain region 11, a channel formation region 12, and a source region 13 (hereinafter sometimes referred to as "1A-th transistor TR" in some cases)₁The channel structure portion of) to a virtual vertical plane perpendicular to the first direction;

[B]configuring the 1B transistor TR₂A drain region 21, a channel formation region 22, and a source region 23 (hereinafter sometimes referred to as "1B-th transistor TR")₂Channel structure portion) to a virtual vertical plane perpendicular to the first direction,

[C]configuring the 2A transistor TR₃A drain region 31, a channel formation region 32, and a source region 33 (hereinafter sometimes referred to as "2A-th transistor TR₃The channel structure portion of) to a virtual vertical plane perpendicular to the first direction;

[D]configuring the 2B transistor TR₄A drain region 41, a channel formation region 42, and a source region 43 (hereinafter sometimes referred to as "2B-th transistor TR₄The channel structure portion of) to a virtual vertical plane perpendicular to the first direction;

[E]configuring the first transfer transistor TR₅One source/drain region 51, a channel formation region 52, and the other source/drain region 53 (hereinafter sometimes referred to as "first transfer transistor TR")₅An orthographic projection image of the channel structure portion "to a virtual perpendicular plane perpendicular to the first direction; and

[F]configuring the second transfer transistor TR₆One source/drain region 61, a channel formation region 62, and the other source/drain region 63 (hereinafter sometimes referred to as "second transfer transistor TR")₆The channel structure portion) to a virtual vertical plane perpendicular to the first direction. Here, the virtual horizontal plane and the virtual vertical plane indicate a virtual plane horizontal to the surface of the substrate and a virtual plane vertical to the surface of the substrate.

In addition, in the storage unit of working example 1 or working example 3 described below,

1A transistor TR₁And the 1B transistor TR₂Substantially overlap each other to a virtual vertical plane perpendicular to the second direction,

2A transistor TR₃And the 2B-th transistor TR₄To a virtual vertical plane perpendicular to the second direction, and

first transfer transistor TR₅And the second transfer transistor TR₆Substantially overlap each other to a virtual vertical plane perpendicular to the second direction.

Further, in the memory cell of working example 1, the first power supply line 91 and the second power supply line 92 are arranged in a first stage, and the first bit line 93 and the second bit line 94 are arranged in a second stage different from the first stage. Although in the illustrated example the first level is located on the substrate side with respect to the second level, the second level may be located on the substrate side with respect to the first level.

In addition, in the memory cell of working example 1 or working example 3 described below, the 1B-th transistor TR of a specific memory cell is configured₂Is connected to a 2B-th transistor TR arranged adjacent to the specific memory cell in the second direction₄The second power supply line 92 of the source region 43 (the memory cell is located on the boundary line extending in the first direction). Specifically, the 1B-th transistor TR of one memory cell is configured₂And a 2B-th transistor TR configuring a memory cell adjacent to one memory cell in the second direction₄Is connected to the same second power supply line 92. Applied to the first power supply line 91 is V_ddAnd applied to the second power supply line 92 is V_ss. At the first transfer transistor TR₅And a second transfer transistor TR₆The first power supply line 91 and the second power supply line 92 are not provided.

In any one of working example 1 or working examples 2 to 4 described below, the transistor TR₁、TR₂、TR₃、TR₄、TR₅And TR₆(for the sake of convenience of description, hereinafter sometimes referred to as "transistor TR₁Etc.) have nanowire structures. The channel formation regions 12, 22, 32, 42, 52, and 62 are covered with the gate insulating film 84 over the entire circumference thereof, and the gate electrode layers 81, 82, and 83 are formed in contact with the gate insulating film 84 (i.e., on the gate insulating film 84). The substrate 70 includes, for example, a silicon semiconductor substrate. At the transistor TR₁And the number of channel structure portions configuring one transistor may be one or two or more. nMOS transistor TR₂、TR₄、TR₅And TR₆Is configured of silicon (Si), and the pMOS transistor TR₁And TR₃Is configured from silicon germanium (SiGe). As a configuration nMOS transistor TR₂、TR₄、TR₅And TR₆Gate electrode layers 81 and 83 and pMOS transistor TR₁And TR₃TiN may be used as the material of the gate electrode layer 82. As the material for disposing the gate insulating film 84, SiN, SiON, and SiO are cited₂And may be exemplified by high dielectric constant materials (commonly referred to as high-k materials), such as HfO₂HfAlON and Y₂O₃And the like.

Hereinafter, an outline of a manufacturing method of the memory cell of working example 1 is described. However, the manufacturing method of the memory cell is not limited to the method described below.

[ step 100]

First, a device isolation region (not shown) having an STI (shallow trench isolation) structure is formed in a predetermined region of the substrate 70 including a silicon semiconductor substrate based on a well-known method so that an active region is not short-circuited.

[ step 110]

Then, in order to form a well, ion implantation is performed in a predetermined region of the substrate 70. Thereafter, a first drain region-connecting portion 71 and a second drain region-connecting portion 72 each including a high concentration impurity region are formed on the substrate 70 based on a well-known ion implantation method. Then, after an insulating layer 79A is formed on the entire region based on a well-known method, a second gate electrode-connecting portion (through hole or connecting hole) 74 and a first gate electrode-connecting portion (through hole or connecting hole) 73 are formed in the insulating layer 79A above the first drain region-connecting portion 71 and the second drain region-connecting portion 72, respectively.

[ step 120]

Then, a 1A transistor TR is formed in the insulating layer 79A₁Drain region 11 and 2A transistor TR₃Is formed at the portion of the drain region 31. Thereafter, based on the epitaxial growth method, a transistor TR configured of SiGe containing a p-type impurity is formed₁And forming a transistor TR configured by SiGe₁And then forming a transistor TR configured by SiGe containing p-type impurity₁Source regions 13 and 33. Then, the 1A-th transistor TR is covered with an appropriate mask material₁And a 2A transistor TR₃And source regions 13 and 33, and channel formation regions 12 and 32.

[ step 130]

Then, a 1B transistor TR is formed in the insulating layer 79A₂Drain region 21, 2B transistor TR₄Drain region 41 of the first transfer transistor TR₅And a source/drain region 51 and a second transfer transistor TR₆Is formed at a portion of one of the source/drain regions 61. Then, the drain regions 21 and 41 and one source/drain region 51 and 61 of the transistor configured by Si containing an n-type impurity are formed based on an epitaxial growth method, then the channel formation regions 22, 42, 52, and 62 of the transistor configured by Si are formed, and then the source regions 23 and 43 and the other source/drain region 53 and 63 of the transistor configured by Si containing an n-type impurity are formed. Thereafter, the mask material is removed.

[ step 140]

Then, based on a known method, the gate insulating film 84 forms the 1A-th transistor TR protruding on the insulating layer 79A₁Channel formation region 12, 1B-th transistor TR₂Channel formation region 22, 2A transistor TR₃Channel formation region 32, 2B-th transistor TR₄Channel formation region 42, first transfer transistor TR₅And the second transfer transistor TR and the channel formation region 52 of₆On the outer surface of the channel forming region 62. Although the gate insulating film 84 is also formed on the outer surfaces of the source regions 13, 23, 33, 43, 53, and 63 of the transistors, there is no problem even if the gate insulating film 84 is left at a portion. Further, the gate insulating film at these portions is not depicted.

[ step 150]

Thereafter, gate electrode layers 81, 82, 83 configured of TiN are formed on the insulating layer 79A so as to surround the 1A-th transistor TR formed protruding on the insulating layer 9A based on a known method₁1B transistor TR₂2A transistor TR₃2B transistor TR₄A first transfer transistor TR₅And a second transfer transistor TR₆The gate insulating film 84 on the outer surfaces of the channel forming regions 12, 22, 32, 42, 52, and 62.

[ step 160]

Then, an insulating layer 79B is formed over the entire region, and a planarization process is performed to expose the 1A-th transistor TR on the top surface of the insulating layer 79B₁1B transistor TR₂2A transistor TR₃2B transistor TR₄And the first transfer transistor TR and the top surfaces of the source regions 13, 23, 33, and 43₅And a second transfer transistor TR₆And the other source/drain regions 53 and 63.

[ step 170]

Thereafter, an interlayer insulating layer 79C is formed over the entire region, at the 1A-th transistor TR₁1B transistor TR₂2A transistor TR₃2B transistor TR₄An opening is formed at a portion of the interlayer insulating layer 79C above the source regions 13, 23, 33, and 43, and connection holes 14, 24, 34, and 44 and a first power supply line 91 and a second power supply line 92 are formed on the interlayer insulating layer 79C including the inside of the opening. In addition, in the first transfer transistor TR₅And a second transfer transistor TR₆An opening is formed at a portion of the interlayer insulating layer 79C above the source regions 53 and 63, and the connection holes 54 and 64 are formed in the opening.

[ step 180]

Then, an interlayer insulating layer 79D is formed over the entire region, openings are formed at portions of the interlayer insulating layer 79D above the connection holes 54 and 64, and the connection holes 55 and 65 and the first bit lines 93 and the second bit lines 94 are formed on the interlayer insulating layer 79D including the inside of the openings. The memory cell of working example 1 can be obtained in this manner.

In the memory cell of working example 1, the 1 st a transistor TR₁And a 1B transistor TR₂Are connected to a common first drain region-connection 71; 2A transistor TR₃And a 2B transistor TR₄To the common second drain region-connection 72; 1A transistor TR₁And a 1B transistor TR₂The common first gate electrode layer 81 is connected to the second drain region-connection portion 72 through the first gate electrode-connection portion 73; 2A transistor TR₃And a 2B transistor TR₄The common second gate electrode layer 82 is connected to the first drain region-connection 71 through the second gate electrode-connection 74; 1A transistor TR₁And a 1B transistor TR₂To the common first power supply line 91; and a 1B transistor TR₂And a 2B transistor TR₄Are connected to a common second power supply line 92. Therefore, a reduction in the area of the memory cell can be achieved. It should be noted that the area of the memory cell is 36 Δ²(6. DELTA. times.6. DELTA.). Further, although one word line WL, two bit lines 93 and 94, one first power supply line 91, and one second power supply line 92 are provided for one memory cell, the number of wiring layers for providing wirings may be three, and the number of wiring layers may be made smaller than in the past. Further, in the CMOS inverter circuit of working example 1, the pMOS transistor TR₁And TR₃Drain regions 11 and 31 and nMOS transistor TR₂And TR₄Are connected to the common drain-region-connection portions 71 and 72, and the pMOS transistor TR₁And TR₃And an nMOS transistor TR₂And TR₄The common gate electrode layer 82 is connected to the common gate wiring sections 72 and 71 formed on the substrate 70 (particularly on the top surface portion of the substrate 70) through the gate electrode-connecting sections 73 and 74. Therefore, the area of the CMOS inverter circuit can be reduced.

Although conceptual diagrams configuring the arrangement states of the components of the first modification and the second modification of the memory cell of working example 1 when the first modification and the second modification of the memory cell of working example 1 are cut along the virtual horizontal plane including the arrow mark a-a of fig. 4A are depicted in fig. 11 and 12, not only a form in which adjacent memory cells are symmetrically arranged with respect to the boundary line extending in the first direction (refer to fig. 11) but also a form in which adjacent memory cells are symmetrically arranged with respect to the boundary line extending in the second direction (refer to fig. 12) may be used. It should be noted that fig. 11 and 12 are conceptual diagrams similar to fig. 5.

Working example 2

Working example 2 is a modification of working example 1, and relates to a memory cell of the first form of the present disclosure and a memory cell of the second configuration of the present disclosure.

A schematic partial sectional view of the memory cell of working example 2 taken along arrow mark a-a of fig. 15 is depicted in fig. 13A, a schematic partial sectional view of the memory cell of working example 2 taken along arrow mark B-B of fig. 15 is depicted in fig. 13B, and an equivalent circuit diagram of the memory cell of working example 2 is depicted in fig. 14. Further, conceptual diagrams configuring the arrangement state of the components of the storage unit of the working example 2 when the storage unit of the working example 2 is cut along the virtual horizontal plane including the arrow mark a-a of fig. 13A, the virtual horizontal plane including the arrow mark B-B of fig. 13A, the virtual horizontal plane including the arrow mark C-C of fig. 13A, the virtual horizontal plane including the arrow mark D-D of fig. 13A, the virtual horizontal plane including the arrow mark E-E of fig. 13A, and the virtual horizontal plane including the arrow mark F-F of fig. 13A of the storage unit of the working example 2 are depicted in fig. 15, fig. 16, fig. 17, fig. 18, fig. 19, and fig. 20. It should be noted that in fig. 13A and 13B, a part of hatching is omitted, and in fig. 13B, a side face of the Word Line (WL)95 is depicted. Further, in fig. 15, 16, 17, 18, 19, and 20, eight memory cells are depicted, and boundary lines between the memory cells are indicated by broken lines.

In the storage unit of working example 2 or working example 4 described below, the first transferTransistor TR₅Gate electrode layer 85 and second transfer transistor TR₆The gate electrode layer 86 of (a) is connected to a Word Line (WL) 95. The word line WL extends in a second direction different from a first direction in which the first power supply line 91, the second power supply line 92, the first Bit Line (BL)93, and the second bit line (BL')94 extend (specifically, for example, extends in a second direction perpendicular to the first direction), and is connected to a peripheral circuit.

In particular, in the memory cell of working example 2 or working example 4 described below, the first transfer transistor TR₅The gate electrode layer 85 of (a) is connected to the word line 95 through a connection hole 87 formed in the interlayer insulating layer 79C. On the other hand, the second transfer transistor TR₆The gate electrode layer 86 of (a) is connected to the word line 95 through a connection hole 88 and a wiring portion 96 formed in the interlayer insulating layer 79C. The word line 95 and the wiring portion 96 are formed on the interlayer insulating layer 79D, and the connection holes 87 and 88 are provided on the insulating layer 79B and the interlayer insulating layers 79C and 79D.

In the memory cell of working example 2, the first transfer transistor TR₅Is connected to a first Bit Line (BL)93 through a connection hole 54 provided in the interlayer insulating layer 79C, and a second transfer transistor TR₆Is connected to the second bit line 94(BL') through the connection hole 64 provided in the interlayer insulating layer 79C. 1A transistor TR₁And the 2A transistor TR and the source region 13 of₃The source region 33 is connected to the common first power supply line 91 through the connection holes 14 and 34 formed in the interlayer insulating layer 79C. 1B transistor TR₂And a 2B transistor TR₄The source regions 23 and 43 are connected to the common second power supply line 92 through connection holes 24 and 44 formed in the interlayer insulating layer 79C. 1A transistor TR₁Drain region 11, 1B-th transistor TR₂And the first transfer transistor TR and the drain region 21 of₅Is connected to the first drain region-connection portion 71, and the 2A-th transistor TR₃Drain region 31 of the 2B-th transistor TR₄And the second transfer transistor TR and the drain region 41 of₆Is connected to the second drain region-connection 72. At the first transfer transistor TR₅And a firstTwo transfer transistors TR₆Above, the first power supply line 91 and the second power supply line 92 are not provided. A first power supply line 91, a second power supply line 92, a first bit line 93, and a second bit line 94 are formed on the interlayer insulating layer 79C.

Further, in the memory cell of working example 2 or embodiment 4 described below, adjacent memory cells are arranged symmetrically with respect to the boundary line extending in the first direction, the boundary line extending in the second direction, or the boundary lines extending in the first and second directions. In the illustrated example, adjacent memory cells are arranged line-symmetrically with respect to a boundary line extending in the first direction and a boundary line extending in the second direction. Further, the first CMOS inverter circuit and the second inverter circuit are arranged symmetrically twice with respect to the central axis of the memory cell. In fig. 15 and 36, the central axis of one storage unit is indicated by a black circle "CA".

In addition, in the memory cell of working example 2 or embodiment 4 described below,

[a]1A transistor TR₁To a virtual vertical plane perpendicular to the second direction,

[b]1B transistor TR₂To a virtual vertical plane perpendicular to the second direction, an

[c]First transfer transistor TR₅To a virtual vertical plane perpendicular to the second direction substantially overlap each other, and

[d]2A transistor TR₃To a virtual vertical plane perpendicular to the second direction,

[e]2B transistor TR₄To a virtual vertical plane perpendicular to the second direction, an

[f]Second transfer transistor TR₆Substantially overlap each other in an orthographic projection image to a virtual vertical plane perpendicular to the second direction.

Further, in the memory cell of working example 2, the first power supply line 91, the second power supply line 92, the first bit line 93, and the second bit line 94 are arranged in a first stage, and the word line 95 is arranged in a second stage different from the first stage. Although in the illustrated example the first level is located on the substrate side with respect to the second level, the second level may be located on the substrate side with respect to the first level.

Since the memory cell of working example 2 can be made substantially similar in configuration and structure to the memory cell of working example 1 except for the above-described matters, detailed description thereof is omitted.

Working example 3

Although working example 3 is also a modification of working example 1, it relates to the memory cell of the second form of the present disclosure and the memory cell of the first configuration of the present disclosure.

A schematic partial cross-sectional view of the memory cell of working example 3 taken along arrow mark a-a of fig. 24 is depicted in fig. 21A; a schematic partial sectional view of the memory cell of working example 3 taken along arrow mark B-B of fig. 24 is depicted in fig. 21B; fig. 21C depicts a schematic partial cross-sectional view of the memory cell of working example 3 taken along arrow mark C-C of fig. 24; a schematic partial cross-sectional view of the memory cell of working example 3 taken along arrow mark D-D of fig. 24 is depicted in fig. 22A; and a schematic partial sectional view of the memory cell of working example 3 taken along arrow mark E-E of fig. 24 is depicted in fig. 22B. Further, an equivalent circuit diagram of the memory cell of working example 3 is depicted in fig. 23. Further, conceptual diagrams configuring the arrangement state of the components of the storage unit of working example 3 when the storage unit of working example 3 is cut along the virtual horizontal plane including arrow marks a-a of fig. 21A, the virtual horizontal plane including arrow marks B-B of fig. 21A, the virtual horizontal plane including arrow marks C-C of fig. 21A, the virtual horizontal plane including arrow marks D-D of fig. 21A, and the virtual horizontal plane including arrow marks E-E of fig. 21A are depicted in fig. 24, 25, 26, 27, and 28. Note that in fig. 21A, 21B, 21C, 22A, and 22B, a part of hatching is omitted. Further, in fig. 24, 25, 26, 27, and 28, six memory cells are depicted, and boundary lines between the memory cells are indicated by broken lines.

In the memory cell of working example 3, the 1 st a transistor TR₁1B transistor TR₂2A transistor TR₃And a 2B transistor TR₄And the first transfer transistor TR, and source regions 13, 23, 33, and 43₅And a second transfer transistor TR₆Is formed on the substrate 70 (particularly directly above the substrate 70), and the first and second power supply lines 91 and 92 are formed on the substrate 70 (particularly on the top surface portion of the substrate 70). The first power supply line 91 and the second power supply line 92 each include a high-concentration impurity region or a conductive material layer formed on the substrate 70 (particularly on the top surface portion of the substrate 70), or a metal material layer surrounded by an insulating material layer and insulated from the surroundings.

1A transistor TR₁1B transistor TR₂2A transistor TR₃2B transistor TR₄A first transfer transistor TR₅And a second transfer transistor TR₆Is covered with an interlayer insulating layer 79C, and an interlayer insulating layer 79D is formed on the interlayer insulating layer 79C.

1A transistor TR₁And the 2A transistor TR and the source region 13 of₃Is connected to a common first power supply line 91, and a 1B transistor TR₂Source region 23 and 2B-th transistor TR₄Is connected to a common second power supply line 92.

In addition, the 1A-th transistor TR₁Is connected to the first drain region-connecting portion 71 through the connection hole 14 provided in the interlayer insulating layer 79C, and the 1B-th transistor TR₂Is connected to the first drain region-connecting portion 71 through the connecting hole 24 provided in the interlayer insulating layer 79C. First transfer transistor TR₅Is connected to the first drain region-connecting portion 71 through the connecting hole 54 provided in the interlayer insulating layer 79C. 2A transistor TR₃Is connected to the second drain region-connecting portion 72 through the connecting hole 34 provided in the interlayer insulating layer 79C, and the 2B-th transistor TR₄Is connected through a connection hole 44 provided in an interlayer insulating layer 79CTo the second drain region-connection 72. Second transfer transistor TR₆Is connected to the second drain region-connecting portion 72 through a connecting hole 64 provided in the interlayer insulating layer 79C.

First transfer transistor TR₅Is connected to the first bit line 93 provided on the interlayer insulating layer 79D through the connection portion 75 and the connection hole 76, the connection portion 75 includes a high concentration impurity region or a conductive material layer provided on the substrate 70 (particularly on the top surface portion of the substrate 70), and the connection hole 76 is connected to the connection portion 75 and provided in the insulating layers 79A and 79B and the interlayer insulating layers 79C and 79D. Second transfer transistor TR₆Is connected to a second bit line 94 provided on the interlayer insulating layer 79D through a connection portion 77 and a connection hole 78, the connection portion 77 including a high concentration impurity region or a conductive material layer provided on the substrate 70 (particularly on the top surface portion of the substrate 70), the connection hole 78 being connected to the connection portion 77 and provided in the insulating layers 79A and 79B and the interlayer insulating layers 79C and 79D.

1A transistor TR₁And a 1B transistor TR₂The common first gate electrode layer 81 is connected to the second drain region-connecting portion 72 through the first gate electrode-connecting portion 73 provided on the insulating layer 79B and the interlayer insulating layer 79C, and the 2A-th transistor TR₃And a 2B transistor TR₄The common second gate electrode layer 82 is connected to the first drain region-connecting portion 71 through the second gate electrode-connecting portion 74 provided on the insulating layer 79B and the interlayer insulating layer 79C.

The first power line 91, the second power line 92, the first bit line 93, and the second bit line 94 extend in a first direction, and the first transfer transistor TR₅And a second transfer transistor TR₆The common gate electrode layer (third gate electrode layer) 83 also functions as a word line WL and extends in the second direction.

Further, in the CMOS inverter circuit of working example 3, the pMOS transistor TR₁And TR₃Source regions 13 and 33 and nMOS transistor TR₂And TR₄Are formed on the substrate 70 (particularly, directly above the substrate 70), and the first power supply line 91 and the second power supply lineThe line 92 is formed on the substrate 70 (particularly on the top surface portion of the substrate 70).

Since the memory cell of working example 3 can be made substantially similar in configuration and structure to the memory cell of working example 1 except for the above points, detailed description thereof is omitted. It should be noted that although the area of the memory cell of working example 3 was 48 Δ²And the area of the region occupied by the conventional SRAM memory cell shown in fig. 52B is the same, but a reduction in the number of wiring layers is achieved.

As shown in fig. 29, fig. 29 is a conceptual diagram similar to the first modification of working example 3 of fig. 25, and a form may also be adopted in which adjacent memory cells are arranged line-symmetrically with respect to a boundary line extending in the first direction.

Working example 4

Working example 4 is a modification of working example 2, and relates to a storage unit of the second form of the present disclosure and a storage unit of the second configuration of the present disclosure.

A schematic partial sectional view of the memory cell of working example 4 taken along arrow mark a-a of fig. 36 is depicted in fig. 30A; a schematic partial sectional view of the memory cell of working example 4 taken along arrow mark B-B of fig. 36 is depicted in fig. 30B; and an equivalent circuit diagram of the memory cell of working example 4 is depicted in fig. 31. Further, conceptual diagrams configuring the arrangement state of the components of the storage unit of the working example 4 when the storage unit of the working example 4 is cut along the virtual horizontal plane including the arrow mark a-a of fig. 30A, the virtual horizontal plane including the arrow mark B-B of fig. 30A, the virtual horizontal plane including the arrow mark C-C of fig. 30A, the virtual horizontal plane including the arrow mark D-D of fig. 30A, the virtual horizontal plane including the arrow mark E-E of fig. 30A, and the virtual horizontal plane including the arrow mark F-F of fig. 30A are depicted in fig. 32, 33, 34, 35, 36, and 37. It should be noted that in fig. 30A and 30B, a part of hatching is omitted, and in fig. 30B, the side of the Word Line (WL)95 is depicted. Further, in fig. 32, 33, 34, 35, 36, and 37, eight memory cells are depicted, and boundary lines between the memory cells are indicated by broken lines.

In the memory cell of working example 4, the 1 st a transistor TR₁1B transistor TR₂2A transistor TR₃And a 2B transistor TR₄And the first transfer transistor TR, and source regions 13, 23, 33, and 43₅And a second transfer transistor TR₆Is formed on the substrate 70 (particularly, directly above the substrate 70), and the first power supply line 91, the second power supply line 92, the first bit line 93, and the second bit line 94 are formed on the substrate 70 (particularly, on the top surface portion of the substrate 70). The first power supply line 91, the second power supply line 92, the first bit line 93, and the second bit line 94 include a high-concentration impurity region or a conductive material layer formed on the substrate 70 (particularly on the top surface portion of the substrate 70), or include a metal material layer surrounded by an insulating material layer and insulated from the surrounding environment.

In the memory cell of working example 4, the first transfer transistor TR₅Is connected to the first bit line 93(BL), and the second transfer transistor TR₆Is connected to a second bit line 94 (BL'). 1A transistor TR₁And the 2A transistor TR and the source region 13 of₃Is connected to a common first power supply line 91. 1B transistor TR₂And a 2B transistor TR₄Are connected to a common first power supply line 92. 1A transistor TR₁Drain region 11, 1B-th transistor TR₂And the first transfer transistor TR and the drain region 21 of₅Is connected to the first drain region-connecting portion 71 through the connection holes 14, 24 and 54, and the 2A-th transistor TR₃Drain region 31 of the 2B-th transistor TR₄And a second transfer transistor TR and a drain region 41 of₆Is connected to the second drain region-connection portion 72 through the respective connection holes 34, 44 and 64. The first drain region-connecting portion 71 and the second drain region-connecting portion 72 are disposed on the interlayer insulating layer 79C. At the first transfer transistor TR₅And a second transfer transistor TR₆The first power supply line 91 and the second power supply line 92 are not provided.

1A transistor TR₁And a 1B transistor TR₂The common first gate electrode layer 81 is connected to the second drain region-connecting portion 72 through the first gate electrode-connecting portion 73 provided on the insulating layer 79B and the interlayer insulating layer 79C, and the 2A-th transistor TR₃And a 2B transistor TR₄A common gate electrode layer (second gate electrode layer) 82 is connected to the first drain connecting portion 71 through a second gate electrode-connecting portion 74 provided on the insulating layer 79B and the interlayer insulating layer 79C.

Since the memory cell of working example 4 can be made substantially similar in configuration and structure to the memory cell of working example 2 except for the above points, detailed description thereof is omitted.

Although the present disclosure has been described based on the preferred working examples, the configuration and structure of the memory cell or the CMOS inverter circuit, the material configuring the memory cell or the CMOS inverter circuit, and the manufacturing method of the memory cell or the CMOS inverter circuit described in connection with the working examples are exemplary and may be appropriately changed. Further, the order of steps in the manufacturing method of the memory cell described above in connection with working example 1 may be appropriately changed as necessary. Although in the description of the working example, the channel structure portion is described based on the nanowire structure, a nanosheet structure or a nanotube structure may also be used. Instead of the silicon semiconductor substrate, an SOI substrate may be used as the substrate.

The memory cell (SRAM) of the present disclosure is applicable to both 2-port-SRAM and dual-port-SRAM.

A schematic partial sectional view of a third modification of the memory cell of working example 1 taken along arrow marks a-a, B-B, and C-C of fig. 39 is depicted in fig. 38A, 38B, and 38C. Further, the arrangement state of the components configuring the third modification of the storage unit of working example 1 when the third modification of the storage unit of working example 1 is cut along the virtual horizontal plane including arrow mark a-a of fig. 38A, the virtual horizontal plane including arrow mark B-B of fig. 38A, the virtual horizontal plane including arrow mark C-C of fig. 38A, the virtual horizontal plane including arrow mark D-D of fig. 38A, the virtual horizontal plane including arrow mark E-E of fig. 38A, and the virtual horizontal plane including arrow mark F-F of fig. 38A is depicted in the conceptual diagrams of fig. 39, 40, 41, 42, 43, and 44. In the memory cell of the third modification of working example 1, unlike the memory cell described above in conjunction with working example 1,

[A] an orthographic projection image of the drain region, the channel formation region and the source region of the 1A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction is configured, and

[C] orthographic projection images of the drain region, the channel formation region and the source region configuring the 2A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction overlap with each other, and

[B] orthographic projection images of the drain region, the channel formation region and the source region of the 1B-th transistor on a virtual plane (virtual vertical plane) perpendicular to the first direction are arranged so as to overlap each other as described above, and

[D']the drain region, the channel formation region and the source region of the 2B-th transistor are arranged with a gap between orthogonal projection images to a virtual plane (virtual vertical plane) perpendicular to the first direction, the 2B-th transistor being TR with the 1B-th transistor TR₂Adjacent 2B transistor TR₄. The first power line 91 is located at the 1A-th transistor TR₁And a 1B transistor TR₂Above (b). On the other hand, the second power supply line 92 is located at the 1B-th transistor TR₂And a 1B transistor TR₂Adjacent 2B transistor TR₄Above the region in between. Specifically, although the orthogonal projection image of the first power supply line 91 is orthogonal to the 1A-th transistor TR₁And a 1B transistor TR₂Is overlapped, but the second power supply line 92 is not connected to the 1B-th transistor TR₂And a 2B transistor TR₄Overlap. The first bit line 93 is opposite to the first transfer transistor TR₅In the 1B transistor TR₂Is located above in a shifted relationship on the side, and the second bit line 94 is opposed to the second transfer transistor TR₆In the 2B transistor TR₄On the side, in displaced relation, above. In particular, the first and second bit lines 93 and 94 are disposed over a region located between the first and second power supply lines 91 and 92, and orthogonal projections of the first and second bit lines 93 and 94The image does not overlap the orthographic projection images of the first power supply line 91 and the second power supply line 92.

Further, the arrangement state of the components configuring the fourth modification of the storage unit of working example 1 when the fourth modification of the storage unit of working example 1 is cut along the virtual horizontal plane including arrow mark a-a of fig. 38A, the virtual horizontal plane including arrow mark B-B of fig. 38A, the virtual horizontal plane including arrow mark C-C of fig. 38A, the virtual horizontal plane including arrow mark D-D of fig. 38A, the virtual horizontal plane including arrow mark E-E of fig. 38A, and the virtual horizontal plane including arrow mark F-F of fig. 38A is depicted in the conceptual diagrams of fig. 45, 46, 47, 48, 49, and 50. In the memory cell of the fourth modification of working example 1, unlike the memory cell described above in conjunction with working example 1,

[A] an orthographic projection image of the drain region, the channel formation region and the source region of the 1A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction is configured, and

[C]orthogonal projection images of the drain region, the channel formation region, and the source region of the 2A-th transistor to a virtual plane (virtual vertical plane) perpendicular to the first direction are configured so as not to overlap with each other as described above, and further, a gap is provided between the orthogonal projection images. The first power line 91 is located at the 1A-th transistor TR₁And a 1B transistor TR₂Above the region therebetween, and the second power supply line 92 is positioned at the 1B-th transistor TR₂And a 2B transistor TR₄And a 1B transistor TR₂Above the adjacent region. The orthogonally projected image of the first power line 91 does not coincide with the 1A-th transistor TR₁And a 1B transistor TR₂Is overlapped and the second power supply line 92 is not overlapped with the 1B-th transistor TR₂And a 2B transistor TR₄Overlap. The first bit line 93 is located at the first transfer transistor TR₅And the second bit line 94 is located above the second transfer transistor TR₆Above (b).

The positions of the connection holes 87 and 88 may be changed as shown in fig. 51, and fig. 51 depicts a conceptual diagram of the arrangement state of the components configuring the first modification of the storage unit of working example 2 when the first modification of the storage unit of working example 2 is cut along a virtual horizontal plane similar to that shown in fig. 17.

Although in the working example, the first power supply line is made common to the source region of the 1A transistor and the source region of the 2A transistor and the second power supply line is made common to the source regions of the 1B transistor and the 2B transistor, in some cases, the first power supply line may be made common to the source region of the 1A transistor and the source region of the 2A transistor while two second power supply lines are connected to the source region of the 1B transistor and the source region of the 2B transistor, respectively, or the two first power supply lines may be connected to the source region of the 1A transistor and the source region of the 2A transistor, respectively, while the second power supply line is made common to the source region of the 1B transistor and the source region of the 2B transistor.

It should be noted that the present disclosure may also have a configuration as described below.

[A01]

Imaging device

A memory cell, comprising:

a flip-flop circuit including a first CMOS inverter circuit and a second inverter circuit; and

two transmission transistors, wherein

The first CMOS inverter comprises

A 1A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 1B transistor including an nMOS transistor including a drain region, a channel formation region and a source region stacked together and further including a gate electrode layer, and a second CMOS inverter circuit including

A 2A transistor including a pMOS transistor including a drain region, a channel formation region and a source region stacked together, and further including a gate electrode layer, and

a 2B transistor including an nMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer,

each of the transfer transistors includes a drain region, a channel formation region, and a source region stacked together, and further includes a gate electrode layer;

the drain region of the 1A-th transistor and the drain region of the 1B-th transistor are connected to a common first drain region-connection,

the drain region of the 2A-th transistor and the drain region of the 2B-th transistor are connected to a common second drain region-connection,

the gate electrode layer common to the 1A-th transistor and the 1B-th transistor is connected to the second drain region-connecting portion via a first gate electrode-connecting portion,

the gate electrode layer common to the 2A-th transistor and the 2B-th transistor is connected to the first drain region-connecting portion via a second gate electrode-connecting portion,

the source region of the 1A transistor and the source region of the 2A transistor are connected to a common first power supply line, and

the source region of the 1B-th transistor and the source region of the 2B-th transistor are connected to a common second power supply line.

[A02]

The memory cell according to [ A01], wherein

Drain regions of the 1A th transistor, the 1B th transistor, the 2A th transistor and the 2B th transistor and one source/drain region of the first transfer transistor and the second transfer transistor are formed on the substrate,

the first drain region-connecting portion and the second drain region-connecting portion are formed on the substrate.

[A03]

The memory cell according to [ a02], wherein the first drain region-connecting portion and the second drain region-connecting portion each include a high concentration impurity region or a conductive material layer formed on the substrate.

[A04]

The memory cell according to [ A01], wherein

Source regions of the 1A, 1B, 2A and 2B transistors and one source/drain region of the first and second transfer transistors are formed on the substrate, and

the first power line and the second power line are formed on the substrate.

[A05]

The memory cell according to [ a04], wherein the first power supply line and the second power supply line each include a high concentration impurity region or a conductive material layer formed on the substrate.

[A06]

The memory cell according to any one of [ A01] to [ A05], wherein

The other source/drain region of the first transfer transistor is connected to a first bit line,

the other source/drain region of the second pass transistor is connected to a second bit line,

one source/drain region of the first transfer transistor is connected to the first drain region-connecting portion, and

one source/drain region of the second transfer transistor is connected to the second drain region-connecting portion.

[A07]

The memory cell according to [ a06], wherein the first power supply line, the second power supply line, the first bit line, and the second bit line extend in a first direction.

[A08]

The memory cell according to any one of [ a01] to [ a07], wherein assuming that a direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend is a first direction, and assuming that a direction orthogonal to the first direction is a second direction, adjacent memory cells are arranged line-symmetrically with respect to a boundary line extending in the first direction, a boundary line extending in the second direction, or boundary lines extending in the first direction and the second direction.

[A09]

The memory cell according to any one of [ a01] to [ a08], wherein the first CMOS inverter circuit and the second inverter circuit are symmetrically arranged twice with respect to a central axis of the memory cell.

[A10]

The memory cell according to any one of [ A01] to [ A9], wherein

The gate electrode layer common to the first transfer transistor and the second transfer transistor also serves as a word line, and

the word lines extend in a second direction different from a first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend.

[A11]

The memory cell according to [ A10], wherein

The orthographic projection image of the first power supply line overlaps with a part of the orthographic projection image of the source region of the 1A-th transistor and also overlaps with a part of the orthographic projection image of the source region of the 2A-th transistor, and

the orthographic projection image of the second power supply line overlaps a part of the orthographic projection image of the source region of the 1B-th transistor and also overlaps a part of the orthographic projection image of the source region of the 2B-th transistor.

[A12]

The memory cell according to [ A10] or [ A11], wherein an orthogonal projection image of the drain region, the channel formation region and the source region of the 1A-th transistor and the drain region, the channel formation region and the source region of the 1B-th transistor to a virtual plane perpendicular to the first direction is configured, an orthogonal projection image of the drain region, the channel formation region and the source region of the 2A-th transistor and the drain region, the channel formation region and the source region of the 2B-th transistor to a virtual plane perpendicular to the first direction is configured, an orthogonal projection image of one source/drain region, the channel formation region and the other source/drain region of the first transfer transistor to a virtual plane perpendicular to the first direction is configured, and configuring one source/drain region, the channel formation region, and the other source/drain region of the second transfer transistor to be substantially non-overlapping with each other in orthogonal projection images to a virtual plane perpendicular to the first direction.

[A13]

The memory cell according to any one of [ A10] to [ A12], wherein

Orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1A-th transistor to a virtual plane perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 1B-th transistor to a virtual plane perpendicular to the second direction substantially overlap each other,

orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2A-th transistor to a virtual plane perpendicular to the second direction and orthogonal projection images of the drain region, the channel formation region, and the source region configuring the 2B-th transistor to a virtual plane perpendicular to the second direction substantially overlap each other, and

an orthogonal projection image of the one source/drain region, the channel formation region, and the other source/drain region configuring the first transfer transistor to a virtual plane perpendicular to the second direction and an orthogonal projection image of the one source/drain region, the channel formation region, and the other source/drain region configuring the second transfer transistor to a virtual plane perpendicular to the second direction substantially overlap each other.

[A14]

The memory cell according to any one of [ A10] to [ A13], wherein

The first power supply line and the second power supply line are arranged in a first stage, and

the first bit lines and the second bit lines are arranged in a second level different from the first level.

[A15]

The memory cell according to any one of [ A01] to [ A09], wherein

A gate electrode layer common to the first transfer transistor and the second transfer transistor is connected to a word line, and

the word lines extend in a second direction different from a first direction in which the first power supply line, the second power supply line, the first bit line, and the second bit line extend.

[A16]

The memory cell according to [ A15], wherein

An orthographic projection image of the drain region, the channel formation region and the source region of the 1A-th transistor to a virtual plane perpendicular to the second direction is configured, an orthographic projection image of the drain region, the channel formation region and the source region of the 1B-th transistor to a virtual plane perpendicular to the second direction is configured, and an orthographic projection image of one source/drain region, the channel formation region and the other source/drain region of the first transfer transistor are configured to substantially overlap each other, and

an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 2A-th transistor to a virtual plane perpendicular to the second direction, an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 2B-th transistor to a virtual plane perpendicular to the second direction, and an orthogonal projection image of one source/drain region, the channel formation region, and the other source/drain region configuring the second transfer transistor substantially overlap each other.

[A17]

The memory cell according to [ A15] or [ A16], wherein

The first power supply line, the second power supply line, the first bit line, and the second bit line are arranged in a first stage, and

the word lines are arranged in a second level different from the first level.

[A18]

The memory cell according to any one of [ a01] to [ a17], wherein the first power supply line and the second power supply line are not provided above the first transfer transistor and the second transfer transistor.

[B01]

CMOS inverter circuit

A CMOS inverter circuit comprising:

a pMOS transistor including a drain region, a channel formation region, and a source region stacked together, and further including a gate electrode layer; and

an nMOS transistor comprising a drain region, a channel formation region and a source region stacked together, and further comprising a gate electrode layer, wherein

The drain regions of the pMOS transistor and the drain regions of the nMOS transistor are connected to a common drain region-connecting portion,

a gate electrode layer common to the pMOS transistor and the nMOS transistor is connected to a common gate wiring portion formed on the substrate through a gate electrode-connecting portion,

the source region of the pMOS transistor is connected to a first power supply line, and

the source region of the nMOS transistor is connected to the second power supply line.

[B02]

The CMOS inverter circuit according to [ B01], wherein

Drain regions of the pMOS transistor and the nMOS transistor are formed on the substrate, and

the common drain region-connecting portion is formed on the substrate.

[B03]

The CMOS inverter circuit according to [ B01], wherein

A source region of the pMOS transistor and a source region of the nMOS transistor are formed on the substrate, an

The first power line and the second power line are formed on the substrate.

[ list of reference numerals ]

TR₁… transistor 1A, TR₂… transistor 1B, TR₃… transistor 2A, TR₄… transistor 2B, TR₅… first transfer transistor, TR₆… second transfer transistor, drain region 11, 21, 31, 41 …, source/drain region 51, 61 … one source/drain region, channel formation region 12, 22, 32, 42, 52, 62 …, source region 13, 23, 33, 43 …, source region 53, 63 … another source/drain region, 14, 24, 34, 44, 54, 55, 64, 65, 76, 78, 87, 88 … connection hole, 70 … substrate, 71.. first drain region-connecting portion (gate wiring portion), 72 … second drain region-connecting portion (gate wiring portion), 73 … first gate electrode-connecting portion (through hole or connection hole), 74 … second gate electrode-connecting portion (through hole or connection hole), 75, 77 … connecting portion, 79A, 79B … insulating layer, 79C, 79D … interlayer insulating layer, 81 … (first gate electrode layer), 82 … (second gate electrode layer), 83 … gate electrode layer (third gate electrode), 84 … gate insulating film, 85 … gate electrode layer of first transfer transistor, 86 … gate electrode layer of second transfer transistor, 91 … first power supply line, 92 … second power supply line, 93 … first bit line, 94 … second bit line (BL'), 95 … word line, 96 … wiring section.