阅读说明：本技术 自动化fpga验证系统 (Automatic FPGA verification system ) 是由 谢宝森 于 2020-12-12 设计创作，主要内容包括：本申请实施例提供一种自动化FPGA验证系统,包括：用于装载逻辑设计代码的第一FPGA芯片组、用于IO MUX功能切换的第二FPGA芯片组以及多个外围电路,所述第二FPGA芯片组与所述外围电路连接；所述第一FPGA芯片组和所述第二FPGA芯片组通过通信接口和芯片IO口连接,所述芯片IO口用于对所述外围电路的功能信号进行功能复用,所述通信接口用于在所述芯片IO口进行功能复用时,实现所述第一FPGA芯片组和所述第二FPGA芯片组的同步配合。本申请能够快速、准确和便捷的实现FPGA的自动化验证。(The embodiment of the application provides an automatic FPGA verification system, which comprises: the FPGA chip comprises a first FPGA chip set used for loading logic design codes, a second FPGA chip set used for switching IO MUX functions and a plurality of peripheral circuits, wherein the second FPGA chip set is connected with the peripheral circuits; the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing. The method and the device can realize automatic verification of the FPGA quickly, accurately and conveniently.)

1. An automatic FPGA verification system is characterized by comprising a first FPGA chipset for loading a logic design code, a second FPGA chipset for switching IO MUX functions and a plurality of peripheral circuits, wherein the second FPGA chipset is connected with the peripheral circuits;

the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing.

2. The automated FPGA verification system according to claim 1, wherein when verifying the multiplexing function of the IO port, the first FPGA chipset sets the IO port as a first function signal of a peripheral circuit, and simultaneously notifies the second FPGA chipset through the communication interface to synchronously switch the IO port to the first function signal, so as to connect the IO port of the first FPGA chipset with the peripheral circuit, thereby realizing the IO port multiplexing function using the peripheral circuit verification logic design.

Technical Field

The application relates to the technical field of chips, in particular to an automatic FPGA verification system.

Background

In the chip design process, in order to ensure the accuracy of the logic design, the logic design needs to be verified by using an FPGA verification platform.

The traditional FPGA verification platform consists of an FGPA chip and a peripheral circuit thereof, wherein the FGPA chip is connected with the peripheral circuit through a fixed IO (input/output) port.

On a traditional FPGA verification platform, when IO MUX (input/output port multiplexing) functions of logic design need to be verified, logic code modification is needed to verify each IO MUX function, so that IO of the logic design can correspond to IO of peripheral circuits of the FPGA verification platform. In this way, the following problems may occur:

1. in the verification process, the modification of the logic code destroys the originality of the logic code, and possibly omits or brings a new BUG;

2. the logic code needs to be modified once when one IO MUX function is verified, the workload is large, and the verification consumes long time;

therefore, the inventor provides an automatic FPGA verification system by virtue of experience and practice of related industries for many years so as to overcome the defects of the prior art.

Disclosure of Invention

Aiming at the problems in the prior art, the application provides an automatic FPGA verification system which can realize the automatic verification of the FPGA quickly, accurately and conveniently.

In order to solve the technical problem, the application provides the following technical scheme:

in a first aspect, the present application provides an automated FPGA verification system, including: the FPGA chip comprises a first FPGA chip set used for loading logic design codes, a second FPGA chip set used for switching IO MUX functions and a plurality of peripheral circuits, wherein the second FPGA chip set is connected with the peripheral circuits;

the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing.

Further, when the multiplexing function of the IO port is verified, the first FPGA chipset sets the IO port as a first functional signal of the peripheral circuit, and simultaneously notifies the second FPGA chipset through the communication interface to synchronously switch the IO port to the first functional signal, so that the IO port of the first FPGA chipset is connected with the peripheral circuit, thereby realizing the IO port multiplexing function of verifying the logic design by using the peripheral circuit.

According to the technical scheme, the automatic FPGA verification system is characterized in that a first FPGA chipset for loading logic design codes, a second FPGA chipset for switching IO MUX functions and a plurality of peripheral circuits are used, and the second FPGA chipset is connected with the peripheral circuits; the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing. The method and the device can realize automatic verification of the FPGA quickly, accurately and conveniently.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an automated FPGA verification system according to the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "mounted," "disposed," "provided," "connected," and "sleeved" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Considering that on a traditional FPGA verification platform, when IO MUX (input/output port multiplexing) functions of a logic design need to be verified, logic code modification is needed to be carried out when one IO MUX function is verified, so that IO of the logic design can correspond to IO of peripheral circuits of the FPGA verification platform. In this way, the following problems may occur:

1. in the verification process, the modification of the logic code destroys the originality of the logic code, and possibly omits or brings a new BUG;

2. the logic code needs to be modified once when one IO MUX function is verified, the workload is large, and the verification is long.

The application provides an embodiment of an automatic FPGA verification system, and referring to FIG. 1, in the embodiment, the automatic FPGA verification system specifically comprises a first FPGA chipset for loading a logic design code, a second FPGA chipset for switching IO MUX functions and a plurality of peripheral circuits, wherein the second FPGA chipset is connected with the peripheral circuits;

the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing.

As can be seen from the above description, according to the automatic FPGA verification system provided in the embodiment of the present application, through the first FPGA chipset for loading logic design codes, the second FPGA chipset for IO MUX function switching, and the plurality of peripheral circuits, the second FPGA chipset is connected to the peripheral circuits; the first FPGA chipset and the second FPGA chipset are connected with a chip IO port through a communication interface, the chip IO port is used for carrying out function multiplexing on functional signals of the peripheral circuit, and the communication interface is used for realizing the synchronous matching of the first FPGA chipset and the second FPGA chipset when the chip IO port is used for carrying out function multiplexing. The method and the device can realize automatic verification of the FPGA quickly, accurately and conveniently.

Referring to fig. 1, the connection between the first FPGA chipset and the second FPGA chipset includes a group of communication interfaces and an IO port of a chip, where the IO port includes function multiplexing of a function 1 signal, a function 2 signal, a function 3 signal, and a function n signal (that is, the IO may be set as a function 1, 2, 3, n signal by software setting).

As a preferred embodiment, when verifying the multiplexing function of the IO port, the first FPGA chipset sets the IO port as a first functional signal of the peripheral circuit, and simultaneously notifies the second FPGA chipset through the communication interface to synchronously switch the IO port to the first functional signal, so as to connect the IO port of the first FPGA chipset with the peripheral circuit, thereby implementing the IO port multiplexing function using the peripheral circuit verification logic design.

Similarly, through synchronous cooperation, automatic switching verification of IO port multiplexing functions 2, 3 and n of logic design can be realized.

In the verification mode, logic design codes in the first FPGA chip set do not need to be modified, manual intervention is not needed, complete automatic test verification can be realized particularly in regression testing, the verification workload is greatly reduced, and the verification time is shortened.

The above description is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. Any equivalent changes and modifications that can be made by one skilled in the art without departing from the spirit and principles of the invention should fall within the protection scope of the invention.