阅读说明：本技术 一种通用型ldo瞬态响应增强电路 (General LDO transient response enhancement circuit ) 是由 况立雪 余力澜 马小龙 董钊 韩春杰 刘跃 梁欣 于 2021-05-27 设计创作，主要内容包括：本发明公开了一种通用型LDO瞬态响应增强电路,包括快速误差电压放大、快速阈值比较、功率管控制、单次触发控制和状态更新五个模块。本发明所述电路,在LDO输出电压属于正常范围时不参与LDO环路控制,仅消耗少量静态电流,在LDO输出电压下降超过阈值时,触发瞬态响应增强机制,使得输出电压迅速恢复正常。为避免输出电压在瞬态响应增强电路的作用下来回跳变,在一段可配置的时间内,瞬态响应增强机制仅能被触发一次,瞬态响应增强电路的强度也可配置。(The invention discloses a general LDO transient response enhancement circuit which comprises five modules of rapid error voltage amplification, rapid threshold comparison, power tube control, single trigger control and state updating. The circuit does not participate in LDO loop control when the output voltage of the LDO is in a normal range, only consumes a small amount of static current, and triggers a transient response enhancement mechanism when the output voltage of the LDO drops to exceed a threshold value, so that the output voltage is quickly recovered to be normal. In order to avoid the output voltage from jumping back and forth under the action of the transient response enhancement circuit, the transient response enhancement mechanism can be triggered only once within a configurable time, and the strength of the transient response enhancement circuit can be configured.)

1. The utility model provides a general type LDO transient response reinforcing circuit, includes five modules of quick error voltage amplification, quick threshold value comparison, power tube control, single trigger control and state update, its characterized in that:

one end of the fast error voltage amplification module is connected with the output end of the LDO, and the other end of the fast error voltage amplification module is connected with the fast threshold comparison module; the rapid error voltage amplification module detects and amplifies the variable quantity of the voltage at the output end of the LDO in real time;

one end of the fast threshold comparison module is connected with the fast error voltage amplification module and receives an error voltage signal output by the fast threshold comparison module, and the other end of the fast threshold comparison module is respectively connected with the power tube control module and the single-trigger control module; the fast threshold comparison module compares the amplified error voltage with a set threshold, and inputs the comparison result into the power tube control module and the single trigger control module respectively as input signals of the power tube control module and the single trigger control module;

the power tube control module is connected to the grid end of the LDO power tube, negative change of output voltage is rapidly compensated by adjusting the grid end voltage of the LDO power tube, and the compensation intensity can be configured as required;

the single trigger module is respectively connected with the rapid threshold comparison module and the state updating module, and the rapid threshold comparison module is closed after the output voltage is adjusted back;

the state updating module updates the state of the rapid threshold comparing module in a certain period, and the updating period can be configured according to requirements.

2. The general purpose LDO transient response enhancement circuit of claim 1, wherein: the fast error voltage amplification module is composed of a P-type MOS tube MP1, a current source IB2, a P-type MOS tube MP2, a current source IB2 and a grounding capacitor C1, a voltage node of the gates of MP1 and MP2 is marked as V1 and is commonly connected to a non-grounding end of the grounding capacitor C1 and the current source IB2, the current source IB1 and the current source IB2 are respectively connected to the drains of the MP1 and the MP2, and the output end VOUT of the general LDO is respectively connected to the sources of the MP1 and the MP 2; the voltage node at the drain of MP2 is denoted as V2.

3. The universal LDO transient response enhancement circuit of claim 2, wherein: the fast threshold comparison module is composed of a P-type MOS tube MP3, a current source IB3, a P-type MOS tube MP4, an N-type MOS tube MN1, a resistor R1 and a capacitor C3; the gate of MP3 is connected to the voltage node V1 of the gates of MP1 and MP2, and the drain of MP3 is connected to the current source IB 3; MP3 and MP4 common source, the common source voltage node is denoted as VMIR; MP4 and MN1 share a gate, the voltage of the common gate is denoted as V3, and a resistor R1 is connected between voltage nodes VMIR and V3; the capacitor C3 is connected between the voltage nodes V2 and V3; the input end of the LDO is connected to the sources of MP3 and MP4 and the resistor R1 through the current source IB 5.

4. The general LDO transient response enhancement circuit of claim 3, wherein: the power tube control module is composed of an N-type MOS tube MN3 and a controllable current source IB4, wherein the input end of the controllable current source IB4 is connected with the source electrode of MN3, and the output end of the controllable current source IB4 is grounded; the drain of MN3 is connected to the gate of IDO power tube.

5. The general LDO transient response enhancement circuit of claim 4, wherein: the single-trigger control module is composed of an N-type MOS tube MN4, an N-type MOS tube MN2, a variable capacitor C4, an inverter INV1 and an inverter INV 2; the source of MN2 is grounded, the drain is connected to the source of MN4, the gate voltage node of MN2 is denoted as V6, which is connected to the non-grounded terminal of the variable capacitor C4, and the other terminal of the variable capacitor C4 is grounded; the output end of the inverter VIN2 is connected to the gate of MN2, the input end of the inverter VIN2 is connected to the gate of MN4, and the gate voltage of MN4 is denoted as V5; the drain electrode of MN4 is connected with the source electrodes of MP3 and MP 4; the voltage node at the input of inverter VN1, designated V4, is connected to the gate of MN3 and the drains of MN1 and MP4, respectively.

6. The universal LDO transient response enhancement circuit of claim 5, wherein: the state updating module is composed of a variable capacitor C2, one end of the variable capacitor C2 is grounded, the other end of the variable capacitor C2 is connected with the source electrodes of the MP3 and the MP4, and the other end of the variable capacitor C2 is connected with the drain electrode of the N-type MOS transistor MN 4.

7. The universal LDO transient response enhancement circuit of claim 6, wherein: the P-type MOS transistors MP1 and MP3 and the current sources IB1 and IB3 are respectively in a 1:1 mirror image relationship, and for different LDO circuits, the transient response enhanced intensity can be obtained by adjusting the controllable current value I of the controllable current source IB4_PULLTo be configured.

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a general LDO transient response enhancement circuit.

Background

Along with the development of integrated circuits, the complexity of SoC chips is increased, and higher requirements are put forward on power management circuits, such as providing a plurality of different output voltage values for the chips, and requiring noise isolation between different output voltages. A low dropout linear regulator (LDO) is an important component of a power management circuit, and a chip often needs to include a plurality of LDO circuits.

The power tube of the LDO is usually controlled by a loop with limited bandwidth, and the response to the high-frequency fluctuation of the load current is too slow, resulting in transient jitter of the output voltage of the LDO. An output end is connected with an off-chip filter capacitor with a uF magnitude, which is an effective method for filtering high-frequency transient jitter of output voltage. However, due to SoC chip pins and cost considerations, fully integrated LDOs are often used. The on-chip capacitor of the fully integrated LDO output end is only in the order of 100pF, and the off-chip filter capacitor cannot be utilized to provide good transient response performance.

A conventional LDO transient response enhancement circuit without off-chip capacitance is shown in fig. 1. The capacitor Cf is used as a differentiator for sensing the variation trend of the output voltage of the LDO. One end of Cf is connected with the output voltage of LDO, and the other end is connected with the current amplifier. When the output voltage jumps, the voltage across Cf cannot jump suddenly, so that a feedforward current if is generated. After the feedforward current is amplified by the current amplifier, the gate end voltage of the power tube Mp is compensated, so that the output voltage of the LDO is changed. The LDO transient response enhancement circuit introduces a new fast control loop in a basic LDO circuit, and even a small output voltage change can cause the loop state to change. On one hand, the stability of the LDO is deteriorated due to the newly added zero point, and the design difficulty is increased; on the other hand, when the technology is applied to different existing LDO circuits, circuit parameters of the transient enhanced LDO need to be redesigned according to the load current and the configuration condition of zero pole, and the portability is poor.

Object of the Invention

The invention aims to solve the problems in the prior art and provides a general LDO transient response enhancement circuit, so that the jitter amplitude of output voltage of an LDO is reduced and the response time is shortened under the high-speed forward jump of load current. By providing the general LDO transient response enhancement circuit, when the output voltage of the LDO is in a normal range, the general LDO transient response enhancement circuit does not participate in the control of an LDO loop, only consumes a small amount of static current, and when the output voltage of the LDO drops and exceeds a threshold value, a transient response enhancement mechanism is triggered, so that the output voltage is rapidly recovered to be normal. In order to avoid the output voltage from jumping back and forth under the action of the transient response enhancement circuit, the transient response enhancement mechanism can be triggered only once within a configurable time, and the strength of the transient response enhancement circuit can be configured.

Disclosure of Invention

The invention provides a general LDO transient response enhancement circuit, which comprises five modules of rapid error voltage amplification, rapid threshold comparison, power tube control, single trigger control and state update, wherein:

one end of the fast error voltage amplification module is connected with the output end of the LDO, and the other end of the fast error voltage amplification module is connected with the fast threshold comparison module; the rapid error voltage amplification module detects and amplifies the variable quantity of the voltage at the output end of the LDO in real time;

one end of the fast threshold comparison module is connected with the fast error voltage amplification module and receives an error voltage signal output by the fast threshold comparison module, and the other end of the fast threshold comparison module is respectively connected with the power tube control module and the single-trigger control module; the fast threshold comparison module compares the amplified error voltage with a set threshold, and inputs the comparison result into the power tube control module and the single trigger control module respectively as input signals of the power tube control module and the single trigger control module;

the power tube control module is connected to the grid end of the LDO power tube, negative change of output voltage is rapidly compensated by adjusting the grid end voltage of the LDO power tube, and the compensation intensity can be configured as required;

the single trigger module is respectively connected with the rapid threshold comparison module and the state updating module, and the rapid threshold comparison module is closed after the output voltage is adjusted back;

the state updating module updates the state of the rapid threshold comparing module in a certain period, and the updating period can be configured according to requirements.

Preferably, the fast error voltage amplifying module is composed of a P-type MOS transistor MP1, a current source IB2, a P-type MOS transistor MP2, a current source IB2, and a grounded capacitor C1, a voltage node of the gates of MP1 and MP2 is denoted as V1, the voltage node is commonly connected to a non-grounded terminal of the grounded capacitor C1 and the current source IB2, the current source IB1 and the current source IB2 are respectively connected to the drains of MP1 and MP2, and an output terminal VOUT of the general LDO is respectively connected to the sources of MP1 and MP 2; the voltage node at the drain of MP2 is denoted as V2.

Preferably, the fast threshold comparison module is composed of a P-type MOS transistor MP3, a current source IB3, a P-type MOS transistor MP4, an N-type MOS transistor MN1, a resistor R1, and a capacitor C3; the gate of MP3 is connected to the voltage node V1 of the gates of MP1 and MP2, and the drain of MP3 is connected to the current source IB 3; MP3 and MP4 common source, the common source voltage node is denoted as VMIR; MP4 and MN1 share a gate, the voltage of the common gate is denoted as V3, and a resistor R1 is connected between voltage nodes VMIR and V3; the capacitor C3 is connected between the voltage nodes V2 and V3; the input end of the LDO is connected to the sources of MP3 and MP4 and the resistor R1 through the current source IB 5.

Preferably, the power tube control module is composed of an N-type MOS tube MN3 and a controllable current source IB4, wherein an input end of the controllable current source IB4 is connected with a source electrode of MN3, and an output end of the controllable current source IB4 is grounded; the drain electrode of MN3 is connected to the gate end of the IDO power tube;

preferably, the single-trigger control module is composed of an N-type MOS transistor MN4, an N-type MOS transistor MN2, a variable capacitor C4, an inverter INV1, and an inverter INV 2; the source of MN2 is grounded, the drain is connected to the source of MN4, the gate voltage node of MN2 is denoted as V6, which is connected to the non-grounded terminal of the variable capacitor C4, and the other terminal of the variable capacitor C4 is grounded; the output end of the inverter VIN2 is connected to the gate of MN2, the input end of the inverter VIN2 is connected to the gate of MN4, and the gate voltage of MN4 is denoted as V5; the drain electrode of MN4 is connected with the source electrodes of MP3 and MP 4; the voltage node at the input of inverter VN1, designated V4, is connected to the gate of MN3 and the drains of MN1 and MP4, respectively.

Preferably, the state updating module is composed of a variable capacitor C2, one end of the variable capacitor C2 is grounded, and the other end is connected with the sources of MP3 and MP4 and the drain of the N-type MOS transistor MN 4.

More preferably, the P-type MOS transistors MP1 and MP3 and the current sources IB1 and IB3 are 1:1 mirror images, respectively, and the transient response enhancement strength can be obtained by adjusting the controllable current value I of the controllable current source IB4 for different LDO circuits_PULLTo be configured.

Drawings

FIG. 1 is a prior art LDO transient response enhancement circuit without an off-chip capacitor.

FIG. 2 is a block diagram of a general LDO transient response enhancement circuit according to the present invention.

FIG. 3 shows an embodiment of a general LDO transient response enhancement circuit according to the present invention.

Detailed Description

The present invention is described in detail below with reference to the attached drawings.

FIG. 2 is a block diagram of a general LDO transient response enhancement circuit according to the present invention. As shown in the figure, the general LDO transient response enhancement circuit comprises five modules of rapid error voltage amplification, rapid threshold comparison, power tube control, single-trigger control and state updating.

One end of the rapid error voltage amplification module is connected with the output end of the LDO, and the other end of the rapid error voltage amplification module is connected with the rapid threshold comparison module, so that the variable quantity of the voltage at the output end of the LDO is detected and amplified in real time;

one end of the fast threshold comparison module is connected with the fast error voltage amplification module and receives the output error voltage signal, and the other end of the fast threshold comparison module is respectively connected with the power tube control module and the single trigger control module. And the fast threshold comparison module compares the amplified error voltage with a set threshold, and inputs the comparison result into the power tube control module and the single-trigger control module respectively as input signals of the power tube control module and the single-trigger control module.

The power tube control module is connected to the grid end of the LDO power tube, negative change of output voltage is rapidly compensated by adjusting the grid end voltage of the LDO power tube, and the compensation intensity can be configured as required;

the single trigger module is respectively connected with the rapid threshold comparison module and the state updating module, and the rapid threshold comparison module is closed after the output voltage is adjusted back;

the state updating module updates the state of the rapid threshold comparing module in a certain period, and the updating period can be configured according to requirements.

The circuit according to the invention is described in detail below by way of an exemplary embodiment.

Examples

FIG. 3 shows an embodiment of a general LDO transient response enhancement circuit according to the present invention. As shown in the figure:

the fast error voltage amplification module is composed of a P-type MOS tube MP1, a current source IB2, a P-type MOS tube MP2, a current source IB2 and a grounding capacitor C1, a voltage node of the gates of MP1 and MP2 is marked as V1, the voltage node is connected to a non-grounding end of the grounding capacitor C1 and the current source IB2 in common, the current source IB1 and the current source IB2 are respectively connected to the drains of the MP1 and the MP2, and the output end VOUT of the general LDO is respectively connected to the sources of the MP1 and the MP 2; the voltage node at the drain of MP2 is denoted as V2.

The fast threshold comparison module is composed of a P-type MOS tube MP3, a current source IB3, a P-type MOS tube MP4, an N-type MOS tube MN1, a resistor R1 and a capacitor C3; the gate of MP3 is connected to the voltage node V1 of the gates of MP1 and MP2, and the drain of MP3 is connected to the current source IB 3; MP3 and MP4 common source, the common source voltage node is denoted as VMIR; MP4 and MN1 share a gate, the voltage of the common gate is denoted as V3, and a resistor R1 is connected between voltage nodes VMIR and V3; the capacitor C3 is connected between the voltage nodes V2 and V3; the input end of the LDO is connected to the sources of MP3 and MP4 and the resistor R1 through the current source IB 5.

The power tube control module is composed of an N-type MOS tube MN3 and a controllable current source IB4, wherein the input end of the controllable current source IB4 is connected with the source electrode of the MN3, the output end of the controllable current source IB4 is grounded, and the controllable current value of the controllable current source IB4 is marked as I_PULL(ii) a The drain of MN3 is connected to the gate of IDO power tube.

The single-trigger control module is composed of an N-type MOS transistor MN4, an N-type MOS transistor MN2, a variable capacitor C4, an inverter INV1 and an inverter INV 2; the source of MN2 is grounded, the drain is connected to the source of MN4, the gate voltage node of MN2 is denoted as V6, which is connected to the non-grounded terminal of the variable capacitor C4, and the other terminal of the variable capacitor C4 is grounded; the output end of the inverter VIN2 is connected to the gate of MN2, the input end of the inverter VIN2 is connected to the gate of MN4, and the gate voltage of MN4 is denoted as V5; the drain electrode of MN4 is connected with the source electrodes of MP3 and MP 4; the voltage node at the input of inverter VN1, designated V4, is connected to the gate of MN3 and the drains of MN1 and MP4, respectively.

The state updating module is composed of a variable capacitor C2, one end of C2 is grounded, the other end is connected with the sources of MP3 and MP4, and is connected with the drain of an N-type MOS transistor MN 4.

Wherein MP1, MP3, IB1 and IB3 are 1:1 mirror image relationship, and the transient response enhanced intensity can be obtained by adjusting the current value I of the controllable current source IB4 for different LDO circuits_PULLTo be configured.

The working principle of the circuit control process of the invention is as follows:

s1: when the output end VOUT of the LDO has a rapid negative change, the change of the V1 node is slow due to the charge holding effect of the capacitor C1, and the MP2 and the current source IB2 form a common-gate amplifier to amplify the VOUT error voltage to the V2 node.

S2: MP1, MP3, IB1 and IB3 are in a 1:1 mirror relationship, so that the VMIR node maintains the direct current information of VOUT; the capacitor C3 and the resistor R1 form an alternating current coupling circuit, an alternating current signal of a V2 node is transmitted to a V3 node, the static level of the V3 node is VMIR, and therefore the inverter formed by the MP4 and the MN1 has no static current; when the fast negative change of VOUT occurs, the fast negative change also occurs on V3, and when the negative change of V3 exceeds the threshold of the inverter consisting of MP4 and MN1, the V4 node is flipped from low to high.

S3: after the V4 node is turned to high VMIR, MN3 is turned on at the current value I set by IB4_PULLThe current is extracted from the grid end of the LDO power tube, so that the output current of the power tube is increased, the output voltage is adjusted back, and for different LDO circuits, the transient response enhanced intensity can be adjusted by adjusting the current value I_PULLTo be configured.

S4: after the output voltage is adjusted back, the voltages of the nodes V2 and V3 rise, V4 becomes low level, V5 becomes high level, and MN4 is turned on; at this time, V6 remains at high level under the action of C4, MN2 and MN4 both turn on, pulling the VMIR node down to low level, thereby turning off the fast threshold comparison module and avoiding the LDO output voltage from flipping back and forth.

S5: v5 is high, inverter INV2 discharges capacitor C4, after a discharge time, V6 goes low, MN2 is turned off, and the pull-down of VMIR node is finished. IB5 and adjustable capacitor C2 constitute a state update module, which charges the VMIR node again until the VMIR returns to the mirror image of VOUT DC level, ready for the next transient response enhancement triggering event

The invention has the following advantages:

the transient response enhancement circuit of the present invention has a trigger threshold and does not respond to minute jitter such as noise of an output voltage. Under the static condition, the method does not participate in the loop control of the original LDO circuit, has no stability problem, and greatly reduces the design complexity of the transient enhancement type LDO.

The transient response enhancement circuit can be configured in the working intensity and the allowed period, and can be adapted to LDOs with different load current capacities and different pole-zero configurations.

It will be understood by those skilled in the art that the foregoing detailed description is merely exemplary of the preferred embodiments of the invention, and that modifications and substitutions can be made without departing from the spirit of the invention.