阅读说明：本技术 一种无片外电容型ldo瞬态响应增强电路 (No off-chip capacitance type LDO transient response reinforcing circuit ) 是由 沈洁 王倩 李喜 陈后鹏 宋志棠 于 2021-08-10 设计创作，主要内容包括：本发明涉及一种无片外电容型LDO瞬态响应增强电路,包括：OTA电路,包括第一支路和第二支路,所述第一支路和第二支路在产生上冲电压和下冲电压时会产生电流跳变；下冲检测电压支路,分别与所述第一支路和第二支路相连,用于根据所述第一支路和第二支路产生的电流跳变控制泄放支路；所述泄放支路用于为功率管提供栅极到地的放电通路；上冲检测电压支路,分别与所述第一支路和第二支路相连,用于根据所述第一支路和第二支路产生的电流跳变控制充电支路；所述充电支路用于为所述功率管提供电源到栅极的充电通路。本发明能显著提高LDO瞬态响应。(The invention relates to a transient response enhancement circuit of LDO without off-chip capacitance, comprising: the OTA circuit comprises a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit can generate current jump when generating an overshoot voltage and an undershoot voltage; the undershoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the bleeder branch circuit according to current jumps generated by the first branch circuit and the second branch circuit; the bleeder branch is used for providing a discharge path from a grid electrode to the ground for the power tube; the overshoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the charging branch circuit according to current jump generated by the first branch circuit and the second branch circuit; the charging branch circuit is used for providing a charging path from a power supply to the grid electrode for the power tube. The invention can obviously improve the transient response of the LDO.)

1. An LDO transient response enhancement circuit without an off-chip capacitor, comprising:

the OTA circuit comprises a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit can generate current jump when generating an overshoot voltage and an undershoot voltage;

the undershoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the bleeder branch circuit according to current jumps generated by the first branch circuit and the second branch circuit; the bleeder branch is used for providing a discharge path from a grid electrode to the ground for the power tube;

the overshoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the charging branch circuit according to current jump generated by the first branch circuit and the second branch circuit; the charging branch circuit is used for providing a charging path from a power supply to the grid electrode for the power tube.

2. The LDO transient response enhancement circuit without external capacitance of claim 1, characterized in that the OTA circuit comprises a first transistor (M0), a second transistor (M1), a third transistor (M2), a fourth transistor (M3), a fifth transistor (M4), a sixth transistor (M5), a seventh transistor (M6), an eighth transistor (M7) and a ninth transistor (M8); the grid electrode of the first transistor (M0) is connected with a bias voltage end, the source electrode of the first transistor is connected with a power supply end, and the drain electrode of the first transistor is respectively connected with the source electrode of the second transistor (M1) and the source electrode of the third transistor (M2); the gate of the second transistor (M1) is connected to a reference voltage terminal, and the drain is connected to the drain of the fifth transistor (M4); the grid electrode of the third transistor (M2) is grounded through a second resistor R2, and the drain electrode of the third transistor (M2) is connected with the drain electrode of the fourth transistor (M3); the gate of the fourth transistor (M3) is connected with the gate of the ninth transistor (M8), the source is grounded, and the drain is also connected with the gate of the fourth transistor; the grid electrode of the fifth transistor (M4) is connected with the grid electrode of the sixth transistor (M5), the source electrode is grounded, and the drain electrode is also connected with the grid electrode of the fifth transistor; the source electrode of the sixth transistor (M5) is grounded, and the drain electrode of the sixth transistor (M5) is connected with the drain electrode of the seventh transistor (M6); the grid electrode of the seventh transistor (M6) is connected with the grid electrode of the eighth transistor (M7), the source electrode is connected with a power supply end, and the drain electrode is also connected with the grid electrode of the seventh transistor; the source electrode of the eighth transistor (M7) is connected with a power supply end, and the drain electrode of the eighth transistor (M7) is respectively connected with the drain electrode of the ninth transistor (M8) and the grid electrode of the power tube; a source of the ninth transistor (M8) is grounded; the source electrode of the power tube is connected with a power supply end, and the drain electrode of the power tube is grounded through a first resistor R1 and the second resistor R2 in sequence; the fifth transistor (M4) and the sixth transistor (M5) form the first branch, and the gates of the fifth transistor (M4) and the sixth transistor (M5) are used as the output end of the first branch; the fourth transistor (M3) and the ninth transistor (M8) form the second branch, and the gates of the fourth transistor (M3) and the ninth transistor (M8) are used as the output end of the second branch.

3. The LDO transient response enhancement circuit without external capacitance according to claim 1, characterized in that the undershoot detection voltage branch comprises tenth (Ma1), eleventh (Ma2), twelfth (Ma3) and fourteenth (Ma4) transistors; the gate of the tenth transistor (Ma1) is connected with the gate of the eleventh transistor (Ma2), the source is connected with a power supply end, and the drain is connected with the drain of the twelfth transistor (Ma 3); the source electrode of the eleventh transistor (Ma2) is connected with a power supply end, and the drain electrode of the eleventh transistor (Ma2) is respectively connected with the grid electrode of the eleventh transistor and the drain electrode of the fourteenth transistor (Ma 4); the grid electrode of the twelfth transistor (Ma3) is connected with the output end of the first branch, the source electrode of the twelfth transistor is grounded, the drain electrode of the twelfth transistor (Ma3) is connected with the bleeder branch, and the drain electrode of the twelfth transistor (Ma3) is also grounded through a third resistor (Ra 1); the gate of the fourteenth transistor (Ma4) is connected to the output terminal of the second branch, and the source is grounded.

4. The LDO transient response enhancement circuit without external capacitance according to claim 1, characterized in that the overshoot detection voltage branch comprises a fifteenth transistor (Mb1), a sixteenth transistor (Mb2), a seventeenth transistor (Mb3) and an eighteenth transistor (Mb 4); the gate of the fifteenth transistor (Mb1) is connected to the gate of the sixteenth transistor (Mb2), the source is connected to a power supply terminal, and the drain is connected to the drain of the seventeenth transistor (Mb3) and the charging branch respectively; the drain of the fifteenth transistor (Mb1) is also connected with a power supply end through a fourth resistor (Rb 1); the source electrode of the sixteenth transistor (Mb2) is connected with a power supply end, and the drain electrode of the sixteenth transistor (Mb2) is respectively connected with the drain electrode of the eighteenth transistor (Mb4) and the grid electrode of the sixteenth transistor; the gate of the seventeenth transistor (Mb3) is connected to the output terminal of the first branch, and the source is grounded; the gate of the eighteenth transistor (Mb4) is connected to the output of the second branch, and the source is connected to ground.

5. The LDO transient response enhancement circuit without external capacitor according to claim 1, wherein the bleeding branch comprises an N-type bleeding transistor (Ms2), the gate of the N-type bleeding transistor (Ms2) is connected to the undershoot detection voltage branch, and the drain and source are used to provide a bleeding path of the power tube to ground.

6. The LDO transient response enhancement circuit without external capacitor according to claim 1, wherein the charging branch comprises a P-type charging transistor (Ms1), the gate of the P-type charging transistor (Ms1) is connected to the overshoot detection voltage branch, and the source and drain are used to provide a charging path for the power source terminal to the power transistor.

Technical Field

The invention relates to the technical field of LDO transient response enhancement, in particular to an LDO transient response enhancement circuit without an off-chip capacitor.

Background

The low dropout regulator (LDO) is one of power management chip technologies, has a simple structure, has low output noise and ripple, and is suitable for a system sensitive to noise. In addition, the LDO has a small size and is easy to use, and thus is widely used in portable electronic products, and becomes one of the essential modules for power management of electronic systems.

The transient response of the LDO comprises power supply transient response and load transient response, which means that when the supply voltage or load current of the LDO jumps, the output voltage of the LDO changes; and then the LDO chip returns the output voltage to a stable value through a linear negative feedback system of the LDO chip. It has two important indicators: the overshoot voltage, which determines the maximum change in the LDO output voltage, and the recovery time, which determines the time required for the LDO output voltage to recover to a stable value.

The traditional LDO needs to be externally connected with a large capacitor at the output end, not only is a left half plane zero point compensated for a system so as to keep the system stable, but also the large external capacitor is beneficial to improving the transient response performance of the LDO, and has good inhibiting effect on the output voltage fluctuation caused by sudden change of load current.

But engineers need to choose an external capacitor with a specific equivalent series resistance range, the capacitor is in the order of microfarad, the application complexity and cost are improved, the area is occupied, and the capacitor is not suitable for large-scale integration. The capacitor-free LDO power supply is beneficial to reducing the chip area and the cost, becomes a research hotspot of the LDO at present, and is widely applied to the market. However, the LDO without an external large capacitor can only perform transient response through the power tube itself. Because the power tube is larger in size, larger grid parasitic capacitance can be generated, so that the transient response speed of the LDO is lower, no large capacitor is used for providing or storing extra output current when the load current jumps, and larger overshoot voltage is generated at the output end of the LDO, so that the transient response characteristic of the LDO without the off-chip capacitor is poorer than that of the traditional LDO.

Disclosure of Invention

The invention aims to provide an LDO transient response enhancement circuit without an off-chip capacitor, which can obviously improve the transient response of the LDO.

The technical scheme adopted by the invention for solving the technical problems is as follows: provided is an LDO transient response enhancement circuit without an off-chip capacitor, including:

the OTA circuit comprises a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit can generate current jump when generating an overshoot voltage and an undershoot voltage;

the undershoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the bleeder branch circuit according to current jumps generated by the first branch circuit and the second branch circuit; the bleeder branch is used for providing a discharge path from a grid electrode to the ground for the power tube;

the overshoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the charging branch circuit according to current jump generated by the first branch circuit and the second branch circuit; the charging branch circuit is used for providing a charging path from a power supply to the grid electrode for the power tube.

The OTA circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; the grid electrode of the first transistor is connected with a bias voltage end, the source electrode of the first transistor is connected with a power supply end, and the drain electrode of the first transistor is respectively connected with the source electrode of the second transistor and the source electrode of the third transistor; the grid electrode of the second transistor is connected with a reference voltage end, and the drain electrode of the second transistor is connected with the drain electrode of the fifth transistor; the grid electrode of the third transistor is grounded through a second resistor, and the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor; the grid electrode of the fourth transistor M3 is connected with the grid electrode of the ninth transistor, the source electrode is grounded, and the drain electrode is also connected with the grid electrode of the fourth transistor M3; the grid electrode of the fifth transistor is connected with the grid electrode of the sixth transistor, the source electrode of the fifth transistor is grounded, and the drain electrode of the fifth transistor is also connected with the grid electrode of the fifth transistor; the source electrode of the sixth transistor is grounded, and the drain electrode of the sixth transistor is connected with the drain electrode of the seventh transistor; the grid electrode of the seventh transistor is connected with the grid electrode of the eighth transistor, the source electrode of the seventh transistor is connected with a power supply end, and the drain electrode of the seventh transistor is also connected with the grid electrode of the seventh transistor; the source electrode of the eighth transistor is connected with a power supply end, and the drain electrode of the eighth transistor is respectively connected with the drain electrode of the ninth transistor and the grid electrode of the power tube; a source of the ninth transistor is grounded; the source electrode of the power tube is connected with a power supply end, and the drain electrode is grounded through the first resistor and the second resistor in sequence; the fifth transistor and the sixth transistor form the first branch circuit, and the grid electrodes of the fifth transistor and the sixth transistor are used as the output end of the first branch circuit; the fourth transistor and the ninth transistor form the second branch circuit, and the gates of the fourth transistor and the ninth transistor are used as the output end of the second branch circuit.

The undershoot detection voltage branch circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor and a fourteenth transistor; a gate of the tenth transistor is connected to a gate of the eleventh transistor, a source of the tenth transistor is connected to a power source, and a drain of the tenth transistor is connected to a drain of the twelfth transistor; a source electrode of the eleventh transistor is connected with a power supply end, and a drain electrode of the eleventh transistor is respectively connected with a grid electrode of the eleventh transistor and a drain electrode of the fourteenth transistor; the grid electrode of the twelfth transistor is connected with the output end of the first branch circuit, the source electrode of the twelfth transistor is grounded, the drain electrode of the twelfth transistor is connected with the discharge branch circuit, and the drain electrode of the twelfth transistor is grounded through a third resistor; and the grid electrode of the fourteenth transistor is connected with the output end of the second branch circuit, and the source electrode of the fourteenth transistor is grounded.

The overshoot detection voltage branch circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; the gate of the fifteenth transistor is connected with the gate of the sixteenth transistor, the source of the fifteenth transistor is connected with a power supply end, and the drain of the fifteenth transistor is respectively connected with the drain of the seventeenth transistor and the charging branch circuit; the drain electrode of the fifteenth transistor is also connected with a power supply end through a fourth resistor; the source electrode of the sixteenth transistor is connected with a power supply end, and the drain electrode of the sixteenth transistor is respectively connected with the drain electrode of the eighteenth transistor and the grid electrode of the sixteenth transistor; the grid electrode of the seventeenth transistor is connected with the output end of the first branch circuit, and the source electrode of the seventeenth transistor is grounded; and the grid electrode of the eighteenth transistor is connected with the output end of the second branch circuit, and the source electrode of the eighteenth transistor is grounded.

The drain and the source of the N-type bleeder transistor are used for providing a bleeder path from the power tube to the ground.

The charging branch comprises a P-type charging transistor, the grid of the P-type charging transistor is connected with the overshoot detection voltage branch, and the source electrode and the drain electrode are used for providing a charging path from the power supply end to the power tube.

Advantageous effects

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: according to the invention, the current fluctuation of the OTA is converted into voltage fluctuation by adding the upper punch voltage detection branch and the lower punch voltage detection branch; a charging path from a power supply to a grid electrode and a discharging path from the grid electrode to the ground are provided for the power tube through the arrangement of the discharging branch and the charging branch. When the output changes from light load to heavy load, undershoot voltage is generated, large transient current flows through a resistor in the undershoot voltage detection branch circuit, so that the discharge branch circuit is opened, the grid voltage of the power tube is pulled down, and the undershoot is weakened; when the output changes from heavy load to light load, an overshoot voltage is generated, and a large transient current flows through a resistor in the overshoot voltage detection branch circuit, so that the charging branch circuit is opened, the grid voltage of the power tube is pulled high, and the overshoot is weakened. The invention can obviously improve the transient response of the LDO.

Drawings

FIG. 1 is a circuit block diagram of an embodiment of the invention;

FIG. 2 is a simulation diagram of undershoot optimization in an embodiment of the present invention;

fig. 3 is a simulation diagram of the overshoot optimization in the embodiment of the present invention.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The embodiment of the invention relates to an LDO transient response enhancement circuit without an off-chip capacitor, which comprises: the OTA circuit comprises a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit can generate current jump when generating an overshoot voltage and an undershoot voltage; the undershoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the bleeder branch circuit according to current jumps generated by the first branch circuit and the second branch circuit; the bleeder branch is used for providing a discharge path from a grid electrode to the ground for the power tube; the overshoot detection voltage branch circuit is respectively connected with the first branch circuit and the second branch circuit and is used for controlling the charging branch circuit according to current jump generated by the first branch circuit and the second branch circuit; the charging branch circuit is used for providing a charging path from a power supply to the grid electrode for the power tube.

As shown in fig. 1, the circuit includes: the circuit comprises an OTA circuit consisting of transistors M0-M8, a power tube Mp, a feedback resistor R1, a feedback resistor R2, a variable load current ILOAD, and an undershoot detection voltage branch consisting of transistors Ma1-Ma4 and a resistor Ra 1; an overshoot detection voltage branch composed of transistors Mb1-Mb4 and a resistor Rb 1; a charging branch Ms1 and a bleeding branch Ms 2.

The OTA circuit includes a first transistor M0, a second transistor M1, a third transistor M2, a fourth transistor M3, a fifth transistor M4, a sixth transistor M5, a seventh transistor M6, an eighth transistor M7, and a ninth transistor M8; the gate of the first transistor M0 is connected to a bias voltage terminal, the source is connected to a power supply terminal, and the drain is connected to the source of the second transistor M1 and the source of the third transistor M2, respectively; the grid electrode of the second transistor M1 is connected with a reference voltage end, and the drain electrode of the second transistor M1 is connected with the drain electrode of the fifth transistor M4; the grid electrode of the third transistor M2 is grounded through a second resistor R2, and the drain electrode of the third transistor M2 is connected with the drain electrode of the fourth transistor M3; the grid electrode of the fourth transistor M3 is connected with the grid electrode of the ninth transistor M8, the source electrode is grounded, and the drain electrode is also connected with the grid electrode of the fourth transistor M3; the grid electrode of the fifth transistor M4 is connected with the grid electrode of the sixth transistor M5, the source electrode is grounded, and the drain electrode is also connected with the grid electrode of the fifth transistor M4; the source electrode of the sixth transistor M5 is grounded, and the drain electrode is connected with the drain electrode of the seventh transistor M6; the grid electrode of the seventh transistor M6 is connected with the grid electrode of the eighth transistor M7, the source electrode is connected with a power supply end, and the drain electrode is also connected with the grid electrode of the seventh transistor M6; the source of the eighth transistor M7 is connected to a power supply terminal, and the drain is connected to the drain of the ninth transistor M8 and the gate of the power transistor, respectively; the source of the ninth transistor M8 is grounded; the source electrode of the power tube is connected with a power supply end, and the drain electrode of the power tube is grounded through a first resistor R1 and the second resistor R2 in sequence; the fifth transistor M4 and the sixth transistor M5 form the first branch, and the gates of the fifth transistor M4 and the sixth transistor M5 are used as the output end of the first branch; the fourth transistor M3 and the ninth transistor M8 form the second branch, and the gates of the fourth transistor M3 and the ninth transistor M8 are used as the output terminal of the second branch.

The undershoot detection voltage branch includes a tenth transistor Ma1, an eleventh transistor Ma2, a twelfth transistor Ma3, and a fourteenth transistor Ma 4; the gate of the tenth transistor Ma1 is connected to the gate of the eleventh transistor Ma2, the source thereof is connected to a power source terminal, and the drain thereof is connected to the drain of the twelfth transistor Ma 3; a source of the eleventh transistor Ma2 is connected to a power source, and a drain thereof is connected to a gate thereof and a drain of the fourteenth transistor Ma4, respectively; the gate of the twelfth transistor Ma3 is connected to the output end of the first branch, the source is grounded, the drain is connected to the bleeding branch, and the drain of the twelfth transistor Ma3 is also grounded through a third resistor Ra 1; the gate of the fourteenth transistor Ma4 is connected to the output terminal of the second branch, and the source is grounded.

The overshoot detection voltage branch includes a fifteenth transistor Mb1, a sixteenth transistor Mb2, a seventeenth transistor Mb3, and an eighteenth transistor Mb 4; the gate of the fifteenth transistor Mb1 is connected to the gate of the sixteenth transistor Mb2, the source thereof is connected to a power supply terminal, and the drain thereof is connected to the drain of the seventeenth transistor Mb3 and the charging branch, respectively; the drain of the fifteenth transistor Mb1 is also connected to a power supply terminal through a fourth resistor Rb 1; the source of the sixteenth transistor Mb2 is connected to a power supply terminal, and the drain of the sixteenth transistor Mb2 is connected to the drain of the eighteenth transistor Mb4 and the gate of the sixteenth transistor Mb 3578 respectively; the gate of the seventeenth transistor Mb3 is connected to the output terminal of the first branch, and the source is grounded; the gate of the eighteenth transistor Mb4 is connected to the output of the second branch, and the source is grounded.

The bleeder branch comprises an N-type bleeder transistor Ms2, the gate of the N-type bleeder transistor Ms2 is connected to the undershoot detection voltage branch, and the drain and the source are used for providing a bleeder path for the power tube to ground.

The charging branch comprises a P-type charging transistor Ms1, the grid electrode of the P-type charging transistor Ms1 is connected with the overshoot detection voltage branch, and the source electrode and the drain electrode are used for providing a charging path from the power supply end to the power tube.

When the output current jumps from 0 to 100mA, the gate potential of the power tube Mp is not in time to respond, so that large current is provided for the load, the output voltage is pulled down, and an undershoot voltage is generated. The operational amplifier is influenced through the feedback branch circuit, so that the branch circuit current jumps: the branch current of the sixth transistor M5 decreases and is mirrored to the twelfth transistor Ma3, so that the drain current of the twelfth transistor Ma3 decreases; the ninth transistor M8 branches the current increase, mirroring to the thirteenth transistor Ma4, so that the drain current of the thirteenth transistor Ma4 increases, causing the drain current of the tenth transistor Ma1 to increase through the current mirror circuit constituted by the tenth transistor Ma1 and the eleventh transistor Ma 2. Therefore, the branch currents of the tenth transistor Ma1 and the twelfth transistor Ma3 flow through the third resistor Ra1 to generate an upward jump voltage, the bleeding branch is turned on, the gate voltage of the power tube Mp drops to provide a large current for the load, and the output voltage returns to a normal level.

When the output current jumps from 100mA to 0, the output voltage is pulled high because the grid potential of the power tube Mp does not respond in time, and an overshoot voltage is generated. The operational amplifier is influenced through the feedback branch circuit, so that the branch circuit current jumps: the sixth transistor M5 branches and increases the current, mirroring to the seventeenth transistor Mb3, so that the seventeenth transistor Mb3 drain current increases; the ninth transistor M8 branches and reduces the current, and mirrors to the eighteenth transistor Mb4, so that the drain current of the eighteenth transistor Mb4 is reduced, and the drain current of the fifteenth transistor Mb1 is reduced through the current mirror circuit formed by the fifteenth transistor Mb1 and the sixteenth transistor Mb 2. Therefore, the current of the branches of the fifteenth transistor Mb1 and the seventeenth transistor Mb3 flows through the fourth resistor Rb1, a downward jump voltage is generated, the charging branch is turned on, the voltage of the gate of the power tube Mp rises, and the output voltage falls back to a normal level.

The circuit of the present embodiment was simulated at 27 ℃ with an input voltage of 3V, and the simulation results are shown in fig. 2 and 3, and 2.4V when the output voltage was stable. When the load current 0 becomes 100mA, the maximum voltage drops by 0.988V without adding the transient enhancement circuit, and the stabilization time is 4 mus; the maximum drop is 0.12V and the stabilization time is 2 mus when the transient enhancement circuit is added. When the load current 100mA becomes 0, the overshoot 0.58V is output when the transient enhancement circuit is not added, and the stable time is 2.67 mu s; when the transient enhancement circuit is added, the output is upswept by 0.13V, and the stable time is 2.67 mu s. Therefore, the invention can obviously improve the transient response of the LDO.