阅读说明：本技术 一种时钟补偿方法及装置 (Clock compensation method and device ) 是由 许良掌 于 2021-05-28 设计创作，主要内容包括：本申请涉及时钟同步技术领域,特别涉及一种时钟补偿方法及装置。该方法应用于网络设备的主控板,所述主控板包括主时钟芯片,所述方法包括：获取所述主时钟芯片的时间点T,并获取所述主时钟芯片的输出管脚至所述网络设备的输出接口之间的传输时延TX-DELAY；将所述主时钟芯片的时间点T和所述传输时延TX-DELAY之和,确定为所述主时钟芯片传输至所述网络设备的输出接口的时间点T1；将所述时间点T1通过所述网络设备的输出接口传输至其他网络设备,以使得所述其他网络设备基于所述时间点T1进行时钟同步。(The present disclosure relates to clock synchronization technologies, and in particular, to a clock compensation method and apparatus. The method is applied to a main control board of network equipment, wherein the main control board comprises a main clock chip, and the method comprises the following steps: acquiring a time point T of the main clock chip, and acquiring a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network equipment; determining the sum of the time point T of the master clock chip and the transmission DELAY TX _ DELAY as the time point T1 of the master clock chip transmitted to the output interface of the network device; transmitting the time point T1 to other network devices through an output interface of the network device to enable the other network devices to perform clock synchronization based on the time point T1.)

1. A clock compensation method is applied to a master control board of a network device, wherein the master control board comprises a master clock chip, and the method comprises the following steps:

acquiring a time point T of the main clock chip, and acquiring a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network equipment;

determining the sum of the time point T of the master clock chip and the transmission DELAY TX _ DELAY as the time point T1 of the master clock chip transmitted to the output interface of the network device;

transmitting the time point T1 to other network devices through an output interface of the network device to enable the other network devices to perform clock synchronization based on the time point T1.

2. The method of claim 1, wherein if the network device does not have a time source input; the step of obtaining the time point T of the master clock chip includes:

determining local system time as a time point T of the master clock chip;

if the network device has a time source input, the step of obtaining the time point T of the master clock chip comprises the following steps:

acquiring a time point T' of the time source, and determining a transmission time DELAY RX _ DELAY from an input interface of the network equipment to an input pin of the master clock chip;

and determining the sum of the time point T' of the time source and the transmission time DELAY RX _ DELAY as the time point T of the master clock chip.

3. The method of claim 1 or 2, wherein the network device further comprises a line card, the method further comprising:

determining the transmission time DELAY INNER _ DELAY from the output pin of the main clock chip to the input pin of the clock chip of the line card;

the line card is clock-synchronized based on the time point T1 and the transmission DELAY INNER _ DELAY.

4. The method of claim 3, wherein the step of clock-synchronizing the line card based on the time point T1 and the propagation DELAY INNER _ DELAY comprises:

calculating the difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

5. The method of claim 4, wherein the method further comprises:

if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, wherein T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

6. A clock compensation apparatus, applied to a master control board of a network device, the master control board including a master clock chip, the apparatus comprising:

the acquisition unit is used for acquiring a time point T of the master clock chip and acquiring transmission DELAY TX _ DELAY between an output pin of the master clock chip and an output interface of the network equipment;

a determining unit, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY TX _ DELAY as a time point T1 of the master clock chip being transmitted to an output interface of the network device;

a transmission unit, configured to transmit the time point T1 to another network device through an output interface of the network device, so that the other network device performs clock synchronization based on the time point T1.

7. The apparatus of claim 6, wherein if the network device does not have a time source input; when the time point T of the master clock chip is obtained, the obtaining unit is specifically configured to:

determining local system time as a time point T of the master clock chip;

if the network device has a time source input, and the time point T of the master clock chip is obtained, the obtaining unit is specifically configured to:

acquiring a time point T' of the time source, and determining a transmission time DELAY RX _ DELAY from an input interface of the network equipment to an input pin of the master clock chip;

and determining the sum of the time point T' of the time source and the transmission time DELAY RX _ DELAY as the time point T of the master clock chip.

8. The apparatus of claim 6 or 7, wherein the network device further comprises a line card, the apparatus further comprising a synchronization unit:

the acquisition unit is further configured to acquire a transmission DELAY INNER _ DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line card;

the synchronization unit is configured to perform clock synchronization on the line card based on the time point T1 and the propagation DELAY INNER _ DELAY.

9. The apparatus of claim 8, wherein when clock synchronizing the line card based on the time point T1 and the propagation DELAY INNER _ DELAY, the synchronization unit is specifically configured to:

calculating the difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

10. The apparatus of claim 9, wherein the synchronization unit is further to:

if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, wherein T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

Technical Field

The present disclosure relates to clock synchronization technologies, and in particular, to a clock compensation method and apparatus.

Background

With the emergence of the demand of high-precision time ground transmission of TD-SCDMA and TD-LTE systems, network equipment, base station equipment and the like are required to provide various types of high-precision time synchronization interfaces, the technology of 1PPS + TOD high-precision time synchronization interfaces proposed by China Mobile, and the specification of the high-precision time synchronization 1PPS + TOD interfaces is formulated. The output clock of the GPS satellite positioning system receiver adopts a 1PPS + TOD interface, and simultaneously, all large clock chip manufacturers support clock input and output modes of 1PPS + TOD.

The 1PPS + TOD synchronization technology synchronizes time once per second, namely, each time is synchronized by the time of a whole second, the 1PPS is a pulse of the whole second, and the time is carried in a TOD frame. With the development of wireless communication networks, performance indexes of the networks, such as peak rate, network delay, system capacity and the like, are greatly improved, so that the requirement on time synchronization of the system is gradually improved, wherein precision of a PTP (precision time protocol) protocol reaches the level of error below tens of ns, so that 1PPS (pulse per second) synchronization delay also needs to meet the requirement, and at the moment, routing delay of 1PPS signals at input and output of equipment cannot be ignored and must be accurately compensated.

At present, a clock compensation method is to add an FPGA between a clock chip 1PPS output and an equipment connector, delay and compensate a 1PPS trace to the FPGA, and implement a time (Counter count) increment function of a part of clock chips by the FPGA and output a 1PPS signal. However, the FPGA chip is added between the clock chip 1PPS output and the device connector, so that the FPGA is required to realize the RTC function of the clock chip, and the requirement on the FPGA is high. Meanwhile, 1PPS is generated by the FPGA, and the 1PPS output by the clock chip changes and can be reflected in the 1PPS output by the FPGA in the next period, namely, 1 second is delayed, and the timeliness of clock compensation is not high.

Disclosure of Invention

The application provides a clock compensation method and a clock compensation device, which are used for solving the problem of low timeliness of clock compensation in the prior art.

In a first aspect, the present application provides a clock compensation method applied to a main control board of a network device, where the main control board includes a main clock chip, and the method includes:

acquiring a time point T of the main clock chip, and acquiring a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network equipment;

determining the sum of the time point T of the master clock chip and the transmission DELAY TX _ DELAY as the time point T1 of the master clock chip transmitted to the output interface of the network device;

transmitting the time point T1 to other network devices through an output interface of the network device to enable the other network devices to perform clock synchronization based on the time point T1.

Optionally, if the network device does not have a time source input; the step of obtaining the time point T of the master clock chip includes:

determining local system time as a time point T of the master clock chip;

if the network device has a time source input, the step of obtaining the time point T of the master clock chip comprises the following steps:

acquiring a time point T' of the time source, and determining a transmission time DELAY RX _ DELAY from an input interface of the network equipment to an input pin of the master clock chip;

and determining the sum of the time point T' of the time source and the transmission time DELAY RX _ DELAY as the time point T of the master clock chip.

Optionally, the network device further includes a line card, and the method further includes:

determining the transmission time DELAY INNER _ DELAY from the output pin of the main clock chip to the input pin of the clock chip of the line card;

the line card is clock-synchronized based on the time point T1 and the transmission DELAY INNER _ DELAY.

Optionally, the step of clock-synchronizing the line card based on the time point T1 and the propagation DELAY INNER _ DELAY comprises:

calculating the difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

Optionally, the method further comprises:

if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, wherein T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

In a second aspect, the present application provides a clock compensation apparatus applied to a main control board of a network device, where the main control board includes a main clock chip, the apparatus includes:

the acquisition unit is used for acquiring a time point T of the master clock chip and acquiring transmission DELAY TX _ DELAY between an output pin of the master clock chip and an output interface of the network equipment;

a determining unit, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY TX _ DELAY as a time point T1 of the master clock chip being transmitted to an output interface of the network device;

a transmission unit, configured to transmit the time point T1 to another network device through an output interface of the network device, so that the other network device performs clock synchronization based on the time point T1.

Optionally, if the network device does not have a time source input; when the time point T of the master clock chip is obtained, the obtaining unit is specifically configured to:

determining local system time as a time point T of the master clock chip;

if the network device has a time source input, and the time point T of the master clock chip is obtained, the obtaining unit is specifically configured to:

acquiring a time point T' of the time source, and determining a transmission time DELAY RX _ DELAY from an input interface of the network equipment to an input pin of the master clock chip;

and determining the sum of the time point T' of the time source and the transmission time DELAY RX _ DELAY as the time point T of the master clock chip.

Optionally, the network device further includes a line card, and the apparatus further includes a synchronization unit:

the acquisition unit is further configured to acquire a transmission DELAY INNER _ DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line card;

the synchronization unit is configured to perform clock synchronization on the line card based on the time point T1 and the propagation DELAY INNER _ DELAY.

Optionally, when the line card is clocked based on the time point T1 and the transmission DELAY INNER _ DELAY, the synchronization unit is specifically configured to:

calculating the difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

Optionally, the synchronization unit is further configured to:

if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, wherein T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

In a third aspect, an embodiment of the present application provides a clock compensation apparatus, including:

a memory for storing program instructions;

a processor for calling program instructions stored in said memory and for executing the steps of the method according to any one of the above first aspects in accordance with the obtained program instructions.

In a fourth aspect, the present application further provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the steps of the method according to any one of the above first aspects.

In summary, the clock compensation method provided in the embodiment of the present application is applied to a main control board of a network device, where the main control board includes a main clock chip, and the method includes: acquiring a time point T of the main clock chip, and acquiring a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network equipment; determining the sum of the time point T of the master clock chip and the transmission DELAY TX _ DELAY as the time point T1 of the master clock chip transmitted to the output interface of the network device; transmitting the time point T1 to other network devices through an output interface of the network device to enable the other network devices to perform clock synchronization based on the time point T1.

By adopting the clock compensation method provided by the embodiment of the application, the main clock chip of the network equipment has the function of inputting 1PPS synchronous time and also has the function of outputting 1PPS signals to other equipment for time synchronization. The 1PPS of clock chip output walks line delay compensation, through the compensation value of adjustment input 1PPS signal, reaches compensation 1PPS output delay compensation to reach the effect of compensating every 1PPS signal in real time.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings of the embodiments of the present application.

Fig. 1 is a detailed flowchart of a clock compensation method according to an embodiment of the present disclosure;

fig. 2 is a schematic process diagram of a clock compensation method according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a clock compensation apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another clock compensation apparatus according to an embodiment of the present application.

Detailed Description

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein is meant to encompass any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Depending on the context, moreover, the word "if" as used may be interpreted as "at … …" or "when … …" or "in response to a determination".

Exemplarily, referring to fig. 1, a detailed flowchart of a clock compensation method provided in an embodiment of the present application is shown, where the method is applied to a master control board of a network device, where the master control board includes a master clock chip, and the method includes the following steps:

step 100: and acquiring a time point T of the main clock chip, and acquiring a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network equipment.

In the embodiment of the application, if the network equipment does not have time source input; when the time point T of the master clock chip is obtained, a preferred implementation is to determine the local system time as the time point T of the master clock chip.

That is to say, if the network device does not have an external time source input, the acquired local system time of the network device can be used as the reference time point T of the master clock chip of the network device, and the problem that the reference time point received by the master clock chip is inaccurate due to the clock signal transmission delay generated by the routing does not occur.

Optionally, if there is a time source input to the network device, when the time point T of the master clock chip is obtained, a preferred implementation manner is to obtain a time point T' of the time source and determine a transmission DELAY RX _ DELAY between the input interface of the network device and the input pin of the master clock chip.

That is, if the network device has an external time source input, and the master clock chip receives the clock signal T 'input by the external time source, at this time, since the transmission DELAY RX _ DELAY of the clock signal may exist between the input interface of the network device and the input pin of the master clock chip, the time of the master clock chip needs to be compensated, that is, the sum of the time point T' of the external time source and the transmission DELAY RX _ DELAY between the input interface of the network device and the input pin of the master clock chip is determined as the time point T of the master clock chip.

Step 110: the sum of the time point T of the master clock chip and the transmission DELAY TX _ DELAY is determined as the time point T1 when the master clock chip transmits to the output interface of the network device.

Further, the master control board needs to transmit the clock signal to the other external network devices, and then, due to the fact that there are traces between the output pins of the clock chip of the master control board and the output interfaces of the network devices, there is a transmission DELAY TX _ DELAY in the clock signal transmission, in this embodiment of the present application, the clock signal is compensated in advance on the clock chip, that is, the time point output to the external network devices is set to T1 ═ T + TX _ DELAY ═ T' + RX _ DELAY + TX _ DELAY.

Step 120: transmitting the time point T1 to other network devices through an output interface of the network device to enable the other network devices to perform clock synchronization based on the time point T1.

As can be seen from the above, the clock signal transmitted by the other network device at the output interface of the network device is T1.

Further, the network device further comprises a line card, and then the clock compensation method further comprises the following steps:

determining the transmission time DELAY INNER _ DELAY from the output pin of the main clock chip to the input pin of the clock chip of the line card;

the line card is clock-synchronized based on the time point T1 and the transmission DELAY INNER _ DELAY.

In the embodiment of the present application, when the line card is clocked based on the time point T1 and the transmission DELAY INNER _ DELAY, a preferable implementation is to calculate a difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

Further, if the difference is determined to be less than 0, processing the time point T1 by the FPGA to obtain a time point T3, where T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

The following describes in detail a structure of a network device provided in the embodiments of the present application with reference to a specific application scenario. Exemplarily, referring to fig. 2, for a schematic structural diagram of a network device provided in an embodiment of the present application, a network card device includes a main board card and a plurality of line board cards (e.g., the line board card 1, the line board cards 2, … …, and the line board card N), a clock buckle of the main board card includes an FPGA and a clock chip (referred to as a main clock chip), if a time point of the main clock chip acquired by the network device is T, when a clock signal is transmitted to another external network device through a node 3 (an output interface of the network card device), it is necessary to determine a transmission DELAY TX _ DELAY between an output pin of the main clock chip and an output interface of the network device, and compensate for the time T in advance at the main clock chip, that is, after the time point of the main clock chip is set to T + TX _ DELAY, the clock signal is transmitted to the other external network device through the output interface of the network device, thus, the time point when the external other network device receives the clock signal is T + TX _ DELAY.

Further, when the master clock chip performs clock synchronization with other line card on the network device, compensation operation needs to be performed in advance due to the transmission DELAY INNER _ DELAY existing between the master control board and the other line card, since the master clock chip has only one clock output and has been compensated once based on the transmission DELAY TX _ DELAY between the output pin of the master clock chip and the output interface of the network device, and when the clock signal is synchronized to the other line card, the clock signal does not need to pass through the route between the output pin of the master clock chip and the output interface of the network device, then the synthetically determined compensation value is INNER _ DELAY-TX _ DELAY, and clock compensation is performed based on the INNER _ DELAY-TX _ DELAY.

For example, if the INNER _ DELAY-TX _ DELAY is a positive value, the compensation value may directly set compensation on the PHY of the line card, and if the INNER _ DELAY-TX _ DELAY is a negative value, the TX _ DELAY may be delayed by 1PPS by the FPGA through which the main clock output passes, and then issued to the corresponding line card board, where the line card board only needs to compensate the INNER _ DELAY.

Exemplarily, referring to fig. 3, a schematic structural diagram of a clock compensation apparatus provided in an embodiment of the present application is shown, where the apparatus is applied to a main control board of a network device, where the main control board includes a main clock chip, and the apparatus includes:

an obtaining unit 30, configured to obtain a time point T of the master clock chip, and obtain a transmission DELAY TX _ DELAY between an output pin of the master clock chip and an output interface of the network device;

a determining unit 31, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY TX _ DELAY as a time point T1 of the master clock chip being transmitted to the output interface of the network device;

a transmission unit 32, configured to transmit the time point T1 to another network device through an output interface of the network device, so that the other network device performs clock synchronization based on the time point T1.

Optionally, if the network device does not have a time source input; when the time point T of the master clock chip is obtained, the obtaining unit 30 is specifically configured to:

determining local system time as a time point T of the master clock chip;

if the network device has a time source input, and the obtaining unit 30 is specifically configured to, when obtaining the time point T of the master clock chip:

acquiring a time point T' of the time source, and determining a transmission time DELAY RX _ DELAY from an input interface of the network equipment to an input pin of the master clock chip;

and determining the sum of the time point T' of the time source and the transmission time DELAY RX _ DELAY as the time point T of the master clock chip.

Optionally, the network device further includes a line card, and the apparatus further includes a synchronization unit:

the obtaining unit 30 is further configured to obtain a transmission DELAY INNER _ DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line card;

the synchronization unit is configured to perform clock synchronization on the line card based on the time point T1 and the propagation DELAY INNER _ DELAY.

Optionally, when the line card is clocked based on the time point T1 and the transmission DELAY INNER _ DELAY, the synchronization unit is specifically configured to:

calculating the difference between the transmission DELAY INNER _ DELAY and the transmission DELAY TX _ DELAY;

judging whether the difference value is greater than or equal to 0;

if the difference is judged to be greater than or equal to 0, transmitting the time point T1, the transmission DELAY TX _ DELAY and the transmission DELAY INNER _ DELAY to the clock chip of the line card through the output pin of the master clock chip so that the clock chip sets the time point of the line card to be T2, wherein T2 is T1-TX _ DELAY + INNER _ DELAY.

Optionally, the synchronization unit is further configured to:

if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, wherein T3 is T1-TX _ DELAY;

transmitting the time point T3 and the transmission DELAY INNER _ DELAY to a clock chip of the line card, so that the clock chip sets the time point of the line card to be T4, wherein T4 is T3+ INNER _ DELAY.

The above units may be one or more integrated circuits configured to implement the above methods, for example: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above units is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these units may be integrated together and implemented in the form of a system-on-a-chip (SOC).

In view of the above, it can be seen that,

further, in the clock compensation apparatus provided in the embodiment of the present application, from a hardware aspect, a schematic diagram of a hardware architecture of the clock compensation apparatus may be shown in fig. 4, where the clock compensation apparatus may include: a memory 40 and a processor 41, which,

memory 40 is used to store program instructions; processor 41 calls program instructions stored in memory 40 and executes the above-described method embodiments in accordance with the obtained program instructions. The specific implementation and technical effects are similar, and are not described herein again.

Optionally, the present application also provides a clock compensation device comprising at least one processing element (or chip) for performing the above method embodiments.

Optionally, the present application also provides a program product, such as a computer-readable storage medium, having stored thereon computer-executable instructions for causing the computer to perform the above-described method embodiments.

Here, a machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and so forth. For example, the machine-readable storage medium may be: a RAM (random Access Memory), a volatile Memory, a non-volatile Memory, a flash Memory, a storage drive (e.g., a hard drive), a solid state drive, any type of storage disk (e.g., an optical disk, a dvd, etc.), or similar storage medium, or a combination thereof.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Furthermore, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.