阅读说明：本技术 应用于电子器件的混合封装方法及混合封装结构 (Hybrid packaging method and hybrid packaging structure applied to electronic device ) 是由 潘保顺 彭虎 于 2020-12-14 设计创作，主要内容包括：本发明公开了一种应用于电子器件的混合封装方法及混合封装结构。所述应用于电子器件的混合封装方法包括：将至少一基板或者至少一基板与至少一第一芯片与导线框架结合；对结合有所述基板或所述第一芯片与基板的导线框架进行打线键合处理,之后进行封装处理。本发明实施例提供的一种应用于电子器件的混合封装方法能够匹配电路实现芯片集成、高要求的芯片散热能力、降低封装热阻、芯片性能稳定、降级成本、减薄电子设备外观体积以及提升PCB单位面积使用效率等优点。(The invention discloses a hybrid packaging method and a hybrid packaging structure applied to an electronic device. The hybrid packaging method applied to the electronic device comprises the following steps: combining at least one substrate or at least one substrate and at least one first chip with the lead frame; and carrying out wire bonding treatment on the lead frame combined with the substrate or the first chip and the substrate, and then carrying out packaging treatment. The hybrid packaging method applied to the electronic device provided by the embodiment of the invention can be used for matching circuits to realize the advantages of chip integration, high-requirement chip heat dissipation capability, packaging thermal resistance reduction, stable chip performance, cost degradation, electronic equipment appearance volume reduction, PCB unit area use efficiency improvement and the like.)

1. A hybrid packaging method applied to an electronic device, comprising:

combining at least one substrate or at least one substrate and at least one first chip with the lead frame;

and carrying out wire bonding treatment on the lead frame combined with the substrate or the first chip and the substrate, and then carrying out packaging treatment.

2. The hybrid packaging method applied to electronic devices according to claim 1, specifically comprising: and at least one first chip is attached to the lead frame in any one mode of adhesive dispensing, adhesive brushing and adhesive inverting.

3. The hybrid packaging method applied to electronic devices according to claim 1, specifically comprising: and at least one substrate is attached to the lead frame in any one mode of at least one of adhesive dispensing patch or welding patch.

4. The hybrid packaging method applied to electronic devices according to claim 1, specifically comprising: the at least one substrate and the at least one first chip are simultaneously mounted on the lead frame, or the at least one substrate and the at least one first chip are mounted on the lead frame according to a set sequence.

5. The hybrid packaging method applied to electronic devices according to claim 1, comprising: bonding at least one component and/or at least one second chip on the substrate, and then bonding the substrate with a lead frame;

preferably, at least one second chip is mounted on the substrate in any one of a glue dispensing patch, a glue brushing patch and an inverted patch;

preferably, the at least one component is bonded to the substrate at least by soldering.

6. The hybrid packaging method applied to electronic devices according to claim 5, wherein: the first chip or the second chip comprises any one or the combination of more than two of a silicon chip, a gallium arsenide chip, a gallium nitride chip and a silicon carbide chip;

and/or the component comprises any one or a combination of more than two of a resistor, a capacitor and an inductor;

and/or the substrate comprises any one or the combination of more than two of a multi-ceramic substrate, a mixed sintering substrate, a copper-clad substrate and a soft board.

7. The hybrid packaging method applied to electronic devices according to claim 1, specifically comprising: connecting the first chip, the substrate and the lead frame through metal wires;

and/or, the hybrid packaging method applied to the electronic device specifically comprises the following steps: and realizing the packaging treatment at least by adopting an injection molding and packaging mode.

8. A hybrid packaging structure applied to electronic devices is characterized by comprising at least one substrate or at least one substrate and at least one first chip, a lead frame and a plastic package body, wherein at least the substrate or the substrate and the first chip and the lead frame are packaged in the plastic package body, the substrate and the at least one first chip are combined on the lead frame, a metal wire is further bonded on any one of the substrate, the first chip and the lead frame so as to at least enable the substrate or the substrate and the first chip to be electrically connected with the lead frame, and at least one unitary device and/or at least one second chip are further combined on the substrate.

9. The hybrid package structure of claim 8, wherein: the first chip or the second chip comprises any one or the combination of more than two of a silicon chip, a gallium arsenide chip, a gallium nitride chip and a silicon carbide chip.

10. The hybrid package structure of claim 8, wherein: the component comprises any one or the combination of more than two of a resistor, a capacitor and an inductor; and/or the substrate comprises any one or the combination of more than two of a multi-ceramic substrate, a mixed sintering substrate, a copper-clad substrate and a soft board.

Technical Field

The invention particularly relates to a hybrid packaging method and a hybrid packaging structure applied to an electronic device, and belongs to the technical field of semiconductor packaging.

Background

Lead frame packaging products (such as QFN/DFN packaging) can only be pasted with a single chip or multiple chips to realize circuit integration, but the internal structure of the chip cannot pass large current and large voltage, the power cannot be too high, and all market requirements cannot be met; the substrate packaging product (such as LGA/BGA package) can meet the requirements of large current and large voltage, a designed circuit is matched to realize chip integration, but the power device with high heat dissipation requirements cannot be met, the performance is unstable, the working efficiency is low, and the manufacturing cost is high.

Disclosure of Invention

The present invention is directed to a hybrid packaging method and a hybrid packaging structure for electronic devices, which overcome the disadvantages of the prior art.

In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:

the embodiment of the invention provides a hybrid packaging method applied to an electronic device, which comprises the following steps:

combining at least one substrate or at least one substrate and at least one first chip with the lead frame;

and carrying out wire bonding treatment on the lead frame combined with the substrate or the first chip and the substrate, and then carrying out packaging treatment.

Further, the hybrid packaging method applied to the electronic device specifically includes: and at least one first chip is attached to the lead frame in any one mode of adhesive dispensing, adhesive brushing and adhesive inverting.

Further, the hybrid packaging method applied to the electronic device specifically includes: and at least one substrate is attached to the lead frame in any one mode of at least one of adhesive dispensing patch or welding patch.

Further, the hybrid packaging method applied to the electronic device specifically includes: the at least one substrate and the at least one first chip are simultaneously mounted on the lead frame, or the at least one substrate and the at least one first chip are mounted on the lead frame according to a set sequence.

Further, the hybrid packaging method applied to the electronic device comprises the following steps: at least one component and/or at least one second chip is bonded to the substrate, after which the substrate is bonded to a leadframe.

Furthermore, at least one second chip is attached to the substrate in any one of a glue dispensing patch, a glue brushing patch and an inverted patch.

Furthermore, at least one component is bonded to the substrate by at least soldering.

Further, the first chip or the second chip includes any one of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip or a combination of two or more of them, but is not limited thereto.

Further, the component includes any one or a combination of two or more of a resistor, a capacitor, and an inductor, but is not limited thereto.

Further, the substrate includes any one or a combination of two or more of a multi-ceramic substrate, a hybrid sintered substrate, a copper clad substrate, and a flexible printed circuit board, but is not limited thereto.

Further, the hybrid packaging method applied to the electronic device specifically includes: and connecting the first chip, the substrate and the lead frame through metal wires.

Further, the hybrid packaging method applied to the electronic device specifically comprises the step of realizing the packaging treatment at least by adopting an injection molding and packaging mode.

The embodiment of the invention also provides a hybrid packaging structure applied to an electronic device, which comprises at least one substrate or at least one substrate and at least one first chip, a lead frame and a plastic package body, wherein at least the substrate or the substrate and the first chip as well as the lead frame are packaged in the plastic package body, the substrate and the at least one first chip are combined on the lead frame, any one of the substrate, the first chip and the lead frame is also bonded with a metal wire so as to at least electrically connect the substrate or the substrate and the first chip with the lead frame, and the substrate is also combined with at least one unary device and/or at least one second chip.

Further, the first chip or the second chip includes any one of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip or a combination of two or more of them, but is not limited thereto.

Further, the component includes any one or a combination of two or more of a resistor, a capacitor, and an inductor, but is not limited thereto.

Further, the substrate includes any one or a combination of two or more of a multi-ceramic substrate, a hybrid sintered substrate, a copper clad substrate, and a flexible printed circuit board, but is not limited thereto.

Compared with the prior art, the invention has the advantages that: the hybrid packaging method applied to the electronic device provided by the embodiment of the invention can be used for matching circuits to realize the advantages of chip integration, high-requirement chip heat dissipation capability, packaging thermal resistance reduction, stable chip performance, cost degradation, electronic equipment appearance volume reduction, PCB unit area use efficiency improvement and the like.

Drawings

FIG. 1 is a schematic view of a substrate according to an exemplary embodiment of the present invention;

fig. 2 is a schematic diagram of a structure with components and a chip substrate formed thereon according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram of a chip on substrate structure in accordance with an exemplary embodiment of the present invention;

fig. 4 is a schematic diagram of a substrate patch on a lead frame in accordance with an exemplary embodiment of the present invention;

fig. 5 is a schematic diagram of a chip die mounted on a lead frame in accordance with an exemplary embodiment of the present invention.

Detailed Description

In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The following further explains the technical solutions, the implementation processes and principles thereof, and the processing techniques adopted in the embodiments of the present invention can be known to those skilled in the art unless otherwise specified.

The Hybrid Package (Hybrid Package) structure can realize chip integration, and can satisfy high heat dissipation requirement, reduce cost, the scheme of base plate and lead frame Hybrid preparation is a brand-new circuit integration, high heat dissipation's Hybrid (Hybrid) encapsulation form, contained chip paster (die attached) in the plastic envelope, base plate (laminate) paster (contained components and parts on the base plate, the chip), utilize the internal maximum limit space of plastic envelope, can match the circuit and realize chip integration, high required chip heat-sinking capability, reduce the encapsulation thermal resistance, improve chip stable performance, the degradation cost, advantages such as thinning electronic equipment outward appearance volume and promotion PCB unit area availability factor.

The embodiment of the invention provides a method for hybrid manufacturing of a substrate (laminate) and a lead-frame (lead-frame), wherein a chip patch and a substrate patch (processes of welding components, mounting chips and the like are included on the substrate) are included in a plastic package, and the purposes of realizing high integration of the chip, meeting the high heat dissipation requirement of the chip, continuously and stably electrical property, reducing cost, reducing the appearance volume of an electronic device, improving the use efficiency of a PCB (printed circuit board) in unit area and the like can be realized by matching a hybrid packaging form of the substrate.

At present, SMD (passive component) mostly adopts in QFN/DFN package for packaging, but the existing component can not meet the requirement of complex circuit integration; the QFN/DFN is also common for die packaging processes, but multi-die products have a high requirement on the volume of the package, different die applications, different chip processes and higher cost for different wafers.

The package structure and method applied to the electronic device provided by the invention also need to consider the warp factor of the substrate, such as copper CTE 16, epoxy (ag) CTE 20, and then the CTE (coefficient of thermal expansion) of the substrate needs to be adapted to 10-20, so as to avoid package reliability failure caused by serious warp and too large stress in the high-temperature soldering/curing process.

The packaging structure and the method applied to the electronic device provided by the invention need to consider a substrate Loading mode in a chip mounting process selection method, such as taping (similar to Components-SMD) or blue film de-UV (Die pick up form), and parameters such as substrate thickness can be set by referring to the thickness of the QFN/DFN Mold Cap in the prior OSAT (encapsulation substitute).

The packaging structure method applied to the electronic device provided by the invention needs to pay attention in the packaging patch:

1) type selection of suction nozzle (suction substrate patch): the hollow height and edge width of the suction nozzle need to be designed according to the layout of the substrate and the position of the SMD (surface mounted device) of the component, so as to prevent the substrate from being damaged and the component from being collided;

2) the vacuum intensity of DA machine (die attached) absorption is debugged, when the number of components on the substrate is large and the chip volume is thick, the weight is much heavier than die itself, which is not an order of magnitude, so that the difficulty of DA (driver amplifier) is overcome by evaluating a proper absorption mode;

3.) DA Epoxy type selection, if high heat dissipation is required, if silver paste sintering operation is used, due to poor silver paste sintering operability, attention needs to be paid to side surface paste climbing which needs to be less than or equal to 95% die/substrate thickness, and if the paste amount is too large, silver migration is easy to occur in a reliability experiment to cause electric leakage;

4) in Wire binding arc collision, the design of a WB pressure plate needs to avoid the height of an arc to prevent Wire leakage;

5) plastic-packaged compound selection: because of the welding of components, the welding of chips, the welding of substrates, the welding of die, etc., the process/material is too much, the influence of the cavity generated in the process of compound injection molding and the stress after plastic package needs to be noticed, and in order to avoid Void and incomplete, the resin system can select the compound with smaller SPIRAL FLOW and smaller filler size; and a compound with a smaller Young modulus can be used for solving the packaging stress, and partial stress can be absorbed and converted by the material during the thermal processing (preferably, after the material is determined, stress simulation is needed to determine the material structure).

Referring to fig. 1 to 5, an embodiment of the present invention further provides a substrate and lead frame hybrid package structure, which includes at least one substrate 11, at least one first chip 32, a lead frame 61 and a plastic package body 51, wherein at least the substrate 11, the first chip 32 and the lead frame 61 are packaged in the plastic package body 51, the substrate 11 and the at least one first chip 32 are both bonded on the lead frame 61, a metal wire 41 is further bonded on any one of the substrate 11, the first chip 32 and the lead frame 61 to electrically connect at least the substrate 11 and the first chip 32 to the lead frame 61, and the substrate 11 is further bonded with at least one component 21 and/or at least one second chip 22.

Specifically, please refer to fig. 1, the substrate 11 may be a multilayer board or different materials selected according to the requirement of a designer, so as to implement circuit matching, the component 21 includes but is not limited to a capacitor, an inductor, a resistor, etc., the second chip 22 is mounted on the substrate 11 by means of a glue dispensing patch, a glue brushing patch, a flip-chip patch, etc., wherein the component 21 and the second chip 22 may be mounted alone or not, or may be mounted at the same time, specifically, the component may be set according to the requirement of a technician in the field, and after the component and the second chip are mounted, curing or reflow soldering is performed according to the parameters of a material manual.

Specifically, referring to fig. 4, the substrate 11 may be processed and formed by using two modes, namely Jig cutting (Jig saw) and Tape saw cutting (Tape saw), and a Tray (Tray) needs to be installed on a single substrate obtained after the Jig cutting, and whether to directly use the Tray package and attach the Tray on the device or use the Tape package to be welded on the lead frame 61 (similar to the SMT mode of the component) may be determined according to the processing capability of each foundry; the substrate formed by the adhesive film cutting method may be attached to the lead frame 61 by a glue-dispensing and attaching method (similar to wafer saw, using UV film + Ring), and the first chip 32 is attached to the lead frame 61 by a attaching and bonding method; the bonding mode of the substrate 11 and the first chip 32 is not limited to the type and mode of the material of the chip, and curing or reflow soldering is required after the chip is mounted.

Specifically, referring to fig. 4 again, the metal wires 41 are bonded to the lead frame 61, the first chip 32, and the substrate 11, the metal wires 41 include but are not limited to copper wires, palladium-plated copper wires, gold wires, aluminum wires, silver alloy wires, etc., the plastic package body 51 may be made of resin, and of course, a person skilled in the art may select different resin systems, different dielectric constants, different young moduli, different glass temperatures, and different filler sizes of resin materials according to electrical requirements and process requirements, and perform a post-curing process after the package is completed, and parameters of the post-curing process are set according to a data sheet (datasheet) of the material.

Specifically, the hybrid packaging method applied to the electronic device provided by the embodiment of the present invention includes the following steps: bonding at least one substrate 11 or at least one substrate 11 and at least one first chip 32 with the lead frame 61;

wire bonding the substrate 11 or the first chip 32 and the lead frame 61 of the substrate 11, and packaging

1) Bonding at least one component 21 on the substrate 11 by at least welding, and attaching at least one second chip 22 on the substrate 11 by at least any one of adhesive dispensing, adhesive brushing and flip chip;

2) attaching at least one of the substrates 11 to the lead frame 61 by at least any one of a dispensing adhesive sheet or a soldering adhesive sheet, and attaching at least one of the first chips 32 to the lead frame 61 by at least any one of a dispensing adhesive sheet, a brushing adhesive sheet, and a flip chip sheet;

3) the lead frame 61 with the first chip 32 and the substrate 11 attached thereto in the step 2) is wire bonded, and then is packaged.

Specifically, the substrate 11 in the embodiment of the present invention includes, but is not limited to, various substrates such as a multi-ceramic substrate, a hybrid sintered substrate, a copper-clad substrate, and a flexible printed circuit board, the components 21 include, but is not limited to, components such as a resistor, a capacitor, and an inductor, and the manner in which the substrate 11 is attached to the lead frame includes, but is not limited to, a dispensing patch, a soldering patch, and the like; the mounting process of the first chip 32 and the mounting process of the substrate 11 may be completed simultaneously or separately, and are not in sequence.

Specifically, the first chip 32 in step 2) may also be mounted on the substrate 11 (chip bonding includes Flip chip technology), but at least one chip is mounted on the lead frame, and the first chip 32 and the second chip 22 include, but are not limited to, a silicon chip, a gallium arsenide chip, a gallium nitride chip, a silicon carbide chip, and the like.

The hybrid packaging method applied to the electronic device provided by the embodiment of the invention can be used for matching circuits to realize the advantages of chip integration, high-requirement chip heat dissipation capability, packaging thermal resistance reduction, stable chip performance, cost degradation, electronic equipment appearance volume reduction, PCB unit area use efficiency improvement and the like.

It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.