阅读说明：本技术 一种堆叠式芯片封装结构及其制作方法 (Stacked chip packaging structure and manufacturing method thereof ) 是由 贺晓辉 石磊 蒋雨芯 朱永丽 赵世纪 于 2020-12-01 设计创作，主要内容包括：本发明公开了一种堆叠式芯片封装结构及其制作方法,涉及半导体技术领域,包括基板,形成于基板的第二表面上的多个焊球,用于电连接到外部电路；并排设置在基板上的多个绝缘座,绝缘座的上端面设有一缺口朝上的直角缺口,直角缺口向一侧倾斜设置,且多个绝缘座上的直角缺口开口方向一致；一一固定在绝缘座上的直角缺口内的多片芯片；分别用于多片芯片与基板之间的电性连接多个金属凸块；以及形成于基板上的封装胶体。本发明能够在无需制作硅通孔的情况下将多个芯片堆叠在一起,不会对各芯片的集成电路及测试构成不良影响,且本发明的堆叠式芯片封装结构制作工艺简单、制造成本低、散热效果好,能够提高堆叠式芯片封装结构的生产效率和成品率。(The invention discloses a stacked chip packaging structure and a manufacturing method thereof, relating to the technical field of semiconductors, comprising a substrate, a plurality of solder balls formed on the second surface of the substrate and used for being electrically connected to an external circuit; the insulating bases are arranged on the substrate side by side, the upper end faces of the insulating bases are provided with right-angle notches with upward notches, the right-angle notches are arranged in an inclined mode towards one side, and the opening directions of the right-angle notches on the insulating bases are consistent; the chips are fixed in the right-angle notches on the insulating seat one by one; the metal bumps are respectively used for electrically connecting the chips and the substrate; and an encapsulant formed on the substrate. The invention can stack a plurality of chips without manufacturing through silicon vias, and has no adverse effect on the integrated circuit and the test of each chip.)

1. A stacked chip package structure, comprising:

a substrate having a first surface and a second surface;

a plurality of solder balls formed on the second surface of the substrate for electrical connection to an external circuit;

the upper end surface of each insulating seat is provided with a right-angle notch with an upward notch, the right-angle notches are obliquely arranged towards one side, the lower end surface of each insulating seat is fixed on the first surface of the substrate, the insulating seats are arranged side by side, and the opening directions of the right-angle notches on the insulating seats are consistent;

the chips are fixed in the right-angle notches on the insulating seat one by one and are arranged in parallel;

the metal bumps are respectively positioned in gaps among the insulating bases and are respectively used for electrically connecting the chips with the substrate;

the packaging colloid is formed on the substrate to cover the plurality of chips, the plurality of insulating seats and the plurality of metal bumps and fill gaps among the plurality of insulating seats.

2. The stacked chip package structure of claim 1, wherein there is an overlapping portion between any two adjacent chips, and an insulating layer is disposed between overlapping surfaces of the overlapping portions of any two adjacent chips.

3. The stacked chip package structure as claimed in claim 2, wherein an adhesive layer is disposed in the right-angle notch of the upper surface of the insulating base, and the chip is adhered in the right-angle notch.

4. The stacked chip package structure according to claim 3, wherein the angle of inclination of the right-angle notch of the upper surface of the insulating base is 30-45 °.

5. The stacked chip package structure as claimed in any one of claims 1 to 4, wherein the insulating base is a rectangular parallelepiped structure.

6. A method for manufacturing a stacked chip package structure according to claim 5, comprising the steps of:

s1, fixing a plurality of insulating bases on the first surface of the substrate side by side respectively, and keeping the opening directions of the right-angle notches consistent;

s2, respectively bonding a plurality of chips in the right-angle notch on the insulating base one by one, and bonding an insulating layer on the overlapping part of the previous chip and the next chip before bonding the next chip;

s3, electrically connecting the multiple chips with the substrate through the metal bumps by adopting a flip chip bonding technology;

s4, forming a packaging colloid on the substrate, coating the plurality of chips, the plurality of insulating seats and the plurality of metal bumps, and filling gaps among the plurality of insulating seats;

and S5, forming a plurality of solder balls on the second surface of the substrate.

7. The method of claim 6, wherein the bonding of the plurality of chips to the right-angled notches of the insulating base is performed by bonding the plurality of chips to the right-angled notches of the insulating base one by one from the ends of the insulating base facing the openings of the right-angled notches.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a stacked chip packaging structure and a manufacturing method thereof.

Background

The stacked chip package structure is a semiconductor package structure with multiple chips vertically stacked by using three-dimensional packaging technology, and can be applied to storage devices such as memory modules, memory cards or flash drives. The memory module is a standardized product, such as a Dynamic Random Access Memory (DRAM) module, and is commonly used in desktop computers, notebook computers or industrial computers, and the memory capacity and access speed thereof are continuously increased and accelerated to meet the requirements of computer operations. In a conventional memory module, a plurality of memory chips are disposed on a single circuit board, and the memory chips are disposed in a single-sided inline manner or a double-sided inline manner, and their leads are soldered to a substrate by using a Surface Mount Technology (SMT). In addition, the memory module can be inserted into the PCI slot of the motherboard of the computer by using the plug-in surface joint interface (such as golden finger) arranged on the circuit board for transmitting the required data.

However, the larger the required capacity of the memory module, the higher the number of memory chips and the larger the area required for the substrate. Therefore, the memory module configured according to the conventional method cannot expand its storage capacity rapidly and largely, and the development of the three-dimensional package structure is inevitable. Common packaging technologies applied to memory modules include Wire bonding (Wire bonding) Package, Flip-chip bonding (Flip-chip bonding) Package, Package On Package (Package On Package), Gold to Gold interconnection (GGI) Package, Through Silicon Via (TSV) Package, and the like. These packaging technologies are developed to meet the demand for high-density memory capacity, and are three-dimensional packaging structures. Taking the through-silicon-Via packaging technique as an example, a micro-Via (Via) with a high aspect ratio is first fabricated on a silicon substrate, then a conductive material is filled in the micro-Via, and a solder ball (solder bump) is formed on the silicon substrate so as to electrically connect the solder ball with the conductive material in the micro-Via. However, in order to stack a plurality of chips together, a through silicon via structure needs to be fabricated in each chip, which not only has complex process, high manufacturing cost and low production efficiency, but also has bad influence on the electrical performance and reliability of the integrated circuit in the chip due to the fabrication of the through silicon via, and the heat dissipation effect is poor after the plurality of chips are stacked together. In addition, the silicon through hole structure is manufactured in each chip, so that the chip testing is difficult, and the yield is low.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a stacked chip package structure and a method for manufacturing the same, in which a plurality of chips are stacked together without through silicon vias, and the stacked chip package structure has the advantages of simple manufacturing process, low manufacturing cost, high production efficiency, good heat dissipation effect, and high yield, and does not adversely affect the integrated circuits and tests of the chips.

The invention solves the technical problems by the following technical means:

a stacked chip package structure, comprising:

a substrate having a first surface and a second surface;

a plurality of solder balls formed on the second surface of the substrate for electrical connection to an external circuit;

the upper end surface of each insulating seat is provided with a right-angle notch with an upward notch, the right-angle notches are obliquely arranged towards one side, the lower end surface of each insulating seat is fixed on the first surface of the substrate, the insulating seats are arranged side by side, and the opening directions of the right-angle notches on the insulating seats are consistent;

the plurality of chips are fixed in the right-angle notches on the insulating base one by one and are arranged in parallel;

the metal bumps are respectively positioned in gaps among the insulating bases and are respectively used for electrically connecting the chips with the substrate;

the packaging colloid is formed on the substrate to cover the plurality of chips, the plurality of insulating seats and the plurality of metal bumps and fill gaps among the plurality of insulating seats.

Furthermore, an overlapping part is arranged between any two adjacent chips, and an insulating layer is arranged between overlapping surfaces of the overlapping parts of any two adjacent chips. Through overlapping any two adjacent chips, the volume of the stacked chips can be reduced, the chips can be supported and balanced mutually, the local stress of each chip in the manufacturing process can be reduced, and the chips are protected better.

Furthermore, an adhesive layer is arranged in the right-angle notch of the upper end face of the insulating base, and the chip is adhered to the right-angle notch. The adhesive layer can be used for quickly positioning the position of the chip, can be used for adjusting the bonded chip and then bonding the chip, and is convenient for setting the insulating layer between the overlapping surfaces of any two adjacent chip overlapping parts.

Further, the inclination angle of the right angle gap of the upper end surface of the insulating base is 30-45 degrees. The undersize or small inclination angle of the right-angle notch can increase the volume of the chip packaging structure, and the packaging colloid layer of each chip is coated with the chip, so that the heat dissipation of the chip is not facilitated.

Further, the insulating base is of a cuboid structure. The cuboid structure is more convenient to be arranged in parallel of the insulating bases, and the cuboid structure is good in stability after being fixed on the substrate.

It should be noted that the shape of the encapsulant can be designed into a parallelogram according to the inclination of the chip where the front and rear ends are located, and the upper end surface of the encapsulant can be designed into a zigzag structure according to the recess formed by the overlapping portion of any two adjacent chips, which is more beneficial to the heat dissipation of the chip and further reduces the chip encapsulation volume.

In addition, the invention also provides a manufacturing method of the stacked chip packaging structure, which comprises the following steps:

s1, fixing a plurality of insulating bases on the first surface of the substrate side by side respectively, and keeping the opening directions of the right-angle notches consistent;

s2, respectively bonding a plurality of chips in the right-angle notch on the insulating base one by one, and bonding an insulating layer on the overlapping part of the previous chip and the next chip before bonding the next chip;

s3, electrically connecting the multiple chips with the substrate through the metal bumps by adopting a flip chip bonding technology;

s4, forming a packaging colloid on the substrate, coating the plurality of chips, the plurality of insulating seats and the plurality of metal bumps, and filling gaps among the plurality of insulating seats;

and S5, forming a plurality of solder balls on the second surface of the substrate.

Furthermore, the process of bonding the plurality of chips in the right-angle notch on the insulating base one by one is characterized in that the plurality of chips are respectively bonded in the right-angle notch on the insulating base one by one from one end of the opening of the right-angle notch on the insulating base towards the opening.

The invention has the beneficial effects that: the invention can stack a plurality of chips without manufacturing through silicon vias, and can not have adverse effect on the integrated circuit and the test of each chip, and the thickness of the chip can be reduced by obliquely stacking the plurality of chips, so that the overall thickness of the stacked chip packaging structure is reduced, the purpose of high-density 3D stacked packaging is achieved, the chips can be supported and balanced mutually, the local stress of each chip in the manufacturing process can be reduced, and the chips are protected better; in addition, the stacked chip packaging structure has the advantages of simple manufacturing process, low manufacturing cost and good heat dissipation effect, and can effectively improve the production efficiency and the yield of the stacked chip packaging structure.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic view of the structure of the insulating base of the present invention;

the chip package comprises a substrate 1, a first surface 101, a second surface 102, solder balls 2, an insulating base 3, a right-angle notch 4, a chip 5, a metal bump 6, a packaging colloid 7, an insulating layer 8 and an adhesive layer 9.

Detailed Description

The present invention will be described in detail with reference to examples below:

example one

As shown in fig. 1 and 2, a stacked chip package structure includes:

a substrate 1 having a first surface 101 and a second surface 102;

a plurality of solder balls 2, the plurality of solder balls 2 being formed on the second surface 102 of the substrate 1 for electrical connection to an external circuit;

the upper end face of each insulating seat 3 is provided with a right-angle notch 4 with an upward notch, the right-angle notches 4 are obliquely arranged towards one side, the lower end face of each insulating seat 3 is fixed on the first surface 101 of the substrate 1, the insulating seats 3 are arranged side by side, and the opening directions of the right-angle notches 4 on the insulating seats 3 are consistent;

the plurality of chips 5 are fixed in the right-angle notches 4 on the insulating base 3 one by one, and the plurality of chips 5 are arranged in parallel;

the metal bumps 6 are respectively positioned in gaps among the insulating bases 3 and are respectively used for electrically connecting the chips 5 with the substrate 1;

the encapsulant 7 is formed on the substrate 1 to encapsulate the chips 5, the insulating bases 3, and the metal bumps 6, and to fill gaps between the insulating bases 3.

Any two adjacent chips 5 are provided with overlapping parts, and an insulating layer 8 is arranged between overlapping surfaces of the overlapping parts of any two adjacent chips 5. Through overlapping any two adjacent chips 5, the volume of the stacked chips 5 can be reduced, the chips 5 can be supported and balanced mutually, the local stress of each chip 5 in the manufacturing process can be reduced, and the chips 5 can be protected better.

The right-angle notch 4 of the upper end face of the insulating base 3 is internally provided with an adhesive layer 9, and the chip 5 is adhered and positioned in the right-angle notch 4. The adhesive layer 9 can quickly position the chip 5, can adjust the bonded chip 5 and then bond the chip, and is convenient for setting the insulating layer 8 between the overlapping surfaces of the overlapping parts of any two adjacent chips 5.

The inclination angle of the right angle gap 4 of the upper end surface of the insulating base 3 is 30-45 degrees. The small or small inclination angle of the right-angle notch 4 can increase the volume of the chip packaging structure, and the packaging colloid layer of the chip 5 is coated on each chip, which is not beneficial to the heat dissipation of the chip 5.

The insulating base 3 is a rectangular parallelepiped structure. The cuboid structure is more convenient to be arranged in parallel of the insulating bases 3, and the cuboid structure is good in stability after being fixed on the substrate.

This embodiment can be in need of making under the circumstances of through-silicon-via and pile together a plurality of chips, can not constitute harmful effects to the integrated circuit and the test of each chip, through piling up a plurality of chips slopes, can reduce the thickness of chip, and then reduce the holistic thickness of heap chip package structure, in order to reach high density 3D and pile up the purpose of encapsulation, can make again and play the balanced effect of mutual support between each chip, can reduce the local atress of each chip in the manufacturing process, protect the chip better

Example two

A manufacturing method of a stacked chip packaging structure comprises the following steps:

s1, fixing a plurality of insulating bases 3 on the first surface of the substrate 1 side by side respectively, and keeping the opening directions of the right-angle notches 4 consistent;

s2, respectively bonding a plurality of chips 5 in the right-angle notch 4 on the insulating base 3 one by one from the end of the right-angle notch 4 on the insulating base 3 facing the opening, and bonding an insulating layer 8 on the overlapping part of the previous chip 5 and the next chip 5 before bonding the next chip 5;

s3, electrically connecting the chips 5 with the substrate 1 through the metal bumps 6 by adopting a flip chip bonding technology;

s4, forming a package encapsulant 7 on the substrate 1, encapsulating the plurality of chips 5, the plurality of insulating bases 3, and the plurality of metal bumps 6, and filling gaps between the plurality of insulating bases 3;

s5, a plurality of solder balls 2 are formed on the second surface of the substrate 1.

The stacked chip packaging structure of the embodiment has the advantages of simple manufacturing process, low manufacturing cost and good heat dissipation effect, and can effectively improve the production efficiency and yield of the stacked chip packaging structure.

Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.