阅读说明：本技术 转向马达制动 (Steering motor brake ) 是由 蒂莫西·帕特里克·迪茨 布莱恩·鲁特科夫斯基 大卫·鲁特科夫斯基 于 2020-09-09 设计创作，主要内容包括：本公开提供了“转向马达制动”。本公开描述了一种用于使转向马达中的一个或多个绕组短路的方法。所述方法确定在电路处没有从处理器接收到信号。所述方法响应于电路没有从处理器接收到信号而对电路中的第一电容器放电。所述方法响应于对所述第一电容器放电而经由电阻器导通第一多个晶体管。所述方法响应于导通第一多个晶体管而导通第二多个晶体管。所述方法将来自第二多个晶体管的短路信号发送到转向马达。(The present disclosure provides a "steering motor brake". The present disclosure describes a method for short-circuiting one or more windings in a steering motor. The method determines that no signal is received at the circuit from the processor. The method discharges a first capacitor in a circuit in response to the circuit not receiving a signal from a processor. The method turns on a first plurality of transistors via a resistor in response to discharging the first capacitor. The method turns on the second plurality of transistors in response to turning on the first plurality of transistors. The method sends a short circuit signal from the second plurality of transistors to the steering motor.)

1. A method, comprising:

determining that a signal has not been received by the circuitry from the processor;

discharging a first capacitor in the circuit in response to the circuit not receiving the signal from the processor;

turning on a first plurality of transistors via a resistor in response to discharging the first capacitor;

turning on a second plurality of transistors in response to turning on the first plurality of transistors; and is

Sending a short circuit signal from the second plurality of transistors to a steering motor.

2. The method of claim 1, wherein the short circuit signal is a burst signal.

3. The method of claim 1, further comprising turning off a first transistor in response to the first capacitor discharging.

4. The method of claim 3, wherein the first transistor turns on the first plurality of transistors.

5. The method of claim 3, wherein the first transistor is turned on in response to the pulse train signal.

6. The method of claim 3, wherein the first transistor is turned on in response to a constant high signal.

7. The method of claim 1, further comprising applying a voltage from a supercapacitor to the second plurality of transistors.

8. The method of claim 1, further comprising applying a voltage from a battery to the second plurality of transistors.

9. The method of claim 1, wherein the second plurality of transistors comprises a first transistor, a second transistor, and a third transistor.

10. The method of claim 9, wherein the steering motor comprises:

a first phase, a second phase and a third phase, and

the first transistor is connected to the first phase, the second transistor is connected to the second phase, and the third transistor is connected to the third phase.

11. The method of claim 10, wherein responsive to the first transistor, the second transistor, and the third transistor being turned on, the first transistor causes the short circuit signal to be sent to the first phase, the second transistor causes the short circuit signal to be sent to the second phase, and the third transistor causes the short circuit signal to be sent to the third phase.

12. A system, comprising:

a circuit;

a processor;

a first capacitor that discharges in response to the circuit not receiving a signal from the processor;

a first plurality of transistors energized in response to discharging the first capacitor;

a second plurality of transistors activated in response to the first plurality of transistors being activated; and

a steering motor that receives a short circuit signal in response to the second plurality of transistors being energized.

13. The system of claim 12, wherein the short circuit signal is a burst signal.

14. The system of claim 12, further comprising turning off a first transistor in response to discharging the first capacitor.

15. The system of claim 14, wherein the first transistor causes the first plurality of transistors to be activated.

Technical Field

The present disclosure relates to a three-phase circuit for use in a vehicular environment. In some embodiments, the present disclosure utilizes a Field Effect Transistor (FET) circuit to short circuit windings in the steering motor, thereby enabling the rear wheels of the vehicle to straighten out after the vehicle turns, in order to reduce undesirable effects on vehicle control in the event of a steering motor failure.

Background

An electric motor used to steer a vehicle in an electric power steering system must have the ability to be disabled if the microprocessor in the electric motor fails. In particular in rear steering systems, it is desirable to brake the electric steering motor and have the return spring in the electric steering motor slowly bring the wheels into a straight orientation after the vehicle has completed a turn. Some systems use mechanical relays to short circuit windings in an electric steering motor using normally closed contacts. When the contacts are open, the electric steering motor is free to turn the wheels on the vehicle. However, when the relay is de-energized and the contacts are closed, the electric steering motor cannot steer the wheels on the vehicle, and therefore the windings that control the mobility of the wheels are disabled. The mechanical relay overrides any motor control transistors in the electric steering motor and provides a braking function such that the wheels move to a straightened position under the influence of a centering spring in the electric steering motor. However, one notable problem with mechanical relays is the movement of the contacts as the vehicle moves, causing them to bounce. Another problem is the ability of the contacts to arc, the life of the contacts, and the sensitivity to vibration and shock.

Disclosure of Invention

The present disclosure describes a method for short-circuiting one or more windings in a steering motor. The method determines that no signal is received at the circuit from the processor. The method discharges a first capacitor in a circuit in response to the circuit not receiving a signal from a processor. The method turns on a first plurality of transistors via a resistor in response to discharging the first capacitor. The method turns on the second plurality of transistors in response to turning on the first plurality of transistors. The method sends a short circuit signal from the second plurality of transistors to the steering motor.

Drawings

The embodiments are explained with reference to the drawings. The use of the same reference numbers may indicate similar or identical items. Various embodiments may utilize elements and/or components other than those shown in the figures, and some elements and/or components may not be present in various embodiments. Elements and/or components in the drawings have not necessarily been drawn to scale. Throughout this disclosure, singular and plural terms are used interchangeably, depending on the context.

FIG. 1 depicts an exemplary vehicle and steering components of an electronic power steering system according to the present disclosure.

Fig. 2 depicts an exemplary steering motor braking circuit according to the present disclosure.

Fig. 3 depicts an exemplary steering motor braking circuit according to the present disclosure.

FIG. 4 is a flow chart of an example method of braking a steering motor according to the present disclosure.

FIG. 5 is a flow chart of an example method of braking a steering motor according to the present disclosure.

Detailed Description

SUMMARY

Electric Power Steering (EPS) is an important high power load. Electrification of the steering system has resulted in a significant increase in the efficiency of motor vehicles. Depending on the vehicle class, an electric power steering system may consume more than 90% less energy than a hydraulic servo steering system. Electrification reduces the average power requirements because permanently operating hydraulic pumps are not required. EPS systems only consume energy during operation. This can reduce fuel on motorways by as much as 0.4 litres per hundred kilometres, whilst in urban traffic the fuel is reduced by as much as 0.8 litres per hundred kilometres.

Other advantages of EPS systems are increased safety functions, greater comfort, and less maintenance (no hydraulic oil system) compared to conventional hydraulic servo steering systems. The EPS system allows additional functions to be implemented. For example, EPS systems may assist a driver in emergency driving situations, such as corrective steering measures during parking and on the highway. The EPS also makes automatic parking possible. In conventional hydraulic servo steering systems, the hydraulic oil requires routine maintenance. This is not necessary in the case of EPS systems, which leads to reduced maintenance costs.

The systems and methods described herein relate to using a normally closed Field Effect Transistor (FET) circuit in an EPS system in place of one or more circuits of a mechanical relay used in conventional post-EPS systems. The one or more circuits maintain a constant transistor bias under all conditions including power loss. One or more circuits use energy storage devices in the form of super capacitors that store electrical energy and battery storage technology. The non-volatile storage device is also combined with one or more circuits to indicate that the system is in a safe mode and that an override of the motor drive control inverter is not required.

In one embodiment, the EPS may include a circuit composed of a plurality of circuit components. The components include transistors, capacitors, resistors, one or more power supplies to power different parts of the circuit, a processor, non-volatile memory, a three-phase inverter, and a three-phase steering motor. The three-phase steering motor may comprise three windings arranged in a delta connection, but in some embodiments they may be arranged in a wye connection. The circuit may further comprise a charge pump. The circuit may connect each of the three transistors to one of the windings in the three-phase steering motor. When the transistors are energized, they may short all windings in response to the processor not receiving a valid signal from the three-phase inverter.

In another embodiment, the EPS may include a circuit composed of a plurality of circuit components. The components include transistors, capacitors, resistors, one or more power supplies to power different parts of the circuit, a processor, non-volatile memory, a three-phase inverter, and a three-phase steering motor. The three-phase steering motor may comprise three windings arranged in a delta connection, but in some embodiments they may be arranged in a wye connection. The circuit may further comprise a charge pump. The circuit may connect each of the two transistors to one of the windings of the three-phase steering motor. When the transistors are energized, they may short circuit only two of the windings in response to the processor not receiving a signal from the three-phase inverter.

Illustrative embodiments

FIG. 1 depicts an exemplary vehicle 140 and a power steering control module 150, which may be located near or on a rear axle of the exemplary vehicle 140. When the processor 151 stops receiving signals from the steering control circuit 153, the power steering control module 150 may be responsible for braking the power steering electric motor 170. The processor 151 may perform the same functions as those generally described with reference to processors throughout this application. That is, the processor may execute the blocks in fig. 3 and 4. Memory 152 stores instructions that are executed by processor 151 to cause the steering motor braking circuit to perform the actions disclosed herein. When referring to operations performed by the power steering control module 150, it will be understood that this includes execution of instructions by the processor 151.

Steering control circuit 153 may be implemented in one of two embodiments. In the first embodiment, the steering control circuit 153 may be implemented at least partially based on the steering motor brake circuit 200. In a second embodiment, steering control circuit 153 may be implemented based at least in part on steering motor braking circuit 300. The battery 154 may be a power source that may power the power steering control circuit 153, and the capacitor 155 may be a power source that also powers the power steering control circuit 153. In some embodiments, the battery 154 may be isolated to power the power steering control circuit 153. In some embodiments, the capacitor 155 may be isolated to power the power steering control circuit 153. However, in other embodiments, both the battery 154 and the capacitor 155 may power the power steering control circuit 153. In the first embodiment, the battery 154 may be implemented as the battery 235b, and may be implemented as the energy storage device 321. In the second embodiment, the capacitor 155 may be implemented as the supercapacitor 235a, and may be implemented as the energy storage device 321.

Fig. 2 depicts an exemplary steering motor braking circuit 200 according to the present disclosure. Steering motor braking circuit 200 may include one or more resistors, capacitors, transistors, power supplies, charge pumps, diodes, non-volatile memory, ultracapacitors, and a steering motor. Resistors, capacitors, transistors, power supplies, charge pumps, diodes, non-volatile memory, supercapacitors may be arranged in a particular manner to be implemented in a microprocessor (for exampleE.g., μ P207) fails to pass through a three-phase inverter (e.g.,inverter 205) stops or brakes steering motor 215 when an active signal is provided to steering motor 215. μ P207 is functionally identical to processor 151. VB 201 is towardsThe battery voltage supplied by the inverter 205. Supplied from VB 201The power of the inverter 205 is such thatThe inverter 205 can control the windings 215a, 215b, and 215c of the steering motor 215. The steering motor 215 may be a motor having three phases. In some embodiments, the steering motor 215 may not be a three-phase motor. PS REG 203 is a power supply regulator that regulates power from VB 201 toPower supply of the inverter 205. VB 201 may be a Direct Current (DC) power supply and PS REG 203 may control or regulate the application toPower of inverter 205. For example, PS REG 203 may increase or decrease the supply toThe power of the inverter 205, which in turn will control the magnitude, frequency and phase of the current and/or voltage applied to the windings 215a, 215b and 215 c. These windings may also be referred to as phases. Can be supplied according to the driving adjustment of the operatorPower of inverter 205. For example, the PS REG 203 may limit or increase the power demand to the steering motor 215 based onPower to the inverter 205 in response to the driver's steering of the vehicle. μ P207 may be oriented towardsThe inverter 205 provides a control signal, which may controlOperation of inverter 205. For example, μ P207 may be oriented towardsInverter 205 sends one or more signals that may causeThe inverter 205 changes the amount of current or voltage applied to any one of the three phases of the steering motor 215 in response to the driver turning the steering column of the vehicle.The inverter 205 may also send a signal to the μ P207 to indicate that it is still responsive to instructions or commands sent to it from the μ P207.The inverter 205 may send a periodic signal to the μ P207 to indicate that it is still operating properly.

If μ P207 receives a valid signal from the inverter and μ P207 is operating within established specifications, it sends a periodic signal as a burst 247 or a status signal 249 to transistor Q8; it also writes signals to non-volatile memory (NVM) 229. Signal 247 or 249 keeps transistor Q8 conductive and the signal in NVM 229 does not enable charge pump 225. In some embodiments, VBX 2223 may be 24 volts. The voltage may be higher than the voltage applied to the motor windings to drive transistors Q1209, Q2211, and Q3213. CP 225 may be powered by a super capacitor (super capacitor 235a) charged to a voltage Vb. The super capacitor 235a may be the primary power source for conserving battery energy. If the voltage generated by the super capacitor 235a is lower than the available power stored in the battery 235b, the battery 235a will power the CP 225. The battery 235b can be charged by VB 233. 24 volts ensures that transistors Q1209, Q2211, and Q3213 will be turned on. Super capacitor 235a may be charged with power supply VB 233. VB 233 may be a DC power supply.

Transistors Q1209, Q2211, and Q3213 may short circuit windings 215a, 215b, and/or 215 c. Transistors Q1209, Q2211, and Q3213 are driven by transistors Q4217, Q5219, and Q6221. Resistor R1237 turns on transistors Q4217, Q5219, and Q6221 by biasing their gate-sources with a negative voltage. Accordingly, the transistors Q4217, Q5219, and Q6221 turn on the transistors Q1209, Q2211, and Q3213. When transistors Q1209, Q2211, and Q3213 are turned on, the windings 215a, 215b, and 215c are shorted, and the steering motor 215 is disabled, thereby allowing the wheels of the vehicle (not shown) to straighten after the operator of the vehicle turns a corner. In some embodiments, windings 215a, 215b, and 215c are not shorted when transistors Q7239 and Q8241 are energized or conducting. Transistors Q7239 and Q8241 are normally activated (turned on) in response to either the μ P207 application pulse train 247 or the status signal 249. If the pulse train 247 or the status signal 249 is interrupted, the transistor Q8, and therefore the transistor Q9, will de-energize (turn off), and the motor braking transistor will be energized.

If the steering system is active, μ P207 disables the shorting FETs (i.e., transistors Q1209, Q2211, and Q3213) in response to the pulse train 247 at Q8241. The Q8241 may be turned on based at least in part on the high level signal 249 or by the pulse train 247. If the μ P207 stops sending the high signal 249 and the steering motor 215 is active, the shorting FET can turn on and cause the steering motor to turn onThe inverter 205 is short circuited, which will in turn brake the steering motor 215. The pulse train 247 holds the capacitor C1245 charged and the high-level signal holding transistor Q8241 is turned on. If pulse train 247 is stopped, electricity is suppliedCapacitor C1245 discharges and transistor Q8241 turns off and the shorting FET turns on. μ P207 will write a high level signal (digital 1) to NVM 229. The high level signal causes the energy storage device supercapacitor 235a and battery 235b to supply power to the CP 225. If either signal 247 or 249 is stopped, NVM 229 provides power to the shorting FET.

During normal vehicle shutdown, μ P207 will first write a low signal to NVM 229 to disable circuit steering motor braking circuit 200 and the depletion of the energy stored in supercapacitor 235 a. When the operator turns on the ignition switch, the μ P207 may stop sending the high signal 249 to perform a diagnostic check on the shorting FET, thereby ensuring that when the steering motor 215 is shorted,the transistors in the inverter 205 are driven into the steering motor 215. The μ P207 may also monitor the energy in the super capacitor 235a and battery 235b, as well as the voltage generated by the CP 225.

Fig. 3 depicts an exemplary steering motor braking circuit according to the present disclosure. During normal operation, the microprocessor 309 is powered viaThe inverter 305 controls a steering motor 315. The microprocessor 309 is functionally identical to the processor 151. During a fault condition (i.e., microprocessor 309 failure), it may be necessary to independently disable the motor drive associated with the steering motor 315 with a fault protection circuit to force the steering motor 315 to brake and gradually return to a neutral position consistent with a return spring in the gear train.

Two transistors (Q1333 and Q2335) may be placed across two of the steering motor 315 phases (phases 315a and 315b, respectively) to short the motor leads and the brake steering motor 315. Q1333 and Q2335 are sized sufficiently to overwhelm the transistors in 3 inverter 305. To ensure that Q1333 and Q2335 are on, the voltage driving the gate on each of Q1333 and Q2335 must be greater than the voltage on the motor phase to which they are connected (which may be VB (battery voltage), respectively, phases 315a and 315 b). To is coming toThis can be accomplished using a voltage multiplier called a charge pump (charge pump 331) to produce a voltage twice that produced by a battery (not shown). The voltage generated by the battery is V_b323 and the voltage generated by the charge pump 331 is V_CP 341＝V_b323x 2. An energy source such as a supercapacitor (similar to supercapacitor 335a) may be used to power the charge pump 331. In some embodiments, a rechargeable battery may be used in place of the supercapacitor. The rechargeable battery may be similar to battery 335 b. To prevent static discharge of the energy source, the energy source may be disconnected by Q7329 when the vehicle is not receiving power from the battery that starts the vehicle. A non-volatile memory unit (NVM 319) may be used to store the enable/clear status (enable/clear 317) of the microprocessor 309 during possible failures of the microprocessor 309 so that the charge pump 331 continues to receive power. The microprocessor 309 may send periodic diagnostic signals to the monitor mode timer unit 311. The diagnostic signal indicates that the microprocessor 309 is functioning properly. These diagnostic signals may bias R1343, which in turn may turn off or disable Q1333 and Q2335. In the event that the microprocessor 309 fails and stops sending these diagnostic signals to the monitor mode timer unit 311, Q3337 and Q4339 will be biased by R1343, which in turn causes Q1333 and Q2335 to be enabled or conducting.

In some embodiments, a dedicated small microprocessor may be used that includes a monitor diagnostic function between the microprocessor 309 and the monitor mode timer unit 311, as well as an enable/clear function. In the described embodiment, the small microprocessor may communicate with the main microprocessor to determine what state Q1333 and Q2335 are in (i.e., on or off/enabled or disabled). Q1333 and Q2335 may be referred to as brake FETs. Resistor R1343 forms a voltage divider if transistor Q5315 is off, with the resistor connected to transistors Q3337 and Q4334 and Vcp 341 to form a negative gate-to-source voltage (Vgs) for transistors Q3337 and Q4334. Negative Vgs will energize (turn on) a P-channel FET such as transistors Q3337 and Q4334. If transistor Q5315 is on, voltage Vcp 341 is applied to resistor R1343, which will turn off transistors Q3337 and Q4334.

FIG. 4 is a flow chart of an example method of braking a steering motor according to the present disclosure. The method may begin at block 402, where a power steering control circuit (e.g., power steering control circuit 153) may write a binary digit (e.g., "1" or "0") to a memory (e.g., NVM 229). At block 404, the method may determine whether it is still receiving a signal from a processor (e.g., μ P207). The signal may be a pulse train, such as pulse train 247, and the circuit element receiving the signal is a capacitor, such as capacitor C1245. The pulse train 247 may keep the capacitor C1245 charged to a certain potential or voltage. If the capacitor C1245 remains charged, the method may return to block 404 (YES). When capacitor C1245 remains charged, transistor Q8241 will be turned on and/or remain turned on. In some embodiments, a constant high level signal replaces the on-off keying pulse train 247 signal.

If capacitor C1245 does not receive the burst 247 from the processor μ P207, the method may proceed to block 406 (NO). At block 406, the first capacitor (e.g., capacitor C1245) may be discharged and the method may proceed to block 408. At block 408, the method may turn on a first plurality of transistors via a resistor. The first plurality of transistors may be transistors Q4217, Q5219, and Q6221. When capacitor C1245 discharges, transistor Q8241 will turn off, allowing current to flow to transistors Q4217, Q5219, and Q6221, turning on transistors Q4217, Q5219, and Q6221.

At block 410, the method may turn on a second plurality of transistors. The second plurality of transistors may be transistors Q1209, Q2211, and Q3213. After the transistors Q4217, Q5219, and Q6221 are turned on, the transistors Q1209, Q2211, and Q3213 (short-circuit FETs) will also be turned on. At block 412, the method may send a short circuit signal to the steering motor. After the transistors Q1209, Q2211, and Q3213 are turned on, the shorting FET may short circuit the windings 215a, 215b, and 215c of the steer motor 215.

FIG. 5 is a flow chart of an example method of braking a steering motor according to the present disclosure. The method may begin at block 502, where a power steering control circuit (e.g., power steering control circuit 153) may write a binary digit (e.g., "1" or "0") to a memory (e.g., NVM 319). At block 504, the method may determine whether it is still receiving a signal from a processor (e.g., microprocessor 309). If the power steering control circuit continues to receive signals from the microprocessor 309, the method may return to block 504. More specifically, if the monitor circuit 311 continues to receive signals from the microprocessor 309, the method may return to block 504. If the monitor circuit 311 continues to receive signals from the microprocessor 309, the monitor circuit 311 may output a high voltage (e.g., 5 volts) signal to keep the transistor Q6313 conductive, which in turn may keep the transistor Q5315 conductive. When the transistor Q5315 is on, it provides a positive voltage to R1343 to keep the transistors Q1333, Q2335, Q3337, and Q4339 off.

If the power steering control circuit is not continuing to receive signals from the microprocessor 309, the method may proceed to block 506, at block 506, the transistor Q6313 may be turned off, which in turn may turn off the transistor Q5315 at block 508. More specifically, if the monitor circuit 311 does not receive an appropriate signal, the transistor Q6313 may be turned off and the transistor Q6313 may turn off the transistor Q5315. If the monitor circuit 311 does not receive the OK signal, at block 510, the transistors Q6313 and Q5315 will be off, and the transistors Q1333, Q2335, Q3337 and Q4339 will be on. After the transistors Q1333, Q2335, Q3337, and Q4339 are turned on, they may short circuit the steering motor 395 at block 512.

In the foregoing disclosure, reference has been made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. It is to be understood that other implementations may be utilized and structural changes may be made without departing from the scope of the present disclosure. References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Implementations of the systems, apparatus, devices, and methods disclosed herein may include or utilize a special purpose or general-purpose computer including computer hardware, such as, for example, one or more processors and system memory, as discussed herein. Implementations within the scope of the present disclosure may also include physical and other computer-readable media for carrying or storing computer-executable instructions and/or data structures. Such computer-readable media can be any available media that can be accessed by a general purpose or special purpose computer system. Computer-readable media storing computer-executable instructions are computer storage media (devices). Computer-readable media carrying computer-executable instructions are transmission media. Thus, by way of example, and not limitation, implementations of the present disclosure can include at least two distinct computer-readable media: computer storage media (devices) and transmission media.

Computer storage media (devices) include RAM, ROM, EEPROM, CD-ROM, Solid State Drives (SSDs) (e.g., based on RAM), flash memory, Phase Change Memory (PCM), other types of memory, other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store desired program code means in the form of computer-executable instructions or data structures and which can be accessed by a general purpose or special purpose computer.

Implementations of the apparatus, systems, and methods disclosed herein may communicate over a computer network. A "network" is defined as one or more data links that enable the transfer of electronic data between computer systems and/or modules and/or other electronic devices. When information is transferred or provided over a network or another communications connection (either hardwired, wireless, or any combination of hardwired or wireless) to a computer, the computer properly views the connection as a transmission medium. Transmission media can include a network and/or data links which can be used to carry desired program code means in the form of computer-executable instructions or data structures and which can be accessed by a general purpose or special purpose computer. Combinations of the above should also be included within the scope of computer-readable media.

Computer-executable instructions comprise, for example, instructions and data which, when executed at a processor, cause a general purpose computer, special purpose computer, or special purpose processing device to perform a certain function or group of functions. The computer-executable instructions may be, for example, binary code, intermediate format instructions (such as assembly language), or even source code. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the features or acts described above. Rather, the described features and acts are disclosed as example forms of implementing the claims.

Those skilled in the art will appreciate that the disclosure may be practiced in network computing environments with many types of computer system configurations, including internal vehicle computers, personal computers, desktop computers, laptop computers, message processors, hand-held devices, multi-processor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, mobile telephones, PDAs, tablet computers, pagers, routers, switches, various storage devices, and the like. The present disclosure may also be practiced in distributed system environments where local and remote computer systems, which are linked (either by hardwired data links, wireless data links, or by any combination of hardwired and wireless data links) through a network, both perform tasks. In a distributed system environment, program modules may be located in both local and remote memory storage devices.

Further, where appropriate, the functions described herein may be performed in one or more of the following: hardware, software, firmware, digital components, or analog components. For example, one or more Application Specific Integrated Circuits (ASICs) may be programmed to perform one or more of the systems and procedures described herein. Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, components may be referred to by different names. This document does not intend to distinguish between components that differ in name but not function.

It should be noted that the sensor embodiments discussed above may include computer hardware, software, firmware, or any combination thereof to perform at least a portion of their functions. For example, the sensors may include computer code configured to be executed in one or more processors, and may include hardware logic/circuitry controlled by the computer code. These exemplary devices are provided herein for illustrative purposes and are not intended to be limiting. As will be appreciated by one skilled in the relevant art, embodiments of the present disclosure may be implemented in additional types of devices.

At least some embodiments of the present disclosure are directed to computer program products comprising such logic (e.g., in the form of software) stored on any computer-usable medium. Such software, when executed in one or more data processing devices, causes the devices to operate as described herein.

While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents. The foregoing description has been presented for purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. Further, it should be noted that any or all of the foregoing alternative implementations may be used in any desired combination to form additional hybrid implementations of the present disclosure. For example, any function described with respect to a particular device or component may be performed by another device or component. Further, although particular device features have been described, embodiments of the present disclosure may be directed to many other device features. Furthermore, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the disclosure is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as illustrative forms of implementing the embodiments. Conditional language, such as "can," "might," or "may," among others, is generally intended to convey that certain embodiments may include certain features, elements, and/or steps, while other embodiments may not include certain features, elements, and/or steps, unless expressly specified otherwise or understood otherwise in the context of such use. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more embodiments.

According to one embodiment, the first transistor is activated in response to a pulse train signal.

According to one embodiment, the first transistor is turned on in response to a constant high level signal.

According to one embodiment, the invention also features a supercapacitor applying a voltage to the second plurality of transistors.

According to one embodiment, the invention also features a battery that applies a voltage to the second plurality of transistors.

According to one embodiment, the second plurality of transistors includes a first transistor, a second transistor, and a third transistor, and the steering motor includes a first phase, a second phase, and a third phase, and the first transistor is connected to the first phase, the second transistor is connected to the second phase, and the third transistor is connected to the third phase.