阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 丸井俊治 林哲也 沼仓启一郎 倪威 田中亮太 竹本圭佑 于 2018-07-27 设计创作，主要内容包括：本发明提供一种半导体装置及其制造方法。该半导体装置具有：基板(10)、配置在基板(10)的主面的半导体层(20)、以及经由半导体层(20)而在基板(10)之上分离而配置且在导通状态下作为流动的主电流的电流通路的各端部的第一主电极(30)及第二主电极(40),半导体层(20)具有：在主电流流动的第一导电型漂移区(21)、在漂移区(21)的内部配置并与电流通路平行延伸的第二导电型柱区(22)、以及在漂移区(21)与柱区(22)之间的至少一部分配置且杂质浓度比相同导电型的邻接区域低的低浓度区或非掺杂区的任一区即电场缓和区(23)。(The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes: the semiconductor device includes a substrate (10), a semiconductor layer (20) disposed on a main surface of the substrate (10), and a first main electrode (30) and a second main electrode (40) which are disposed separately on the substrate (10) via the semiconductor layer (20) and which serve as respective ends of a current path through which a main current flows in an on state, wherein the semiconductor layer (20) includes: the drift region (21) of a first conductivity type in which a main current flows, a column region (22) of a second conductivity type which is arranged inside the drift region (21) and extends parallel to a current path, and an electric field alleviation region (23) which is either a low concentration region or a non-doped region which is arranged at least partially between the drift region (21) and the column region (22) and has a lower impurity concentration than an adjacent region of the same conductivity type.)

1. A semiconductor device is characterized by comprising:

a substrate;

a semiconductor layer disposed on a main surface of the substrate;

a first main electrode and a second main electrode which are arranged on the substrate so as to be separated from each other through the semiconductor layer and which are each end portions of a current path of a main current flowing in an on state;

the semiconductor layer has:

a drift region of a first conductivity type in which the main current flows;

a second conductive type column region arranged inside the drift region and extending parallel to the current path;

and an electric field alleviation region which is disposed at least partially between the drift region and the column region, and which is either a low concentration region or a non-doped region having an impurity concentration lower than that of an adjacent region of the same conductivity type.

2. The semiconductor device according to claim 1,

the electric field alleviation region is disposed on a side surface of the column region that faces the second main electrode.

3. The semiconductor device according to claim 1 or 2,

the electric field alleviation region is disposed on a side surface of the column region that is parallel to the current path and faces the drift region.

4. The semiconductor device according to any one of claims 1 to 3,

in an off state where the main current is cut off, impurity concentrations of the drift region and the column region are set so that the drift region and the column region are depleted by a depletion layer generated between the drift region and the column region.

5. The semiconductor device according to any one of claims 1 to 4,

the electric field alleviation region reaches the substrate.

6. The semiconductor device according to any one of claims 1 to 5,

the semiconductor layer has a second conductivity type well region disposed between the drift region and the pillar region and the first main electrode.

7. The semiconductor device according to claim 6,

the semiconductor layer has a first conductive type source region disposed between the well region and the first main electrode and electrically connected to the first main electrode,

further comprising a control electrode embedded in the semiconductor layer so as to face the drift region, the well region, and the source region via an insulating film,

operating as a transistor for controlling the main current by the control electrode.

8. The semiconductor device according to any one of claims 1 to 7,

the drift region includes a first main electrode and a second main electrode, and the first main electrode and the second main electrode are electrically connected to each other.

9. The semiconductor device according to any one of claims 1 to 8,

the drift region and the column region are alternately arranged on a side surface of a groove formed in the substrate along a surface normal direction of the side surface of the groove.

10. The semiconductor device according to any one of claims 1 to 8,

the drift regions and the column regions are alternately arranged along the thickness direction of the substrate.

11. The semiconductor device according to any one of claims 1 to 10,

the semiconductor layer is formed of a wide bandgap semiconductor.

12. The semiconductor device according to any one of claims 1 to 11,

each region of the semiconductor layer is formed of the same material.

13. The semiconductor device according to any one of claims 1 to 12,

the substrate is a semi-insulating substrate or an insulating substrate.

14. The semiconductor device according to any one of claims 1 to 12,

the substrate is a silicon carbide substrate.

15. A method for manufacturing a semiconductor device, comprising:

forming a first conductivity type drift region on a main surface of a substrate;

forming a second conductive type column region extending in parallel to the drift region in the drift region to form an electric field alleviation region, which is either a low concentration region or a non-doped region having an impurity concentration lower than that of an adjacent region of the same conductivity type, in at least a part of a region between the second conductive type column region and the drift region;

a step of separating a first main electrode and a second main electrode facing each other via the drift region and the column region on the substrate along an extending direction of the drift region;

and forming the drift region and the column region by ion-implanting impurities into the substrate.

Technical Field

The invention relates to a semiconductor device and a method for manufacturing the same.

Background

In order to realize a high withstand voltage and a low on-resistance, a semiconductor device of a Super Junction (SJ) structure in which an n-type drift region and a p-type column region are alternately arranged and pn junctions are periodically formed has been developed (see patent document 1). In the semiconductor device having the SJ structure, even if the on-resistance is reduced by increasing the concentration of the n-type impurity in the drift region through which the main current flows, the drift region is depleted by the depletion layer extending from the pn junction during reverse bias, and therefore, the breakdown voltage can be maintained high.

Documents of the prior art

Patent document

Patent document 1: japanese unexamined patent application publication No. 2002-319680

Disclosure of Invention

Technical problem to be solved by the invention

However, since an electric field is concentrated at the boundary between the drift region and the column region at the time of reverse bias, there is a problem that the withstand voltage of the semiconductor device is lowered.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having a super junction structure and capable of suppressing a reduction in withstand voltage, and a method for manufacturing the semiconductor device.

Technical solution for solving technical problem

The gist of the semiconductor device according to one embodiment of the present invention is that at least a part of a space between a drift region and a column region constituting a super junction structure has an electric field relaxing region which is either a low concentration region or an undoped region having an impurity concentration lower than that of an adjacent region of the same conductivity type.

A method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a drift region and a column region by ion-implanting an impurity into a substrate, and forming an electric field relaxing region, which is either a low concentration region or a non-doped region having an impurity concentration lower than that of an adjacent region of the same conductivity type, in at least a part between the drift region and the column region.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, a semiconductor device having a super junction structure and capable of suppressing a reduction in withstand voltage and a method for manufacturing the semiconductor device can be provided.

Drawings

Fig. 1 is a schematic perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a plan view showing an example model for calculating the electric field intensity.

Fig. 3 is a plan view showing a model of a comparative example for calculating an electric field strength.

Fig. 4 is a graph showing the calculation result of the electric field strength.

Fig. 5 is a graph showing the calculation result of the electric field strength.

Fig. 6 is a graph showing the calculation result of the electric field strength.

Fig. 7 is a perspective view (one of) illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

Fig. 8 is a perspective view (two) for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 9 is a perspective view (iii) for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 10 is a perspective view (fourth) for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 11 is a perspective view (fifthly) for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 12 is a perspective view (sixteenth) for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment of the present invention.

Fig. 14 is a schematic perspective view showing the structure of a semiconductor device according to a second embodiment of the present invention.

Fig. 15 is a perspective view (one of) illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 16 is a perspective view (two) for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 17 is a perspective view (iii) for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 18 is a perspective view (fourth) for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 19 is a perspective view (fifthly) for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 20 is a perspective view (sixth) for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 21 is a perspective view (seventeenth) for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 22 is a schematic perspective view showing the structure of a semiconductor device according to a third embodiment of the present invention.

Fig. 23 is a schematic perspective view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

Fig. 24 is a schematic perspective view showing another structure of a semiconductor device according to a fourth embodiment of the present invention.

Detailed Description

The following describes embodiments with reference to the drawings. In the description of the drawings, the same reference numerals are used for the same portions, and the description is omitted. However, the drawings are schematic, and the relationship of the thickness to the planar size, the ratio of the thicknesses of the respective layers, and the like include portions different from the actual ones. In addition, the drawings also include portions having different dimensional relationships and ratios from each other.

(first embodiment)

As shown in fig. 1, a semiconductor device according to a first embodiment of the present invention includes: the semiconductor device includes a substrate 10, a semiconductor layer 20 disposed on a main surface of the substrate 10, and a first main electrode 30 and a second main electrode 40 disposed above the substrate 10 so as to be separated from each other through the semiconductor layer 20. The first main electrode 30 and the second main electrode 40 are ends of a current path of a main current flowing through the semiconductor device in an on state.

The semiconductor layer 20 has: a drift region 21 of a first conductivity type through which a main current flows, a column region 22 of a second conductivity type arranged inside the drift region 21, and an electric field alleviation region 23 arranged at least partially between the drift region 21 and the column region 22. The column regions 22 extend parallel to the current path, and the drift region 21 and the column regions 22 form an SJ structure. The electric field relaxation region 23 is a low concentration region having an impurity concentration lower than that of an adjacent region having the same conductivity type or a non-doped region intentionally not doped with impurities. In the semiconductor device shown in fig. 1, the electric field alleviation region 23 is disposed in contact with the side surface of the column region 22 that faces the second main electrode 40 and the side surface of the column region 22 that is parallel to the current path and faces the drift region 21.

The first conductivity type and the second conductivity type are opposite conductivity types. That is, when the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type. In the following, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described.

The semiconductor layer 20 shown in fig. 1 further has: a second conductive type well region 24 disposed between the end portions of the drift region 21 and the column region 22 and the first main electrode 30, and a first conductive type source region 25 disposed between the well region 24 and the first main electrode 30. The well region 24 is connected to the drift region 21 and the pillar region 22, and the source region 25 is electrically connected to the first main electrode 30.

The semiconductor device shown in fig. 1 further includes a control electrode 50 embedded in the semiconductor layer 20 so as to face the drift region 21, the well region 24, and the source region 25 via the gate insulating film 60. The semiconductor device of the first embodiment operates as a transistor in which a main current is controlled by the control electrode 50. That is, the semiconductor device shown in fig. 1 is a MOSFET in which the first main electrode 30 is a source electrode, the second main electrode 40 is a drain electrode, and the control electrode 50 is a gate electrode. The first main electrode 30 is in ohmic contact with the source region 25 and the second main electrode 40 is in ohmic contact with the drift region 21.

A plurality of gate trenches having openings formed across the upper surfaces of the source region 25, the pillar region 22, and the well region 24 reach the substrate 10. A gate insulating film 60 is disposed on the inner wall surface of the gate trench, and a control electrode 50 is disposed inside the gate trench and surrounded by the gate insulating film 60. Between the gate trenches, the drift region 21 is connected to a well region 24, and the well region 24 is connected to a source region 25. Further, at the time of the on operation, an inversion layer is formed in the channel region in contact with the gate insulating film 60 of the well region 24.

The semiconductor device shown in fig. 1 has an SJ structure in which a plurality of drift regions 21 and a plurality of column regions 22 are alternately arranged in a direction perpendicular to a current path. Therefore, when a reverse voltage is applied (reverse bias), the drift region 21 and the column region 22 are depleted due to a depletion layer extending from the pn junction formed at the interface of the drift region 21 and the column region 22. Therefore, a high withstand voltage can be obtained for the semiconductor device.

In the semiconductor device shown in fig. 1, an electric field alleviation region 23 is arranged between the drift region 21 and the column region 22. In the case where the electric field alleviation region 23 is not an undoped region, the electric field alleviation region 23 has the same conductivity type as either of the adjacent drift region 21 and column region 22, but the impurity concentration of the electric field alleviation region 23 is lower than that of the same conductivity type region. That is, when the electric field alleviation region 23 is of the first conductivity type, the impurity concentration of the electric field alleviation region 23 is lower than the impurity concentration of the drift region 21. On the other hand, when the electric field alleviation region 23 is of the second conductivity type, the impurity concentration of the electric field alleviation region 23 is lower than the impurity concentration of the column region 22. Thereby, the electric field concentration in the boundary region where the drift region 21 and the column region 22 face each other is relaxed by the electric field relaxing region 23. The width of the electric field alleviation region 23 is, for example, about 0.1 μm to about 0.3 μm.

When the drift region 21 is n-type and the electric field alleviation region 23 is p-type, the impurity concentration of the electric field alleviation region 23 may be higher than that of the drift region 21. In addition, when the column region 22 is p-type and the electric field relaxation region 23 is n-type, the impurity concentration of the electric field relaxation region 23 may be higher than that of the column region 22.

Next, a description is given of a basic operation of the semiconductor device shown in fig. 1.

In the on operation, the potential of the control electrode 50 is controlled in a state where a positive potential is applied to the second main electrode 40 with reference to the potential of the first main electrode 30, whereby the semiconductor device operates as a transistor. That is, when the voltage between the control electrode 50 and the first main electrode 30 is equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 24 on the side surface of the control electrode 50. Thereby, the semiconductor device is in an on state, and a main current flows between the first main electrode 30 and the second main electrode 40.

On the other hand, in the off operation, the voltage between the control electrode 50 and the first main electrode 30 is made to be a predetermined threshold voltage or less. This causes the inversion layer to disappear, and the main current is cut off.

In the off state, when the depletion layer expands from the interface between the drift region 21 and the column region 22 and the reverse voltage increases to a certain extent, the drift region 21 and the column region 22 are pinched off. Accordingly, the electric field intensity of the drift region 21 and the column region 22 is uniformly distributed in a rectangular shape, and the maximum electric field applied to the semiconductor device is greatly reduced. This improves the withstand voltage of the semiconductor device.

In order to fully deplete the SJ structure in the off state and obtain a high breakdown voltage, it is necessary to set the ratio of the total amount of n-type impurities in the n-type semiconductor region to the total amount of p-type impurities in the p-type semiconductor region to around 1. Therefore, the concentration Nd of the n-type impurity of the drift region 21, the concentration Na of the p-type impurity of the column region 22, the width Wn of the drift region 21, and the width Wp of the column region 22 satisfy the following formula (1):

Na×Wp＝Nd×Wn…(1)

the widths Wn and Wp are widths in a direction in which the drift regions 21 and the column regions 22 are alternately arranged.

By setting the impurity concentrations of the drift region 21 and the column region 22 so as to satisfy expression (1), the drift region 21 and the column region 22 are depleted by a depletion layer extending from the pn junction, and a high withstand voltage is obtained. At the same time, the resistance value of the drift region 21 can be suppressed.

However, the electric field is easily concentrated at the pn junction at the interface between the drift region 21 and the column region 22 in the reverse bias. This is because the relationship of expression (1) does not hold in the region close to the pn junction, and the n-type semiconductor region and the p-type semiconductor region do not achieve charge balance. When an electric field is concentrated at the pn junction, the withstand voltage of the semiconductor device is lowered.

In contrast, in the semiconductor device shown in fig. 1, the electric field concentration is reduced by disposing the electric field reduction region 23 between the drift region 21 and the column region 22. Next, the effect of reducing the electric field concentration by the electric field alleviation region 23 will be described with reference to the models shown in fig. 2 and 3, respectively.

The model shown in fig. 2 is an example model in which the electric field alleviation region 23 is arranged between the drift region 21 and the column region 22, as in the semiconductor device shown in fig. 1. On the other hand, the model shown in fig. 3 is a comparative example model in which the electric field alleviation region 23 is not arranged. The electric field alleviation region 23 is an undoped region.

Fig. 4 and 5 show the results of calculation of the electric field intensity along the center line M passing through the vicinity of the center in the width direction of the pillar region 22 in the example model shown in fig. 2 and the comparative example model shown in fig. 3. In fig. 4 and 5, the characteristic E1 of the solid line indicates the electric field intensity of the example model, and the characteristic E2 of the broken line indicates the electric field intensity of the comparative example model. The position a is a position where the well region 24 is connected to the pillar region 22, the position B is a position on the side of the pillar region 22 opposite to the second main electrode 40, and the position C is a position where the drift region 21 is connected to the second main electrode 40.

Fig. 4 shows the calculation result of the electric field intensity at the surface of the semiconductor layer 20. As shown in fig. 4, the electric field strength of the example model is lower than that of the comparative example model at the position B where the electric field strength has a peak. That is, the electric field distribution is more uniform in the example model compared to the comparative example model. In this way, the electric field concentration on the side surface of the column region 22 facing the second main electrode 40 can be relaxed by the electric field relaxing region 23.

Fig. 5 shows the calculation result of the electric field intensity distribution at the same plane level as the bottom surface of the second main electrode 40. As shown in fig. 5, the electric field intensity also has a peak at the position C where the drift region 21 is connected to the second main electrode 40. In the example model, the electric field intensity from the position B to the position C is lower than that in the comparative model, and the concentration of the electric field can be relaxed by the electric field relaxing region 23.

As shown in fig. 5, an electric field is concentrated at the corner of the second main electrode 40 inside the semiconductor layer 20. Therefore, when the electric field alleviation region 23 is formed to the depth of the bottom surface of the semiconductor layer 20, the electric field is diffused in the depth direction, and the electric field concentration can be alleviated. Therefore, the electric field alleviation region 23 may be formed so as to reach the main surface of the substrate 10.

As described above, the electric field is concentrated in the region between the column region 22 and the second main electrode 40. Therefore, although the electric field alleviation region 23 is arranged over the entire boundary between the drift region 21 and the column region 22 in the semiconductor device shown in fig. 1, the electric field alleviation region 23 may be arranged in contact with only the side surface of the column region 22 that faces the second main electrode 40. By not disposing the electric field alleviation region 23 on the side surface of the column region 22 parallel to the current path and opposed to the drift region 21, the width of the drift region 21 is not narrowed, and an increase in the resistance of the current path of the main current can be suppressed.

However, the concentration of the electric field also occurs in the boundary region of the current path facing the column region 22 in parallel with the drift region 21. Fig. 6 shows the electric field intensity distribution along the boundary line L shown in fig. 2 and 3. As shown in fig. 6, the electric field distribution of the example model is more uniform than that of the comparative example model having a peak in the electric field strength at the position B. In this way, the electric field relaxation region 23 can relax the concentration of the electric field even in the boundary region between the drift region 21 and the column region 22 parallel to the current path. Therefore, as shown in fig. 1, the electric field alleviation region 23 is also disposed on the side surface of the column region 22 that is parallel to the current path and faces the drift region 21 of the column region 22.

As described above, according to the semiconductor device of the first embodiment of the present invention, the electric field relaxation region 23 is disposed at least in a part between the drift region 21 and the column region 22, whereby the concentration of the electric field can be relaxed. As a result, the breakdown voltage of the semiconductor device having the SJ structure can be suppressed from decreasing.

The substrate 10 is preferably a semi-insulating substrate or an insulating substrate. This can simplify the element separation process when a plurality of semiconductor devices are integrated on the same substrate 10. In addition, when the semiconductor device is actually mounted on the cooler, an insulating substrate provided between the substrate 10 and the cooler can be omitted. Here, the insulating substrate means a substrate having a resistivity of several k Ω · cm or more.

For example, an insulating silicon carbide (SiC) substrate is used for the substrate 10. Although several polytypes (polymorphs) exist in SiC, a typical 4H SiC substrate can be used as the substrate 10. By using the SiC substrate for the substrate 10, the insulation property of the substrate 10 can be improved and the thermal conductivity can be increased. Therefore, the back surface of the substrate 10 is directly attached to the cooling mechanism, and the semiconductor device can be efficiently cooled. According to this configuration, since the SiC substrate has a high thermal conductivity, heat generated by the main current can be efficiently dissipated when the semiconductor device is in the on state. Further, SiC is a wide band gap semiconductor and has a small number of intrinsic carriers, so that high insulation properties can be easily achieved and a semiconductor device having high withstand voltage can be realized.

Next, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. The following method for manufacturing a semiconductor device is an example, and other methods including this modification can be implemented. In the following, a case where an undoped SiC substrate is used as the substrate 10 will be described.

First, as shown in fig. 7, the drift region 21 is selectively formed by doping the substrate 10 with n-type impurities by ion implantation using the patterned mask material 111 as a mask. To facilitate understanding of the structure, the mask material is shown only on the outer edge (the same below).

As a general mask material, a silicon oxide film can be used, and as a deposition method, a thermal CVD method and a plasma CVD method can be used. As a method of patterning, photolithography can be used. That is, the mask material is etched using the patterned photoresist film as a mask. As an etching method, wet etching using hydrofluoric acid, dry etching such as reactive ion etching, or the like can be used. Thereafter, the photoresist film is removed by oxygen plasma, sulfuric acid, or the like. In this way, the mask material is patterned.

Next, a column region 22 extending parallel to the drift region 21 is formed inside the drift region 21 to form an electric field alleviation region 23 at least a part between the column region 22 and the drift region 21. That is, as shown in fig. 8, the p-type impurity is doped into the substrate 10 by ion implantation using the patterned new mask material 112 as a mask, thereby selectively forming the column region 22. At this time, the mask material 112 is designed so that the exposed region of the substrate 10 is narrower than the region where the drift region 21 is not formed. Thereby, the undoped electric field alleviation region 23 is formed between the drift region 21 and the column region 22.

Thereafter, as shown in fig. 9, the well region 24 is formed by ion implantation in which the substrate 10 is doped with p-type impurities using the mask material 113 as a mask. Further, as shown in fig. 10, the source region 25 is formed by ion implantation in which the substrate 10 is doped with n-type impurities using the mask material 114 as a mask.

In the ion implantation, for example, nitrogen (N) is used as an N-type impurity, and aluminum or boron is used as a p-type impurity. By performing ion implantation while heating the substrate 10 to about 600 ℃, it is possible to suppress occurrence of crystal defects in the ion implanted region. Then, the impurity after ion implantation is activated by heat treatment. For example, the heat treatment is performed at about 1700 ℃ in an argon and nitrogen atmosphere.

The impurity concentrations of the column region 22 and the drift region 21 are, for example, 1E15/cm³～1E19/cm³Left and right. However, in order to deplete the drift region 21 and the column region 22 by the depletion layer generated between the drift region 21 and the column region 22 in the off state, the impurity concentrations of the drift region 21 and the column region 22 are set so as to satisfy the relationship of expression (1).

The impurity concentration of the well region 24 is, for example, 1E15/cm³～1E19/cm³Left and right. In addition, the impurity concentration of the source region 25 is, for example, 1E18/cm³～1E21/cm³Left and right.

Note that, by forming the drift region 21 and the column region 22 by ion-implanting impurities into the substrate 10, the manufacturing cost can be reduced compared to the case of forming by epitaxial growth.

Next, as shown in fig. 11, a gate trench 500 is formed by dry etching using a patterned mask material (not shown) as a mask. Gate trenches 500 are formed at locations bordering the source regions 25, well regions 24, drift regions 21 and pillar regions 22 to a depth reaching the substrate 10.

After that, a gate insulating film 60 is formed on the inner wall surface of the gate trench 500. The gate insulating film 60 may be formed by a thermal oxidation method or a deposition method. As an example, in the case of the thermal oxidation method, the substrate is heated to a temperature of about 1100 ℃ in an oxygen atmosphere. Thereby, a silicon oxide film is formed on all portions of the substrate in contact with oxygen.

After the gate insulating film 60 is formed, nitrogen, argon, and N are added to lower the interface level of the interface between the well region 24 and the gate insulating film 60₂Annealing treatment is carried out at about 1000 ℃ in an environment such as O. In addition, pure (Japanese: straight) NO or N can be used₂And carrying out thermal oxidation in an O environment. The temperature in this case is suitably 1100 ℃ to 1400 ℃. The thickness of the gate insulating film 60 is about several tens nm.

Next, the control electrode 50 embedded in the gate trench 500 is formed. The material of the control electrode 50 is usually a polysilicon film, and here, a case where a polysilicon film is used for the control electrode 50 will be described.

As a method for depositing a polysilicon film, a reduced pressure CVD method or the like can be used. For example, the gate trench 500 is filled with a polysilicon film by depositing the polysilicon film to a thickness greater than half the width of the gate trench 500. Since the polysilicon film is formed from the inner wall surface of the gate trench 500, the gate trench 500 can be completely filled with the polysilicon film by setting the thickness of the polysilicon film as described above. For example, in the case where the width of the gate trench 500 is 2 μm, a polysilicon film is formed so that the film thickness is thicker than 1 μm. Alternatively, after depositing the polysilicon film, the polysilicon film is deposited by etching the polysilicon film in the presence of phosphorus oxychloride (POCl)₃) An n-type polysilicon film is formed by annealing at 950 ℃ to make the control electrode 50 conductive.

Next, as shown in fig. 12, the polysilicon film is etched to be flat. The etching method may be isotropic etching or anisotropic selective etching. The etching amount is set so that the polysilicon film remains inside the gate trench 500. For example, in the case of depositing a polysilicon film to a thickness of 1.5 μm for a gate trench 500 having a width of 2 μm, the etching amount of the polysilicon film is made 1.5 μm. However, in the control of etching, the over-etching of several% does not become a problem with an etching amount of 1.5 μm.

Then, a first main electrode 30 and a second main electrode 40 facing each other through the semiconductor layer 20 are formed separately on the substrate 10 along the extending direction of the drift region 21. For example, the first main electrode 30 and the second main electrode 40 are formed in a predetermined region where the substrate 10 is selectively etched using an etching mask patterned by photolithography or the like. Thereby, the semiconductor device shown in fig. 1 is completed.

As the material of the first main electrode 30 and the second main electrode 40, a metal material such as titanium (Ti), nickel (Ni), or manganese (Mo), or a laminated film of Ti/Ni/Ag or the like can be used. For example, after a metal material is entirely deposited by a sputtering method, an EB evaporation method, or the like, the metal material is etched by dry etching using a patterned photoresist film or the like as a mask, thereby forming the first main electrode 30 and the second main electrode 40. Alternatively, the first main electrode 30 and the second main electrode 40 may be formed by plating.

According to the method of manufacturing a semiconductor device described above, the electric field alleviation region 23 is formed between the drift region 21 and the column region 22. Therefore, it is possible to alleviate the concentration of the electric field at the time of reverse bias and suppress the decrease in withstand voltage of the semiconductor device having the SJ structure.

In the above description, the electric field alleviation region 23 is formed as the undoped semiconductor region by leaving a part of the undoped substrate 10 between the drift region 21 and the column region 22. However, the electric field alleviation region 23 is not limited to an undoped region. That is, the electric field alleviation region 23 may be an n-type semiconductor region formed by doping the substrate 10 with an n-type impurity, or may be a p-type semiconductor region formed by doping a p-type impurity.

For example, when the drift region 21 is an n-type semiconductor region and the column region 22 is a p-type semiconductor region, the electric field alleviation region 23 may be an n-type semiconductor region having a lower impurity concentration than the drift region 21. Alternatively, the electric field alleviation region 23 may be a p-type semiconductor region having a lower impurity concentration than the column region 22.

Although the example in which the SiC substrate is used for the substrate 10 has been described above, a semi-insulating substrate or an insulating substrate other than the SiC substrate may be used for the substrate 10. For example, a GaN substrate, a diamond substrate, a zinc oxide (ZnO) substrate, an AlGaN substrate, or the like, which is a wide band gap substrate, may be used for the substrate 10.

In addition, a wide band gap semiconductor may be used for the semiconductor layer 20. This can increase the impurity concentration while maintaining a high withstand voltage. Therefore, the breakdown voltage of the semiconductor device can be increased, and the on-resistance can be reduced.

Further, by using the semiconductor layer 20 formed of the same material for each region, the active region of the semiconductor device can be formed of the same semiconductor material. Thus, problems due to defects and the like caused by bonding of different types of semiconductor materials do not occur, and the reliability of the semiconductor device can be improved.

In the above description, the example in which the polysilicon film of the first conductivity type is used for the control electrode 50 has been described, but the polysilicon film of the second conductivity type may be used for the control electrode 50. Alternatively, another semiconductor material may be used for the control electrode 50, or another conductive material such as a metal material may be used. For example, second conductivity type silicon carbide, SiGe, Al, or the like can be used as the material of the control electrode 50.

Although an example in which a silicon oxide film is used for the gate insulating film 60 has been described, a silicon nitride film may be used for the gate insulating film 60. Alternatively, a laminated film of a silicon oxide film and a silicon nitride film may be used for the gate insulating film 60. When a silicon nitride film is used for the gate insulating film 60, isotropic etching can be performed by cleaning with hot phosphoric acid at 160 ℃.

< modification example >

The semiconductor device according to the modification of the first embodiment of the present invention further includes an electric field relaxation electrode disposed so as to cover at least a part of a region where the drift region 21 and the column region 22 face each other. In the semiconductor device of the modification shown in fig. 13, the electric field relaxation electrode 70 is disposed above the side surface of the column region 22 facing the second main electrode 40. That is, the electric field relaxation electrode 70 is disposed on the upper surface of the interlayer insulating film 80 disposed on the upper surface of the semiconductor layer 20, and the electric field relaxation electrode 70 is electrically connected to the second main electrode 40 through the opening provided in the interlayer insulating film 80.

The electric field relaxation electrode 70 is formed of a conductive film such as a metal film. For example, the electric field relaxation electrode 70 and the second main electrode 40 may be formed integrally using the same material as the second main electrode 40. The interlayer insulating film 80 is an insulating film such as a silicon oxide film.

In the semiconductor device shown in fig. 13, the electric field relaxation electrode 70 is disposed above the boundary region between the drift region 21 and the column region 22 where the electric field is likely to concentrate, whereby the gradient of the potential distribution in the boundary region can be made gentle, and the concentration of the electric field can be relaxed. That is, by disposing the electric field relaxation electrode 70 above, the depletion layer smoothly extends in the boundary region. By controlling the curvature of the depletion layer in this way, the potential changes smoothly, and the concentration of the electric field can be alleviated. At this time, by disposing the electric field relaxation electrode 70 having the same potential as the second main electrode 40 above the boundary region close to the second main electrode 40, the concentration of the electric field in the boundary region can be greatly relaxed.

Although fig. 13 shows an example in which the electric field relaxation electrode 70 is disposed above the side surface of the column region 22 facing the second main electrode 40, the electric field relaxation electrode 70 may be disposed above the side surface of the column region 22 parallel to the current path and adjacent to the drift region 21. That is, the electric field relaxation electrode 70 is disposed above the region where the electric field is concentrated. Although the electric field relaxation electrode 70 is electrically connected to the second main electrode 40, the electric field relaxation electrode 70 may be electrically connected to the first main electrode 30 or the control electrode 50.

(second embodiment)

As shown in fig. 14, in the semiconductor device according to the second embodiment of the present invention, drift regions 21 and column regions 22 are alternately arranged along the thickness direction of the substrate 10, thereby forming an SJ structure. Further, the drift region 21, the electric field alleviation region 23, and the column region 22 are laminated in the thickness direction. In the semiconductor device shown in fig. 14, the thickness is set so as to satisfy the formula (1) instead of the impurity concentration and the width of the drift region 21 and the column region 22. The other structure is the same as that of the first embodiment shown in fig. 1.

Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. The following method for manufacturing a semiconductor device is an example, and can be realized by various manufacturing methods including the modification other than this method.

First, as shown in fig. 15, the substrate 10, which is an undoped SiC semiconductor, is doped with an n-type impurity by ion implantation using the patterned mask material 211 as a mask, thereby selectively forming the drift region 21. At this time, by adjusting the intensity of the ion implantation energy, the drift region 21 is formed at a position separated from the main surface of the substrate 10 by the total thickness of the column region 22 and the thickness of the electric field relaxation region 23.

Next, as shown in fig. 16, an exposed portion is formed on the surface of the drift region 21 by ion implantation using the mask material 212 as a mask. For example, the drift region 21 is formed in a portion connected to the second main electrode 40 which is not laminated by the column region 22.

Next, as shown in fig. 17, the substrate 10 is doped with p-type impurities by ion implantation using the mask material 213 as a mask, thereby selectively forming the column regions 22. At this time, by adjusting the strength of the ion implantation capability, the electric field relaxation region 23 not doped with impurities is formed between the drift region 21 and the column region 22.

Thereafter, as shown in fig. 18, the well region 24 is formed by ion implantation in which the substrate 10 is doped with p-type impurities using the mask material 214 as a mask. Further, as shown in fig. 19, the source region 25 is formed by ion implantation in which the substrate 10 is doped with n-type impurities using the mask material 215 as a mask.

Next, as shown in fig. 20, a gate trench 500 is formed by dry etching using a patterned mask material (not shown) as a mask. Gate trenches 500 are formed at locations bordering the source regions 25, well regions 24, drift regions 21 and pillar regions 22 to a depth reaching the substrate 10.

As shown in fig. 21, after a gate insulating film 60 is formed on the inner wall surface of the gate trench 500, a control electrode 50 embedded in the gate trench 500 is formed. The method of forming the gate insulating film 60 and the control electrode 50 is the same as that described in the first embodiment.

Then, the first main electrode 30 and the second main electrode 40 facing each other through the semiconductor layer 20 are separated from each other on the substrate 10. Thereby, the semiconductor device shown in fig. 14 is completed.

In the semiconductor device shown in fig. 1, the widths of the drift region 21 and the column region 22 in the horizontal direction parallel to the main surface of the substrate 10 are, for example, about 1 μm to several μm depending on the accuracy of the photolithography technique or the like. On the other hand, in the semiconductor device shown in fig. 14, the thicknesses of the drift region 21 and the column region 22 can be more accurately controlled by adjusting the intensity of the energy of the ion implantation of the impurity. Therefore, the thickness of the drift region 21 and the thickness of the column region 22 can be made thinner than the width in the horizontal direction, for example, about several tens nm to several hundreds nm. Therefore, the repetition period of the drift region 21 and the column region 22 constituting the SJ structure can be shortened. Therefore, the semiconductor device shown in fig. 14 is easily pinched off.

In fig. 14, the drift region 21 and the column region 22 are respectively one layer, but a plurality of drift regions 21 and a plurality of column regions 22 may be alternately laminated. As a result, an SJ structure in which a plurality of pn junctions are arranged at a constant period is formed in the thickness direction of the substrate 10. With this structure, the withstand voltage of the semiconductor device can be further improved.

As described above, according to the semiconductor device of the second embodiment of the present invention, it is possible to suppress a decrease in withstand voltage of the semiconductor device having the SJ structure in which the drift regions 21 and the column regions 22 are alternately arranged in the thickness direction of the substrate 10. Otherwise, the same as the first embodiment is true, and redundant description is omitted.

(third embodiment)

As shown in fig. 22, in the semiconductor device according to the third embodiment of the present invention, the semiconductor layer 20 is formed on the side surface of the groove 100 formed on the main surface of the substrate 10. In the semiconductor device shown in fig. 22, the thickness of the side surface of the trench in the surface normal direction (hereinafter referred to as "surface normal direction") is set so as to satisfy equation (1) in place of the impurity concentrations and widths of the drift region 21 and the column region 22. Thus, in the semiconductor device shown in fig. 22, the SJ structure is formed along the surface normal direction on the side surface of the groove of the substrate 10.

In the semiconductor device shown in fig. 22, the electric field alleviation region 23 may be disposed in contact with the side surface of the column region 22 that faces the second main electrode 40. Further, the electric field alleviation region 23, which is disposed in contact with the side surface of the column region 22 that is parallel to the current path and faces the drift region 21, is disposed between the drift region 21 and the column region 22 along the surface normal direction. Therefore, the breakdown voltage of the semiconductor device can be suppressed from decreasing.

In the semiconductor device shown in fig. 22, the drift region 21 and the column region 22 are formed on the side surface of the trench 100, whereby the width of the current path can be increased in the depth direction of the substrate 10. Therefore, the on-resistance per unit substrate area can be reduced. The semiconductor layer 20 is formed by ion-implanting impurities from obliquely above into the groove 100 formed by etching on the main surface of the substrate 10.

(fourth embodiment)

As shown in fig. 23, the semiconductor device according to the fourth embodiment of the present invention is a diode structure in which the well region 24 is connected to the first main electrode 30. That is, the semiconductor device shown in fig. 23 operates as a pn junction diode having the first main electrode 30 as an anode electrode and the second main electrode 40 as a cathode electrode. In the semiconductor device shown in fig. 23, the drift regions 21 and the column regions 22 are alternately arranged in a direction perpendicular to the current path to form an SJ structure. The well region 24 has ends of the drift region 21 and the column region 22 connected thereto, and the other end of the drift region 21 is connected to the second main electrode 40.

In the on operation, a lower voltage (forward voltage) is applied to the second main electrode 40 with the first main electrode 30 as a reference potential, thereby lowering the energy barrier between the well region 24 and the drift region 21. Therefore, electrons flow from the drift region 21 into the well region 24, and a forward current flows between the first main electrode 30 and the second main electrode 40. In the off operation, a higher voltage (reverse voltage) is applied to the second main electrode 40 with the first main electrode 30 as a reference potential, thereby increasing the energy barrier between the well region 24 and the drift region 21. Therefore, electrons do not flow from the drift region 21 to the well region 24.

In the semiconductor device having a diode structure shown in fig. 23, the electric field relaxation region 23 is disposed between the drift region 21 and the column region 22, whereby the concentration of the electric field can be relaxed and the withstand voltage can be improved. In addition, in the pn junction diode in which the well region 24 is disposed between the first main electrode 30 and the drift region 21 and the column region 22, the leakage current at the time of off-state can be suppressed.

As shown in fig. 24, the semiconductor device may be a Schottky Barrier Diode (SBD) in which the drift region 21 is connected to the first main electrode 30. In the semiconductor device shown in fig. 24, the well region 24 is not disposed between the drift region 21 and the first main electrode 30, and the drift region 21 and the first main electrode 30 are electrically connected to each other with an energy barrier at their interfaces. On the other hand, the second main electrode 40 is in ohmic contact with the drift region 21.

In the semiconductor device shown in fig. 24, a metal material having a high work function, such as nickel or platinum, is used for the first main electrode 30, and a schottky junction is formed between the drift region 21 and the first main electrode 30. The second main electrode 40 is made of a material having a low work function and being in ohmic contact with the drift region 21, such as titanium. In the SBD shown in fig. 24, the electric field relaxation region 23 is disposed between the drift region 21 and the column region 22, whereby the concentration of the electric field can be relaxed.

(other embodiments)

As described above, although the present invention has been described by way of embodiments, it should not be understood that the discussion and drawings forming a part of this disclosure are intended to limit the present invention. Various alternative embodiments, examples, and application techniques will be apparent to those skilled in the art in light of this disclosure.

For example, the case where the semiconductor device which operates as a transistor is a MOSFET has been described above. However, the semiconductor device may be a transistor having another structure. For example, the present invention can be applied to a bipolar transistor in which the first main electrode 30 is an emitter electrode, the second main electrode 40 is a collector electrode, and the control electrode 50 is a base electrode.

As described above, the present invention naturally includes various embodiments and the like not described herein.

Industrial applicability

The semiconductor device and the method for manufacturing a semiconductor device according to the present invention can be used in the electronic equipment industry including the manufacturing industry for manufacturing semiconductor devices having an SJ structure.

Description of the reference numerals

10 a substrate; 20 a semiconductor layer; 21 a drift region; a 22 column region; 23 electric field alleviation region; a 24 well region; 25 a source region; 30 a first main electrode; 40 a second main electrode; 50 a control electrode; 60 a gate insulating film; 70 electric field relaxation electrode.