阅读说明：本技术 高电源抑制比电压转换电流电路 (Voltage conversion current circuit with high power supply rejection ratio ) 是由 周航 于 2019-09-17 设计创作，主要内容包括：本发明涉及一种电源抑制比电压转换电流电路,包括第一电压产生电路、与所述第一电压产生电路相连的第二电压产生电路及与所述第一电压产生电路和所述第二电压产生电路相连的电压转换电流电路,所述第一电压产生电路产生一个高电源抑制比的第一电压至所述第二电压产生电路及所述电压转换电流电路,所述第二电压产生电路产生一个高电源抑制比的第二电压至所述电压转换电流电路,所述电压转换电流电路接收所述第一电压和所述第二电压,并产生高电源抑制比的输出电流。(The invention relates to a power supply rejection ratio voltage conversion current circuit, which comprises a first voltage generation circuit, a second voltage generation circuit connected with the first voltage generation circuit and a voltage conversion current circuit connected with the first voltage generation circuit and the second voltage generation circuit, wherein the first voltage generation circuit generates a first voltage with a high power supply rejection ratio to the second voltage generation circuit and the voltage conversion current circuit, the second voltage generation circuit generates a second voltage with a high power supply rejection ratio to the voltage conversion current circuit, and the voltage conversion current circuit receives the first voltage and the second voltage and generates an output current with a high power supply rejection ratio.)

1. A power supply rejection ratio voltage conversion current circuit is characterized in that: the high power supply rejection ratio voltage conversion current circuit comprises a first voltage generation circuit, a second voltage generation circuit connected with the first voltage generation circuit and a voltage conversion current circuit connected with the first voltage generation circuit and the second voltage generation circuit, wherein the first voltage generation circuit generates a first voltage with a high power supply rejection ratio to the second voltage generation circuit and the voltage conversion current circuit, the second voltage generation circuit generates a second voltage with a high power supply rejection ratio to the voltage conversion current circuit, and the voltage conversion current circuit receives the first voltage and the second voltage and generates an output current with a high power supply rejection ratio.

2. The power supply rejection ratio voltage converting current circuit as claimed in claim 1, wherein said first voltage generating circuit includes a first field effect transistor, a second field effect transistor connected to said first field effect transistor, a third field effect transistor connected to said second field effect transistor, a fourth field effect transistor connected to said third field effect transistor, a fifth field effect transistor connected to said second field effect transistor and said third field effect transistor, a first resistor connected to said fifth field effect transistor, and a sixth field effect transistor connected to said third field effect transistor, said fourth field effect transistor, said fifth field effect transistor, and said first resistor; the first field effect transistor and the second field effect transistor form a current mirror of a cascode structure, the third field effect transistor, the fourth field effect transistor and the sixth field effect transistor form a super source follower structure, and the first resistor and the fifth field effect transistor are subjected to Miller compensation.

3. The power supply rejection ratio voltage converting current circuit as claimed in claim 2, the second voltage generating circuit comprises a seventh field effect transistor connected with the first field effect transistor, an eighth field effect transistor connected with the second field effect transistor and the seventh field effect transistor, a ninth field effect transistor connected with the fifth field effect transistor and the sixth field effect transistor, a tenth field effect transistor connected with the ninth field effect transistor, an eleventh field effect transistor connected with the ninth field effect transistor, a twelfth field effect transistor connected with the tenth field effect transistor, a thirteenth field effect transistor connected with the ninth field effect transistor and the eleventh field effect transistor, a second resistor connected with the thirteenth field effect transistor, and a fourteenth field effect transistor connected with the eighth field effect transistor, the eleventh field effect transistor, the twelfth field effect transistor and a second resistor; the seventh field effect transistor and the eighth field effect transistor form a current mirror of a cascode structure, the eleventh field effect transistor, the twelfth field effect transistor and the fourteenth field effect transistor form a super source follower structure, the second resistor and the thirteenth field effect transistor are in miller compensation, and the ninth field effect transistor is in diode connection and provides bias voltage for the eleventh field effect transistor.

4. The power supply rejection ratio voltage-converted current circuit of claim 3, wherein said voltage-converted current circuit comprises a fifteenth fet connected to said first voltage generating circuit and said second voltage generating circuit and a third resistor connected to said fifteenth fet; the fifteenth field effect transistor is in a source follower amplifier circuit structure, amplifies the first voltage and then sends the amplified first voltage to an output voltage end, and the third resistor is a load.

5. The power supply rejection ratio voltage converting current circuit as claimed in claim 4, wherein a gate of said first field effect transistor and a gate of said seventh field effect transistor are commonly connected to a first bias voltage terminal, a source of said second field effect transistor is connected to a drain of said first field effect transistor, a gate of said second field effect transistor and a gate of said eighth field effect transistor are commonly connected to a second bias voltage terminal, a drain of said second field effect transistor is connected to a source of said third field effect transistor, a source and a drain of said fifth field effect transistor and a drain of said sixth field effect transistor, and generates said first voltage to a source of a ninth field effect transistor and a source and a drain of said thirteenth field effect transistor of said second voltage generating circuit, and a gate of a fifteenth field effect transistor of said voltage converting current circuit.

6. The power supply rejection ratio voltage-converting current circuit of claim 5, wherein a gate of the third field effect transistor is connected to a third bias voltage terminal, a drain of the third field effect transistor is connected to a drain of the fourth field effect transistor, a gate of the sixth field effect transistor and one terminal of the first resistor, a gate of the fourth field effect transistor is connected to a fourth bias voltage terminal in common with a gate of the tenth field effect transistor and a gate of the twelfth field effect transistor, and a gate of the fifth field effect transistor is connected to the other terminal of the first resistor.

7. The power supply rejection ratio voltage conversion current circuit as claimed in claim 6, wherein a drain of said seventh fet is connected to a source of said eighth fet, a drain of said eighth fet is connected to a source of said eleventh fet and a drain of said fourteenth fet, and generates said second voltage to a drain of a fifteenth fet of said voltage conversion current circuit; the grid electrode and the drain electrode of the ninth field effect transistor are connected with the drain electrode of the tenth field effect transistor and the grid electrode of the eleventh field effect transistor, the drain electrode of the eleventh field effect transistor is connected with the drain electrode of the twelfth field effect transistor, the grid electrode of the fourteenth field effect transistor and one end of the second resistor, and the grid electrode of the thirteenth field effect transistor is connected with the other end of the second resistor.

8. The power supply rejection ratio voltage-converting current circuit of claim 7, wherein a source of said fifteenth fet and one end of said third resistor are commonly connected to an output voltage terminal; the source electrode of the first field effect transistor and the source electrode of the seventh field effect transistor are commonly connected with a power supply end, and the source electrode of the fourth field effect transistor, the source electrode of the sixth field effect transistor, the source electrode of the tenth field effect transistor, the source electrode of the twelfth field effect transistor, the source electrode of the fourteenth field effect transistor and the other end of the third resistor are commonly connected with a ground end.

9. The power supply rejection ratio voltage conversion current circuit according to claim 4, wherein the first field effect transistor, the second field effect transistor, the third field effect transistor, the fifth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the eleventh field effect transistor, and the thirteenth field effect transistor are P-type field effect transistors, and the fourth field effect transistor, the sixth field effect transistor, the tenth field effect transistor, the twelfth field effect transistor, the fourteenth field effect transistor, and the fifteenth field effect transistor are N-type field effect transistors.

Technical Field

The invention relates to the field of integrated circuits, in particular to a voltage-to-current conversion circuit with a high power supply rejection ratio.

Background

The existing voltage conversion current circuit does not specially process power supply noise, so that the power supply noise can greatly influence output current, and a load circuit is influenced. For example: the load is a current control oscillator, and the output current of the current control oscillator is influenced by power supply noise, so that the oscillation frequency of the oscillator is changed, and the jitter of an output clock is increased.

Therefore, it is necessary to provide a voltage conversion current circuit with a high power supply rejection ratio capable of reducing the influence of power supply noise on a load circuit.

Disclosure of Invention

The invention provides a voltage conversion current circuit with high power supply rejection ratio, which mainly aims to realize that the output current has high power supply rejection ratio and reduce the influence of power supply noise on a load circuit to a great extent.

In order to achieve the above object, the present invention provides a power supply rejection ratio voltage-to-current conversion circuit, which includes a first voltage generation circuit, a second voltage generation circuit connected to the first voltage generation circuit, and a voltage-to-current conversion circuit connected to the first voltage generation circuit and the second voltage generation circuit, wherein the first voltage generation circuit generates a first voltage with a high power supply rejection ratio to the second voltage generation circuit and the voltage-to-current conversion circuit, the second voltage generation circuit generates a second voltage with a high power supply rejection ratio to the voltage-to-current conversion circuit, and the voltage-to-current conversion circuit receives the first voltage and the second voltage and generates an output current with a high power supply rejection ratio.

Optionally, the first voltage generating circuit includes a first field effect transistor, a second field effect transistor connected to the first field effect transistor, a third field effect transistor connected to the second field effect transistor, a fourth field effect transistor connected to the third field effect transistor, a fifth field effect transistor connected to the second field effect transistor and the third field effect transistor, a first resistor connected to the fifth field effect transistor, and a sixth field effect transistor connected to the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, and the first resistor; the first field effect transistor and the second field effect transistor form a current mirror of a cascode structure, the third field effect transistor, the fourth field effect transistor and the sixth field effect transistor form a super source follower structure, and the first resistor and the fifth field effect transistor are subjected to Miller compensation. .

Optionally, the second voltage generating circuit includes a seventh fet connected to the first fet, an eighth fet connected to the second fet and the seventh fet, a ninth fet connected to the fifth fet and the sixth fet, a tenth fet connected to the ninth fet, an eleventh fet connected to the ninth fet, a twelfth fet connected to the tenth fet, a thirteenth fet connected to the ninth fet and the eleventh fet, a second resistor connected to the thirteenth fet, and a fourteenth fet connected to the eighth fet, the eleventh fet, the twelfth fet, and the second resistor; the seventh field effect transistor and the eighth field effect transistor form a current mirror of a cascode structure, the eleventh field effect transistor, the twelfth field effect transistor and the fourteenth field effect transistor form a super source follower structure, the second resistor and the thirteenth field effect transistor are in miller compensation, and the ninth field effect transistor is in diode connection and provides bias voltage for the eleventh field effect transistor.

Optionally, the voltage conversion current circuit includes a fifteenth fet connected to the first voltage generation circuit and the second voltage generation circuit, and a third resistor connected to the fifteenth fet; the fifteenth field effect transistor is in a source follower amplifier circuit structure, amplifies the first voltage and then sends the amplified first voltage to an output voltage end, and the third resistor is a load.

Optionally, the gate of the first field effect transistor and the gate of the seventh field effect transistor are commonly connected to a first bias voltage terminal, the source of the second field effect transistor is connected to the drain of the first field effect transistor, the gate of the second field effect transistor and the gate of the eighth field effect transistor are commonly connected to a second bias voltage terminal, the drain of the second field effect transistor is connected to the source of the third field effect transistor, the source and the drain of the fifth field effect transistor and the drain of the sixth field effect transistor, and the first voltage is generated to the source of the ninth field effect transistor, the source and the drain of the thirteenth field effect transistor of the second voltage generation circuit and the gate of the fifteenth field effect transistor of the voltage conversion current circuit.

Optionally, a gate of the third field effect transistor is connected to a third bias voltage terminal, a drain of the third field effect transistor is connected to a drain of the fourth field effect transistor, a gate of the sixth field effect transistor and one end of the first resistor, a gate of the fourth field effect transistor, a gate of the tenth field effect transistor and a gate of the twelfth field effect transistor are connected to a fourth bias voltage terminal, and a gate of the fifth field effect transistor is connected to the other end of the first resistor.

Optionally, a drain of the seventh field effect transistor is connected to a source of the eighth field effect transistor, a drain of the eighth field effect transistor is connected to a source of the eleventh field effect transistor and a drain of the fourteenth field effect transistor, and the second voltage is generated to a drain of a fifteenth field effect transistor of the voltage-to-current conversion circuit; the grid electrode and the drain electrode of the ninth field effect transistor are connected with the drain electrode of the tenth field effect transistor and the grid electrode of the eleventh field effect transistor, the drain electrode of the eleventh field effect transistor is connected with the drain electrode of the twelfth field effect transistor, the grid electrode of the fourteenth field effect transistor and one end of the second resistor, and the grid electrode of the thirteenth field effect transistor is connected with the other end of the second resistor.

Optionally, a source of the fifteenth field effect transistor and one end of the third resistor are commonly connected to an output voltage end; the source electrode of the first field effect transistor and the source electrode of the seventh field effect transistor are commonly connected with a power supply end, and the source electrode of the fourth field effect transistor, the source electrode of the sixth field effect transistor, the source electrode of the tenth field effect transistor, the source electrode of the twelfth field effect transistor, the source electrode of the fourteenth field effect transistor and the other end of the third resistor are commonly connected with a ground end.

Optionally, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fifth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the eleventh field effect transistor, and the thirteenth field effect transistor are P-type field effect transistors, and the fourth field effect transistor, the sixth field effect transistor, the tenth field effect transistor, the twelfth field effect transistor, the fourteenth field effect transistor, and the fifteenth field effect transistor are N-type field effect transistors.

The high power supply rejection ratio voltage conversion current circuit provided by the invention has the advantages that the output current has a high power supply rejection ratio, and the influence of power supply noise on a load circuit is reduced to a great extent.

Drawings

Fig. 1 is a block diagram of a voltage-to-current conversion circuit with a high power supply rejection ratio according to an embodiment of the invention;

fig. 2 is a specific circuit structure diagram of a voltage-to-current conversion circuit with a high power supply rejection ratio according to an embodiment of the invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Embodiments of the present invention will now be described with reference to the drawings, wherein like element numerals represent like elements.

The invention provides a voltage conversion current circuit with high power supply rejection ratio. Referring to fig. 1, a block diagram of a voltage-to-current conversion circuit with a high power supply rejection ratio according to an embodiment of the invention is shown.

As shown in fig. 1, the high power supply rejection ratio voltage-converting current circuit of the present invention includes a first voltage generating circuit, a second voltage generating circuit connected to the first voltage generating circuit, and a voltage-converting current circuit connected to the first voltage generating circuit and the second voltage generating circuit, wherein the first voltage generating circuit generates a first voltage VF with a high power supply rejection ratio to the second voltage generating circuit and the voltage-converting current circuit, the second voltage generating circuit generates a second voltage VD with a high power supply rejection ratio to the voltage-converting current circuit, and the voltage-converting current circuit receives the first voltage VF and the second voltage VD and generates an output current IO with a high power supply rejection ratio.

Referring to fig. 2, fig. 2 is a specific circuit structure diagram of a voltage-to-current conversion circuit with high power supply rejection ratio according to an embodiment of the invention. In this embodiment, the first voltage generating circuit includes a first fet M1, a second fet M2 connected to the first fet M1, a third fet M3 connected to the second fet M2, a fourth fet M4 connected to the third fet M3, a fifth fet M5 connected to the second fet M2 and the third fet M3, a first resistor R1 connected to the fifth fet M5, and a sixth fet M6 connected to the third fet M3, the fourth fet M4, the fifth fet M5, and the first resistor R1; the second voltage generating circuit comprises a seventh field effect transistor M7 connected with the first field effect transistor M1, an eighth field effect transistor M8 connected with the second field effect transistor M2 and the seventh field effect transistor M7, a ninth field effect transistor M9 connected with the fifth field effect transistor M5 and the sixth field effect transistor M6, a tenth field effect transistor M10 connected with the ninth field effect transistor M9, and an eleventh field effect transistor M11 connected with the ninth field effect transistor M9, a twelfth fet M12 connected to the tenth fet M10, a thirteenth fet M13 connected to the ninth fet M9 and the eleventh fet M11, a second resistor R2 connected to the thirteenth fet M13, and a fourteenth fet M14 connected to the eighth fet M8, the eleventh fet M11, the twelfth fet M12, and the second resistor R2; the voltage conversion current circuit comprises a fifteenth field effect transistor M15 connected with the first voltage generation circuit and the second voltage generation circuit and a third resistor R3 connected with the fifteenth field effect transistor M15.

The specific circuit connection relationship of the high power supply rejection ratio voltage conversion current circuit provided by one embodiment of the invention is as follows: a gate of the first fet M1 and a gate of the seventh fet M7 are commonly connected to a first bias voltage terminal VP1, a source of the second fet M2 and a drain of the first fet M1 are connected, a gate of the second fet M2 and a gate of the eighth fet M8 are commonly connected to a second bias voltage terminal VP2, a drain of the second fet M2 and a source of the third fet M3, a source and a drain of the fifth fet M5 and a drain of the sixth fet M6 are connected, and the first voltage VF is generated to a source of a ninth fet M9 and a source and a drain of a thirteenth fet M13 of the second voltage generation circuit, and a gate of a fifteenth fet M15 of the voltage conversion current circuit; the gate of the third fet M3 is connected to the third bias voltage terminal VI, the drain of the third fet M3 is connected to the drain of the fourth fet M4, the gate of the sixth fet M6 and one end of the first resistor R1, the gate of the fourth fet M4, the gate of the tenth fet M10 and the gate of the twelfth fet M12 are connected to the fourth bias voltage terminal VN, and the gate of the fifth fet M5 is connected to the other end of the first resistor R1. The drain of the seventh fet M7 is connected to the source of the eighth fet M8, the drain of the eighth fet M8 is connected to the source of the eleventh fet M11 and the drain of the fourteenth fet M14, and generates the second voltage VD to the drain of the fifteenth fet M15 of the voltage-to-current conversion circuit; the grid and the drain of the ninth field-effect tube M9 are connected with the drain of the tenth field-effect tube M10 and the grid of the eleventh field-effect tube M11, the drain of the eleventh field-effect tube M11 is connected with the drain of the twelfth field-effect tube M12, the grid of the fourteenth field-effect tube M14 and one end of the second resistor R2, and the grid of the thirteenth field-effect tube M13 is connected with the other end of the second resistor R2. The source of the fifteenth field effect transistor M15 and one end of the third resistor R3 are connected with an output voltage end VO in common; the source of the first fet M1 and the source of the seventh fet M7 are commonly connected to a power supply terminal VCC, and the source of the fourth fet M4, the source of the sixth fet M6, the source of the tenth fet M10, the source of the twelfth fet M12, the source of the fourteenth fet M14, and the other end of the third resistor R3 are commonly connected to a ground terminal GND.

In this embodiment, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fifth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the eleventh field effect transistor, and the thirteenth field effect transistor are P-type field effect transistors, the fourth field effect transistor, the sixth field effect transistor, the tenth field effect transistor, the twelfth field effect transistor, the fourteenth field effect transistor, and the fifteenth field effect transistor are N-type field effect transistors, and in other embodiments, the field effect transistors may be devices having other structures capable of achieving the same function, but are not limited thereto.

The working principle of the high power supply rejection ratio voltage conversion current circuit is as follows: the first fet M1 and the second fet M2 form a current mirror of a cascode structure, the first bias voltage terminal VP1 and the second bias voltage terminal VP2 provide a bias voltage for the current mirror, the third bias voltage terminal VI and the fourth bias voltage terminal VN provide a bias voltage for the third fet M3 and the fourth fet M4, the third fet M3, the fourth fet M4 and the sixth fet M6 form a super source follower structure, and the first resistor R1 and the fifth fet M5 are miller compensation, so that a feedback system in the super source follower is stabilized.

The seventh fet M7 and the eighth fet M8 constitute a cascode current mirror, the first bias voltage terminal VP1 and the second bias voltage terminal VP2 provide a bias voltage for the current mirror, the fourth bias voltage terminal VN provides a bias voltage for the tenth fet M10 and the twelfth fet M12, the eleventh fet M11, the twelfth fet M12, and the fourteenth fet M14 constitute a super source follower structure, the second resistor R2 and the thirteenth fet M13 are miller compensations, so that a feedback system in the super source follower is stabilized, and the ninth fet M9 is diode-connected to provide a bias voltage for the eleventh fet M11.

The fifteenth fet M15 is a source follower amplifier circuit structure, amplifies the first voltage VF and sends the amplified first voltage VF to the output voltage terminal VO, and the third resistor R3 is a load.

The input voltage of the high power supply rejection ratio voltage conversion current circuit passes through a super source follower composed of the third field-effect transistor M3, the fourth field-effect transistor M4 and the sixth field-effect transistor M6 to obtain the first voltage VF, and a current mirror of a cascode structure composed of the first field-effect transistor M1 and the second field-effect transistor M2 can increase impedance from the first voltage VF to a power supply relative to a current mirror of one field-effect transistor, and meanwhile, the super source follower structure reduces impedance of the first voltage VF to ground, so that the power supply rejection ratio of the first voltage VF can be effectively improved.

The current mirror of the cascode structure formed by the seventh fet M7 and the eighth fet M8 can increase the impedance of the second voltage VD to the power supply, compared with the current mirror of one fet, and at the same time, the super-source follower structure formed by the eleventh fet M11, the twelfth fet M12, and the fourteenth fet M14 reduces the impedance of the second voltage VD to the ground, so that the power supply rejection ratio of the second voltage VD can be effectively improved.

The first voltage VF is amplified by the source follower of the fifteenth fet M15 and then sent to the output voltage terminal VO to generate an output voltage, the output current IO is a ratio of the output voltage to the load resistor R3, and the power supply rejection ratio of the gate voltage and the drain voltage (the first voltage VF and the second voltage VD) of the fifteenth fet M15 is increased, so that the power supply rejection ratio of the output current IO is greatly improved. Therefore, the invention can realize that the output current IO has high power supply rejection ratio, and greatly reduce the influence of power supply noise on a load circuit.

The present invention has been described in connection with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, and is intended to cover various modifications, equivalent combinations, which are made in accordance with the spirit of the present invention.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.