阅读说明：本技术 用于磁传感器的时序控制电路及应用系统 (Sequential control circuit for magnetic sensor and application system ) 是由 肖登艳 陈忠志 彭卓 赵翔 于 2020-11-30 设计创作，主要内容包括：本发明公开了用于磁传感器的时序控制电路及应用系统,包括慢时钟电路、快时钟电路和组合逻辑单元,所述慢时钟电路控制组合逻辑单元,所述快时钟电路同时控制并响应于组合逻辑单元；所述磁信号检测的时序控制电路引入了快慢两套时钟电路,组合逻辑运算量小,慢时钟电路工作电流低,快时钟工作时间短,有效的降低了开关芯片的功耗,另外组合逻辑控制电路逻辑清晰,运算量小,不易产生毛刺信号,可扩展性和实用性强。(The invention discloses a time sequence control circuit for a magnetic sensor and an application system, comprising a slow clock circuit, a fast clock circuit and a combinational logic unit, wherein the slow clock circuit controls the combinational logic unit, and the fast clock circuit controls and responds to the combinational logic unit at the same time; the time sequence control circuit for magnetic signal detection introduces two sets of clock circuits, namely a fast clock circuit and a slow clock circuit, the combinational logic operand is small, the working current of the slow clock circuit is low, the working time of the fast clock is short, the power consumption of a switch chip is effectively reduced, in addition, the combinational logic control circuit has clear logic and small operand, burr signals are not easy to generate, and the expandability and the practicability are strong.)

1. The time sequence control circuit for the magnetic sensor is characterized by comprising a slow clock circuit, a fast clock circuit and a combinational logic unit, wherein the slow clock circuit controls the combinational logic unit, and the fast clock circuit simultaneously controls and responds to the combinational logic unit;

the output F _ CLK signal end of the fast clock circuit is connected with a CLK _1 terminal of the combinational logic unit, and the input EN signal end of the fast clock circuit is connected with an EN output terminal of the combinational logic unit; the output S _ CLK signal end of the slow clock circuit is connected with a CLK _2 terminal of the combinational logic unit; the POR signal end is connected with a POR terminal of the combinational logic unit, and the Sampling end and the EN end of the combinational logic unit output a Sampling signal and an EN signal; the EN signal is used for controlling a switch in the magnetic sensor chip to work in a time sequence, and the Sampling signal is used for Sampling an output result of a comparator in the magnetic sensor chip.

2. The timing control circuit for a magnetic sensor of claim 1, wherein the combinational logic unit comprises: the driving circuit comprises an AND gate And1, an AND gate And3, an AND gate And4, a counter, a D-type trigger DFF6, a delayer buffer1, a delayer buffer2, a driving buffer Driver buffer1 And an inverter INV 1.

3. The timing control circuit for a magnetic sensor according to claim 2, wherein the And gate an 1, the And gate an 3, And the And gate an 4 are two-input And gates an.

4. The timing control circuit for the magnetic sensor as claimed IN claim 2, wherein the CLK _1 AND POR signal terminals are respectively connected to the input terminals of a two-input AND gate AND1, the output terminal of the two-input AND gate AND1 is connected to the input IN terminal of a counter, the output of the counter is a Sampling signal, the output terminal OUT of the counter is connected to the input terminal of a first delay buffer1, the output terminal of the delay buffer1 is connected to the input terminals of two delay buffers 2, the output terminal of the second delay buffer delay 2 AND the POR signal terminal are connected to a two-input AND gate AND3, AND the output terminal of the two-input AND gate AND3 is connected to the input terminal of an inverter INV 1; the output end of the inverter INV1 is connected with the Reset signal end, and the counter Reset terminal is connected with the Reset signal end; the POR signal end AND the clock CLK _2 signal end are connected with a two-input AND gate AND4, the output end of the two-input AND gate AND4 is connected with the input clock CLK terminal of a D-type trigger DFF6, the D-input terminal of the D-type trigger DFF6 is connected with a power supply VDD, the Q output terminal of the D-type trigger DFF6 is connected with the input end of a driving buffer driver buffer1, the output end of the driving buffer driver buffer1 is connected with an EN signal end, the CLR terminal of the D-type trigger DFF6 is connected with a Reset signal end, AND the D-type trigger DFF6 is connected with the clock CLK _2 signal endThe terminals are suspended.

5. The timing control circuit for a magnetic sensor of claim 2, wherein the counter comprises a class D flip-flop DFF1, a class D flip-flop DFF2, a class D flip-flop DFF3, a class D flip-flop DFF4, a class D flip-flop DFF5, And a two-input And gate ant 2; the input IN signal is connected with the input clock CLK terminal of the D-type trigger DFF1, the D-input terminal of the D-type trigger DFF1 is connected with the input clock CLK terminal of the D-type trigger DFF1An output Q terminal of the D-type flip-flop DFF1 is connected with an input clock CLK terminal of the D-type flip-flop DFF2, and an output of the D-type flip-flop DFF2The terminal is connected with the input D terminal of the D-type trigger DFF2, the output Q terminal of the D-type trigger DFF2 is connected with the input clock CLK terminal of the D-type trigger DFF3, and the D input terminal of the D-type trigger DFF3 is connected with the input clock CLK terminal of the D-type trigger DFF3An output Q terminal of the D-type flip-flop DFF3 is connected with an input clock CLK terminal of the D-type flip-flop DFF4, and a D input terminal of the D-type flip-flop DFF4 is connected with a D-type flip-flop DFF4An output Q terminal of the D-type flip-flop DFF4 is connected with an input clock CLK terminal of the D-type flip-flop DFF5, and a D input terminal of the D-type flip-flop DFF5 is connected with a D-type flip-flop DFF5A terminal;

the output Q terminal of the third flip-flop DFF3 AND the output Q terminal of the fifth flip-flop DFF5 are respectively connected to the input terminal of the second two-input AND gate AND2, so as to form a modulo-12 counter; the Reset CLR terminals of the D-type flip-flops DFF1, DFF2, DFF3, DFF4 and DFF5 are simultaneously connected with a Reset signal terminal.

6. The timing control circuit for the magnetic sensor as claimed in claim 2, wherein the Delay buffers 1 and2 are formed by cascading even number Delay inverters, and the Delay inverters are formed by an inverter of an inverse ratio tube and an RC device.

7. The timing control circuit for the magnetic sensor as claimed in claim 2, wherein the driving buffer Driver buffer1 is formed by cascading even number driving inverters, the driving inverters can be formed by proportional tube inverters, the number of driving cascades is designed according to the load of driving, and the cascade proportion is multiple.

8. The application system of the time sequence control circuit for the magnetic sensor is characterized by comprising the time sequence control circuit and a magnetic resistance signal processing circuit, wherein the magnetic resistance signal processing circuit responds to an enable signal EN and a Sampling signal Sampling sent by the time sequence control circuit.

Technical Field

The invention relates to the field of sensor control circuits, in particular to a time sequence control circuit for a magnetic sensor and an application system.

Background

Currently, the Anisotropic Magnetoresistance (AMR) effect is a phenomenon in which the resistivity in a ferromagnetic material changes with the change of magnetization (external magnetic field) and current direction, and a magnetoresistive sensor manufactured based on the AMR effect has been widely used because of its high sensitivity, convenience in integration, and other advantages; because the AMR switch chip is used for detecting the existence or nonexistence of a magnetic field, as long as the response is sensitive, the real-time detection is not necessary, and the framework of a time sequence control circuit for detecting a common magnetic signal has the advantages that for the application of more frequency division times and long counting period, the required combinational logic operation circuit has large scale and large operation amount, burrs are easily generated in the middle process, and the power consumption is larger.

The invention makes the analog circuits such as the magnetic resistance bridge with larger power consumption, the comparator and the like in the chip periodically in the working-sleeping-working state through the digital control circuit, determines the existence or nonexistence of the magnetic field through the sampling method, and can effectively reduce the power consumption of the chip.

Disclosure of Invention

The invention aims to solve the technical problem that a common time sequence control circuit for magnetic signal detection is provided with a fast clock circuit, and for the application of more frequency division times and long counting period, the required combinational logic operation circuit has large scale and large operation amount, burrs are easily generated in the middle process, and the power consumption is higher.

The invention is realized by the following technical scheme:

the time sequence control circuit for the magnetic sensor and the application system comprise a slow clock circuit, a fast clock circuit and a combinational logic unit, wherein the slow clock circuit controls the combinational logic unit, and the fast clock circuit controls and responds to the combinational logic unit at the same time; the output F _ CLK signal end of the fast clock circuit is connected with a CLK _1 terminal of the combinational logic unit, and the input EN signal end of the fast clock circuit is connected with an EN output terminal of the combinational logic unit; the output S _ CLK signal end of the slow clock circuit is connected with a CLK _2 terminal of the combinational logic unit; the POR signal end is connected with a POR terminal of the combinational logic unit, the Sampling end and the EN end of the combinational logic unit output a Sampling signal and an EN signal, and when the EN signal is at a high level, the magnetic sensor chip is in a normal working state; the EN signal is used for controlling a switch in the magnetic sensor chip to work in a time sequence, and the Sampling signal is used for Sampling an output result of a comparator in the magnetic sensor chip; the analog circuits such as a fast clock circuit with larger power consumption, a magnetic resistance bridge, a comparator and the like in the chip are periodically in a working-sleep-working state through a digital control circuit, and the existence or nonexistence of a magnetic field is determined through a sampling method, so that the power consumption of the chip can be effectively reduced.

Further, the combinational logic unit includes: the driving circuit comprises an AND gate And1, an AND gate And3, an AND gate And4, a counter, a D-type trigger DFF6, a delayer buffer1, a delayer buffer2, a driving buffer Driver buffer1 And an inverter INV 1.

Further, the And gate And1, the And gate And3, And the And gate And4 are two-input And gates And.

Further, the CLK _1 AND POR signal terminals are respectively connected to the input terminals of a two-input AND gate AND1, the output terminal of the two-input AND gate AND1 is connected to the input IN terminal of a counter, the output of the counter is a Sampling signal, the output terminal OUT of the counter is connected to the input terminal of a first delay buffer1, the output terminal of the delay buffer1 is connected to the input terminals of two delay buffers 2, the output terminal of the second delay buffer2 AND the POR signal terminal are connected to a two-input AND gate AND3, AND the output terminal of the two-input AND gate AND3 is connected to the input terminal of an inverter INV 1; the output end of the inverter INV1 is connected with the Reset signal end, and the counter Reset terminal is connected with the Reset signal end; the POR signal end AND the clock CLK _2 signal end are connected with a two-input AND gate AND4, the output end of the two-input AND gate AND4 is connected with the input clock CLK terminal of a D-type trigger DFF6, the D-input terminal of the D-type trigger DFF6 is connected with a power supply VDD, the Q output terminal of the D-type trigger DFF6 is connected with the input end of a driving buffer driver buffer1, the output end of the driving buffer driver buffer1 is connected with an EN signal end, the CLR terminal of the D-type trigger DFF6 is connected with a Reset signal end, AND the D-type trigger DFF6 is connected with the clock CLK _2 signal endThe terminals are suspended.

Further, the counter comprises a D-type trigger DFF1, a D-type trigger DFF2, a D-type trigger DFF3, a D-type trigger DFF4, a D-type trigger DFF5 And a two-input AND gate And an 2; the input IN signal is connected with the input clock CLK terminal of the D-type trigger DFF1, the D-input terminal of the D-type trigger DFF1 is connected with the input clock CLK terminal of the D-type trigger DFF1An output Q terminal of the D-type flip-flop DFF1 is connected with an input clock CLK terminal of the D-type flip-flop DFF2, and an output of the D-type flip-flop DFF2The terminal is connected with the input D terminal of the D-type trigger DFF2, the output Q terminal of the D-type trigger DFF2 is connected with the input clock CLK terminal of the D-type trigger DFF3, and the D input terminal of the D-type trigger DFF3 is connected with the input clock CLK terminal of the D-type trigger DFF3An output Q terminal of the D-type flip-flop DFF3 is connected with an input clock CLK terminal of the D-type flip-flop DFF4, and a D input terminal of the D-type flip-flop DFF4 is connected with a D-type flip-flop DFF4An output Q terminal of the D-type flip-flop DFF4 is connected with an input clock CLK terminal of the D-type flip-flop DFF5, and a D input terminal of the D-type flip-flop DFF5 is connected with a D-type flip-flop DFF5A terminal;

the output Q terminal of the third flip-flop DFF3 AND the output Q terminal of the fifth flip-flop DFF5 are respectively connected to the input terminal of the second two-input AND gate AND2, so as to form a modulo-12 counter; the reset CLR terminals of the D-type flip-flops DFF1, DFF2, DFF3, DFF4 and DFF5 are simultaneously connected with a Rest signal terminal.

Further, the application system of the time sequence control circuit for the magnetic sensor comprises the time sequence control circuit and a magnetic resistance signal processing circuit, wherein the magnetic resistance signal processing circuit responds to an enable signal EN and a Sampling signal Sampling sent by the time sequence control circuit.

Further, the Delay buffer1 and the Delay buffer2 are formed by connecting cascaded even number Delay inverters in series, the size of each cascade inverter is designed according to the Delay requirement, the drive buffer Driver 1 is formed by connecting cascaded even number drive inverters in series, the size of each cascade inverter is designed according to the drive load requirement, the period of the slow clock is designed into 1 slow clock period according to the work-sleep period of the chip, the forming mode of the slow clock can be realized based on the framework of an RC charge-discharge and a comparator, and the forming mode of the fast clock can be realized based on the framework of the RC charge-discharge and the comparator; the period is flexibly set according to the working time of the chip and the counting of the combinational logic.

Compared with the prior art, the invention has the following advantages and beneficial effects:

the time sequence control circuit for the magnetic sensor introduces two sets of clock circuits, namely a fast clock circuit and a slow clock circuit, so that the combined logic operand is small, the working current of the slow clock circuit is low, the working time of the fast clock is short, the power consumption of a switch chip is effectively reduced, and in addition, the combined logic control circuit has clear logic, small operand, difficult burr signal generation and strong expandability and practicability.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a frame structure of a chip timing control circuit according to the present invention.

FIG. 2 is a schematic diagram of a control circuit according to the present invention.

FIG. 3 is a schematic diagram of a combinational logic cell structure according to the present invention.

FIG. 4 is a diagram illustrating a counter structure according to the present invention.

FIG. 5 is a timing diagram of the operation of the chip according to the present invention.

FIG. 6 is a schematic diagram of the internal structure of the chip according to the present invention.

Fig. 7 is a schematic diagram of an internal structure of a chip in the prior art.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail so as not to obscure the present invention.

Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "one embodiment," "an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, it is to be understood that the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore, are not to be construed as limiting the scope of the present invention.

Examples

As shown in figure 1, the time sequence control circuit and the application system for the magnetic sensor adopt two sets of clock generators, the chip adopts a working-sleeping mode, analog circuits such as a fast clock circuit with high power consumption, a magnetic resistance bridge, a comparator and the like in the chip are periodically in a working-sleeping-working state, and the existence or nonexistence of a magnetic field is determined by a sampling method. The slow clock circuit has extremely low working current and the fast clock circuit has short working time, so that the power consumption of the chip can be effectively reduced, and the circuit can be applied to various reluctance switch chips. The chip works-the whole time period of sleep is determined by the slow clock. The working time and the sampling time of the chip are obtained by slow clock, fast clock and combinational logic operation, and the circuit comprises two sets of fast and slow clock circuits and a combinational logic operation unit. In this embodiment, to clarify the operation method of the control circuit, it is assumed that the duty-sleep cycle of the chip is set to 1 slow clock cycle, wherein the duty state is 12 fast clock cycles, the sampling time is set by multiplying the delay time of a single delay unit by the number of delay units, and the subsequent time chip is in the sleep state as shown in fig. 5.

The period of the slow clock is designed to be 1 slow clock period according to the working-sleeping period of the chip, and the structure mode can be realized based on the RC charging and discharging and the structure of a comparator.

The fast clock can be realized based on RC charging and discharging and a structure of a comparator; the period is flexibly set according to the working time of the chip and the counting of the combinational logic.

As shown in fig. 2, the combinational logic operation unit includes: an AND gate And1, an AND gate And3, an AND gate And4, a counter, a D-type trigger DFF6, a delayer buffer1, a delayer buffer2, a drive buffer1 And an inverter INV 1; the AND gate And1, the AND gate And3 And the AND gate And4 are two-input AND gates And.

Further, the CLK _1 AND POR signal terminals are respectively connected to the input terminals of a two-input AND gate AND1, the output terminal of the two-input AND gate AND1 is connected to the input IN terminal of a counter, the output of the counter is a Sampling signal, the output terminal OUT of the counter is connected to the input terminal of a first delay buffer1, the output terminal of the delay buffer1 is connected to the input terminals of two delay buffers 2, the output terminal of the second delay buffer2 AND the POR signal terminal are connected to a two-input AND gate AND3, AND the output terminal of the two-input AND gate AND3 is connected to the input terminal of an inverter INV 1; the output end of the inverter INV1 is connected with the Reset signal end, and the counter Reset terminal is connected with the Reset signal end; the POR signal end AND the clock CLK _2 signal end are connected with a two-input AND gate AND4, the output end of the two-input AND gate AND4 is connected with the input clock CLK terminal of a D-type trigger DFF6, the D-input terminal of the D-type trigger DFF6 is connected with a power supply VDD, the Q output terminal of the D-type trigger DFF6 is connected with the input end of a driving buffer driver buffer1, the output end of the driving buffer driver buffer1 is connected with an EN signal end, the CLR terminal (Reset end) of the D-type trigger DFF6 is connected with a Reset signal end, AND the D-type trigger DFF6 is connected with the clock CLK terminalThe terminals are suspended.

Further, as shown in fig. 3, the counter includes a class D flip-flop DFF1, a class D flip-flop DFF2, a class D flip-flop DFF3, a class D flip-flop DFF4, a class D flip-flop DFF5, And a two-input And gate And 2; the input IN signal is connected with the input clock CLK terminal of the D-type trigger DFF1, the D-input terminal of the D-type trigger DFF1 is connected with the input clock CLK terminal of the D-type trigger DFF1An output Q terminal of the D-type flip-flop DFF1 is connected with an input clock CLK terminal of the D-type flip-flop DFF2, and an output of the D-type flip-flop DFF2The terminal is connected with the input D terminal of the D-type trigger DFF2, the output Q terminal of the D-type trigger DFF2 is connected with the input clock CLK terminal of the D-type trigger DFF3, and the D input terminal of the D-type trigger DFF3 is connected with the input clock CLK terminal of the D-type trigger DFF3An output Q terminal of the D-type flip-flop DFF3 is connected with an input clock CLK terminal of the D-type flip-flop DFF4, and a D input terminal of the D-type flip-flop DFF4 is connected with a D-type flip-flop DFF4An output Q terminal of the D-type flip-flop DFF4 is connected with an input clock CLK terminal of the D-type flip-flop DFF5, and a D input terminal of the D-type flip-flop DFF5 is connected with a D-type flip-flop DFF5A terminal;

the output Q terminal of the third flip-flop DFF3 AND the output Q terminal of the fifth flip-flop DFF5 are respectively connected to the input terminal of the second two-input AND gate AND2, so as to form a modulo-12 counter; the Reset CLR terminals of the D-type flip-flops DFF1, DFF2, DFF3, DFF4 and DFF5 are simultaneously connected with a Reset signal terminal.

Furthermore, the delay buffer is formed by cascading even number delay inverters, and each cascade delay inverter can be formed by an inverse ratio tube inverter and an RC device.

Further, the drive buffer is formed by serially connecting odd number of cascaded inverters, the size of each cascaded inverter can be formed by a proportional tube inverter, and the number of the cascaded inverters and the cascade proportion multiple are designed according to the load of the drive.

It can be understood that: as shown in fig. 6, the timing control circuit and the working method introduce two sets of fast and slow clock circuits, the combinational logic operand is small, the working current of the slow clock circuit is low, the working time of the fast clock is short, the power consumption of the switch chip is effectively reduced, in addition, the logic of the combinational logic control circuit is clear, the operand is small, the glitch signal is not easy to generate, and the expandability and the practicability are strong.

The connection between the modules is shown in fig. 2. The output F _ CLK signal of the fast clock circuit is connected with a CLK _1 terminal of the combinational logic unit, and the input EN signal of the fast clock circuit is connected with an EN output terminal of the combinational logic unit; the output S _ CLK signal of the slow clock circuit is connected with a CLK _2 terminal of the combinational logic unit; the POR signal (from the power-on reset block, which is not described in detail here) is connected to the POR terminal of the combinational logic operation unit, which outputs Sampling, EN, reset signals.

A working method of a signal detection sequential control circuit comprises the following steps:

the number of cycles of the slow clock is constructed according to the work-sleep cycle of the chip.

Secondly, the counter is constructed according to the number of the fast clock oscillator clock cycles, in this example, 12 fast clock cycles, of the working cycle of the chip, so that a counter of 5Bit10100 can be constructed.

Constructing the Sampling signal maintaining time reasonably designs delay buffers and the cascade number thereof according to the Sampling time of the chip.

And fourthly, reasonably designing the fast clock circuit according to the working time of the chip.

Fifthly, performing combined operation on the modules to obtain the working-sleeping and sampling working time sequence of the chip.

For example, as shown in fig. 6 and fig. 7, for the architecture of the timing control circuit in the prior art, for the applications with many frequency division times and long counting period, the required combinational logic operation circuit has large scale and large operation amount, burrs are easily generated in the middle process, and the power consumption is relatively large;

the structure of the time sequence control circuit adopts two sets of clock generators, the chip adopts a working-sleeping mode, analog circuits such as a fast clock with larger power consumption, a magnetic resistance bridge, a comparator and the like in the chip are periodically in a working-sleeping-working state, and the existence or nonexistence of a magnetic field is determined by a sampling method. The slow clock circuit has extremely low working current and the fast clock circuit has short working time, so that the power consumption of the chip can be effectively reduced, and the circuit can be applied to various reluctance switch chips. The whole time period of the chip working-sleeping is determined by the slow clock; the working time and the sampling time of the chip are obtained by the combination logic operation of a slow clock, a fast clock and a combinational logic operation, and the circuit comprises:

slow clock circuit: it features long clock period, very low current consumption and setting the working-sleeping period of chip.

Fast clock circuit: the method is characterized in that the clock cycle time is short, and the working time of the fast clock and the switch chip is set through combinational logic.

A combinational logic operation unit: the Sampling clock signal generator is used for generating a detection enabling EN signal of the magnetic sensor chip, an enabling signal of the fast clock and a Sampling signal which is judged and output by the comparator.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.