阅读说明：本技术 一种比较器及电子设备 (Comparator and electronic equipment ) 是由 曹先国 于 2021-08-19 设计创作，主要内容包括：本申请提供一种比较器及电子设备,涉及电子电路技术领域,该比较器包括负载模块、第一开关、第二开关和差分对,所述差分对包括第一输入端、第二输入端、第一负载端和第二负载端,所述第一输入端和所述第二输入端用于接收比较信号,所述第一输入端通过所述第一开关与所述第二负载端连接,所述第二输入端通过所述第二开关与所述第一负载端连接,所述第一负载端和所述第二负载端分别与所述负载模块连接；所述差分对用于在接收到待比较信号且所述第一开关和所述第二开关断开时,输出经放大的电压信号,在所述第一开关和所述第二开关均闭合时,输出比较结果。能够解决目前比较器精度与比较速度受限的问题。(The application provides a comparator and electronic equipment, and relates to the technical field of electronic circuits, wherein the comparator comprises a load module, a first switch, a second switch and a differential pair, the differential pair comprises a first input end, a second input end, a first load end and a second load end, the first input end and the second input end are used for receiving comparison signals, the first input end is connected with the second load end through the first switch, the second input end is connected with the first load end through the second switch, and the first load end and the second load end are respectively connected with the load module; the differential pair is used for outputting an amplified voltage signal when a signal to be compared is received and the first switch and the second switch are disconnected, and outputting a comparison result when the first switch and the second switch are both closed. The problem that the precision and the comparison speed of the existing comparator are limited can be solved.)

1. A comparator, comprising:

a load module;

a first switch;

a second switch;

a differential pair, including a first input terminal, a second input terminal, a first load terminal and a second load terminal, where the first input terminal and the second input terminal are used to receive a comparison signal, the first input terminal is connected to the second load terminal through the first switch, the second input terminal is connected to the first load terminal through the second switch, and the first load terminal and the second load terminal are respectively connected to the load modules;

the differential pair is used for outputting an amplified voltage signal when a signal to be compared is received and the first switch and the second switch are disconnected, and outputting a comparison result when the first switch and the second switch are both closed.

2. The comparator according to claim 1, wherein the differential pair comprises a first MOS transistor and a second MOS transistor, gates of the first MOS transistor and the second MOS transistor are a first input terminal and a second input terminal, respectively, and drains of the first MOS transistor and the second MOS transistor are a first load terminal and a second load terminal, respectively;

the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube through the first switch, the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube through the second switch, and the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube.

3. The comparator according to claim 1, further comprising a plurality of third switches respectively connected to the first input terminal and the second input terminal, the third switches being configured to control the comparison signal to be input to the differential pair.

4. The comparator of claim 3, wherein the first and second switches are controlled by a first clock signal and the third switch is controlled by a second clock signal, the first and second clock signals being complementary clocks, inverted clocks, non-overlapping clocks, or partially overlapping clocks.

5. The comparator according to claim 2, further comprising a fourth switch and a tail current source, wherein one end of the tail current source is connected to the differential pair through the sources of the first and second MOS transistors, the other end of the tail current source is connected to the fourth switch, and the fourth switch is used for controlling the working state of the comparator.

6. The comparator according to claim 2, further comprising two common-gate biased MOS transistors, wherein drains of the first MOS transistor and the second MOS transistor are respectively connected to sources of the two common-gate biased MOS transistors.

7. The comparator as claimed in claim 1, wherein the load module comprises a plurality of MOS transistors and a voltage regulator, the voltage regulator is connected with the plurality of MOS transistors, the plurality of MOS transistors are paired in pairs and connected with the gates, and the voltage regulator is sequentially connected to the first load end and the second load end of the differential pair from the voltage regulator.

8. The comparator of claim 1, wherein the load module is a constant current source.

9. The comparator of claim 1, wherein the plurality of MOS transistors in the differential pair and the load block are bipolar transistors, silicon carbide transistors, gallium nitride transistors, cubic indium phosphide transistors, gallium arsenide transistors, field effect transistors, junction field effect transistors, heterojunction bipolar transistors, or insulated gate bipolar transistors.

10. An electronic device, characterized in that the comparator of any one of claims 1-9 is comprised in the electronic device.

Technical Field

The application relates to the technical field of electronic circuits, in particular to a comparator and electronic equipment.

Background

A comparator is a circuit or device that compares two or more data items or signals to determine whether they are equal or to determine the magnitude relationship and the order of arrangement between them. In the field of signal processing, conversion between an analog signal and a digital signal is important, and a comparator is widely used for conversion from an analog signal to a digital signal.

The accuracy and speed of conventional analog signal comparators is limited by the gain-bandwidth product, which is the product of the amplifier bandwidth and the bandwidth gain, a parameter that is used to evaluate the performance of active devices.

Therefore, in the conventional analog signal comparator, when the performance of the comparator is limited, the highest comparison speed of the comparator is reduced by one time when the comparison accuracy is improved by one time, so that the accuracy and the comparison speed of the comparator cannot be ensured at the same time, and the problem that the accuracy and the comparison speed are mutually compromised and limited exists.

Disclosure of Invention

An object of the present invention is to provide a comparator and an electronic device, so as to solve the problem that the precision and the comparison speed of the current comparator are limited.

In a first aspect, an embodiment of the present application provides a comparator, including:

a load module; a first switch; a second switch; a differential pair, including a first input terminal, a second input terminal, a first load terminal and a second load terminal, where the first input terminal and the second input terminal are used to receive a comparison signal, the first input terminal is connected to the second load terminal through the first switch, the second input terminal is connected to the first load terminal through the second switch, and the first load terminal and the second load terminal are respectively connected to the load modules; the differential pair is used for outputting an amplified voltage signal when a signal to be compared is received and the first switch and the second switch are disconnected, and outputting a comparison result when the first switch and the second switch are both closed.

In the implementation process, the first switch and the second switch are used for controlling one output of the differential pair to be connected to the other input end of the differential pair, the two switches are synchronously controlled to enable the comparator to compare two received analog signals, and positive feedback is carried out on the signal output, so that comparison of the two analog signals can be completed in one clock period, and meanwhile, the precision and the comparison speed of the comparator are guaranteed.

Optionally, the differential pair includes a first MOS transistor and a second MOS transistor, gates of the first MOS transistor and the second MOS transistor are a first input end and a second input end, respectively, and drains of the first MOS transistor and the second MOS transistor are a first load end and a second load end, respectively; the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube through the first switch, the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube through the second switch, and the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube.

In the implementation process, the drain electrodes of the first MOS tube and the second MOS tube are respectively used as load ends, the grid electrodes of the first MOS tube and the second MOS tube are used as input ends, and the output signal of one MOS tube is respectively connected to the input end of the other MOS tube so as to perform positive feedback on the output signal, so that the stability of a comparison result can be improved.

Optionally, the comparator further includes a plurality of third switches, the third switches are respectively connected to the input ends of the differential pairs, and the third switches are configured to control the comparison signal to be input to the differential pairs.

In the implementation process, whether the comparator receives the comparison signal or not is controlled by the plurality of third switches, so that the working state of the comparator can be controlled.

Optionally, the first switch and the second switch are controlled by a first clock signal, the plurality of third switches are controlled by a second clock signal, and the first clock signal and the second clock signal are complementary clocks, inverted clocks, non-overlapping clocks, or partially overlapping clocks.

In the implementation process, the first switch, the second switch and the third switch are respectively controlled by the two clock signals, the output state of the comparator can be changed according to the magnitude of the two input signals, so that the two MOS tubes of the differential pair synchronously operate, and the comparison of the analog signals is realized.

Optionally, the comparator further includes a fourth switch and a tail current source, one end of the tail current source is connected to the differential pair through the source electrodes of the first MOS transistor and the second MOS transistor, the other end of the tail current source is connected to the fourth switch, and the fourth switch is configured to control the operating state of the comparator.

In the implementation process, the fourth switch is arranged on the comparator, and the source electrodes of the first MOS transistor and the second MOS transistor of the comparator can be connected to ground voltage or disconnected, so that the comparator generates power consumption when performing sampling comparison, and is in a complete cut-off state when not performing sampling comparison, thereby reducing power consumption and saving resources.

Optionally, the comparator further includes two common-gate biased MOS transistors, and drains of the first MOS transistor and the second MOS transistor are respectively connected to sources of the two common-gate biased MOS transistors.

In the implementation process, the bias voltage is fixed by the two common-gate biased MOS tubes, so that the amplification factor of the comparator can be improved, and the stability of the comparator is improved.

Optionally, the fourth switch is controlled by a third clock signal.

In the implementation process, the working state of the comparator can be controlled through the third clock signal, so that the comparator can work according to a preset period, and the controllability of the comparator is improved.

Optionally, the load module includes a plurality of MOS transistors and a voltage regulator, the voltage regulator is connected to the plurality of MOS transistors, the plurality of MOS transistors are paired in pairs and connected to gates, and the plurality of MOS transistors are sequentially connected from the voltage regulator to the first load end and the second load end of the differential pair.

Optionally, the load module may also be a constant current source.

In the implementation process, the load provided for the comparator can be provided in various ways, the structure of the load module of the comparator can be selected according to the running circuit structure, and the applicability of the comparator is improved.

Optionally, the MOS transistors in the differential pair and the load module are bipolar transistors, silicon carbide transistors, gallium nitride transistors, cubic indium phosphide transistors, gallium arsenide transistors, field effect transistors, junction field effect transistors, heterojunction bipolar transistors, or insulated gate bipolar transistors.

In a second aspect, an embodiment of the present application further provides an electronic device, and an embodiment of the present application further provides an electronic device, where the electronic device is provided with the comparator in the foregoing implementation manner.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic circuit diagram of a comparator according to an embodiment of the present disclosure;

fig. 2 is a circuit structure diagram of a differential pair using PMOS transistors according to an embodiment of the present disclosure;

fig. 3 is a circuit structure diagram of a comparator with an additional operating state switch according to an embodiment of the present disclosure;

fig. 4 is a circuit structure diagram of a comparator provided in an embodiment of the present application, in which two common-gate biased MOS transistors are additionally installed on the drains of the differential pair MOS transistors;

fig. 5 is a structural diagram of a comparator using two MOS transistors and a voltage regulator as a load according to an embodiment of the present application;

fig. 6 is an equivalent structure diagram of a comparator using more MOS transistors and a voltage regulator as a load according to an embodiment of the present application;

fig. 7 is a circuit structure diagram of a comparator with a resistor as a load according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a comparator with a bipolar transistor structure according to an embodiment of the present application;

fig. 9 is a general structure diagram of a comparator according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. For example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of architectures, systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, block, segment, or portion of code, which comprises one or more executable instructions for implementing the specified analog and logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The structure of the existing comparator mainly comprises an operational amplifier structure comparator and a reproducible comparator structure, wherein the operational amplifier structure comparator needs quiescent current so as to ensure a quiescent operating point, and the sensitivity is high, but the operational amplifier structure comparator is limited by the operational amplifier bandwidth and has low comparison speed; the reproducible comparator structure needs a static working point when working, and simultaneously uses positive feedback to realize the comparison of two signals, the transmission time is short, the speed is high, but the sensitivity and the resolution are not high, and the offset and the return noise are large.

The precision and the speed of the traditional analog signal comparator are limited by the gain bandwidth product, so that the comparator provided by the application adopts an all-digital structure, directly processes the analog signal, and ensures the precision and the comparison speed of the comparator by avoiding the limitation of the gain bandwidth product.

Referring to fig. 1, fig. 1 is a schematic circuit diagram of a comparator according to an embodiment of the present disclosure, where the comparator 10 may include: the load module 11, the first switch, the second switch and the differential pair 12 include a first input end, a second input end, a first load end and a second load end, the first input end and the second input end are used for receiving a comparison signal, the first input end is connected with the second load end through the first switch, the second input end is connected with the first load end through the second switch, and the first load end and the second load end are respectively connected with the load module 11; the differential pair 12 is configured to output an amplified voltage signal when receiving a signal to be compared and the first switch and the second switch are turned off, and output a comparison result when the first switch and the second switch are both turned on.

Wherein the first switch may be a switch S1, the second switch may be a switch S2, and the load module 11 may be a constant current source I₀。

Illustratively, two analog signals V to be compared_inAnd V_refWhen the first switch S1 and the second switch S2 are closed, two analog signals are respectively input to the other input end via one load end of the differential pair 12, and the comparator 10 determines according to the voltage of the two input ends and represents the comparison result according to the mode of outputting high level or low level.

Although the comparator 10 provided in the embodiment of the present application still undergoes the amplification, reverse phase regeneration, and other stages after the sampling stage, and the comparison result can be output after a period of time (latency), the comparison result is already determined after the sampling stage, that is, the comparator has the characteristic that the comparison result is no longer affected by the input comparison voltage difference after the "sampling", and the characteristic can enable a plurality of comparators 10 to be connected to the same group of differential comparison voltage signals for performing "time-interleaved sampling" (time-interleaved sampling) comparison, and obtain a plurality of comparison results within the latency time after the amplification, reverse phase regeneration, and other stages thereafter. The comparator 10 with this structure can be applied to a circuit design with a higher speed.

Therefore, with the comparator structure provided by the embodiment of the present application, the first switch S1 and the second switch S2 are closed to control and respectively connect one output of the differential pair 12 to the other input end of the differential pair 12, the two switches are synchronously controlled to enable the comparator 10 to compare two received analog signals, and perform positive feedback on the signal output, so that the comparison of the two analog signals can be completed within one clock cycle, and the precision and the comparison speed of the comparator 10 are ensured.

Optionally, the differential pair 12 may include a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) Transistor and a second MOS Transistor, gates of the first MOS Transistor and the second MOS Transistor are a first input end and a second input end, respectively, and drains of the first MOS Transistor and the second MOS Transistor are a first load end and a second load end, respectively; the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube through the first switch, the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube through the second switch, and the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube.

Wherein, the first MOS transistor can be M₁The second MOS transistor may be M₂，M₁And M₂It may be a PMOS (P-Metal-Oxide-Semiconductor) transistor, specifically, please refer to fig. 2, and fig. 2 is a circuit structure diagram of a differential pair using a PMOS transistor according to an embodiment of the present disclosure. M₁And M₂Or an NMOS (N-Metal-Oxide-Semiconductor) tube, and as shown in fig. 1, the NMOS tube may be specifically configured according to the actual situation.

M₁And M₂For two identical MOS transistors, the first switch S1 switches M₂Is connected to M₁Of the second switch S2 will M₁Is connected to M₂At two analog signals V_inAnd V_refWhen the analog signal is inputted to the differential pair 12, the third switch S3 is controlled to be closed to output the analog signal V_inIs transmitted to M₁Input terminal of, will imitate the signal V_refIs transmitted to M₂Of two analog signals V, comparing the two analog signals V_inAnd V_refThe level of (2).

Therefore, the embodiment of the application adopts the structure of the differential pair to compare analog signals, the drain electrodes of the first MOS tube and the second MOS tube are respectively used as the load ends, the grid electrodes of the first MOS tube and the second MOS tube are used as the input ends, the output signals of the MOS tubes are respectively connected to the input end of the other MOS tube, so that the output signals are positively fed back, and the stability of the comparison result can be improved.

Optionally, the comparator 10 may further include a plurality of third switches, the third switches being respectively connected to the first input terminal and the second input terminal, and the third switches being used for controlling the comparison signal to be input to the differential pair 12.

Illustratively, two third switches, respectively two switches S3, may be included in the comparator 10.

It can be seen that the operation state of the comparator 10 can be controlled by controlling whether the comparator 10 receives the comparison signal through the third switch S3.

Optionally, the first switch and the second switch are controlled by a first clock signal, the third switch is controlled by a second clock signal, and the first clock signal and the second clock signal are complementary clocks, reverse clocks, non-overlapping clocks, or partially overlapping clocks.

Wherein the first clock signal may be phi₁The second clock signal may be phi₂，ф₁The period of (2) may be T1 phi₂May be T2 according to phi₁Phi-₂The clock signal of (1) controls the comparator (10) to operate in accordance with a fixed sequential logic on the analog signal (V)_inAnd V_refA comparison is made.

It can be seen that the output state of the comparator 10 can be changed according to the input signal by controlling the first switch, the second switch and the third switch with two clock signals, so that the two MOS transistors M of the differential pair 12 can be changed₁And M₂And synchronously operating to realize comparison of the analog signals.

Illustratively, two analog signals V_inAnd V_refConnected to the first and second inputs of the differential pair 12, respectively, MOS transistor M₁Is connected to the MOS transistor M₂Grid of (3), MOS transistor M₂Is connected to M₁The three switches are respectively driven by a clock signal phi₁Phi-₂Control, wherein the clock signal phi₁Control switch S₃Phi, clock signal₂Control switch S₁And S₂Phi, clock signal₁Phi-₂The complementary clocks may be inverted clocks, non-overlapping clocks, or partially overlapping clocks.

Wherein, the constant current source is used as the load of the differential pair 12, and the clock signal phi is generated when the constant current source is used as the load₁When logic 1 is present, switch S₃On, switch S₁、S₂Cut-off, analogue signal V_inBy means of a switch S₃Is input to M₁At point A of the input terminal, at this time V_A＝V_inAnalog signal V_refBy means of a switch S₃Is input to M₂At point B of the input terminal, at this time V_B＝V_refThen the voltage at the point A is controlled by the MOS transistor M₁Amplification is-KV_A(ф₁) Voltage at point B is controlled by MOS transistor M₂Amplification is-KV_B(ф₁)。

When the clock signal phi₂When logic 1 is present, switch S₃Cut-off, switch S₁、S₂On, M₂Is passed through S₁Is connected to M₁At the time point A, the voltage at the point A is V_A(ф₁) And by M₂amplified-KV_B(ф₁) Since both are in a line-and-line relationship, V_AWill tend to a certain value, set the value to be [ (alpha V)_A(ф₁))+β(-KV_B(ф₁))](ii) a Wherein alpha and beta are respectively line and rear V_A(ф₁) Amplification factor of and (-KV)_B(ф₁) Magnification of), M₁Is passed through S₂Is connected to M₂At point B of the input terminal, the voltage at point B is changed from V_B(ф₁) And by M₂amplified-KV_A(ф₁) Is also based on the fact that both are wired-and-connected, so V_BWill also tend toward a value of [ (α V)_B(ф₁))+β(-KV_A(ф₁))]。

Let V_in＞V_refThen [ (alpha V) can be obtained_A(ф₁))+β(-KV_B(ф₁))]＞[(αV_B(ф₁))+β(-KV_A(ф₁))]Thereby comparing the level of the two analog signals.

At the same time, the voltage at point A passes through M₁And M₂Is amplified and then fed back to an input point A as positive feedback, and the voltage of a point B passes through M₂And M₁Is fed back to the input point B, which is also a positive feedback, and repeating the above steps will make M₂Is stabilized at a high level, and M₁The drain of (2) is stabilized at a low level, so that a stable comparison result can be obtained.

In the current comparator circuit structure, there is always an active leakage current, so that the comparator also has power consumption in a static state, and the power consumption is not much different from the power consumption of the comparator in an operating state, in view of this, the embodiment of the present application further provides a schematic circuit structure diagram of the comparator with the operating state switch, please refer to fig. 3, and fig. 3 is a circuit structure diagram of the comparator with the operating state switch provided in the embodiment of the present application.

The comparator 10 may further include a fourth switch and a tail current source, and the fourth switch may be S₄The tail current source 2I₀May be a constant current source. The tail current source 2I₀One end of the differential pair 12 is connected with the source electrodes of the first MOS tube and the second MOS tube, and the tail current source 2I₀And the other end of the fourth switch S₄Connection, the fourth switch S₄For controlling the operating state of said comparator 10.

The operating state of the comparator 10 can be switched by the fourth switch to control the comparator 10 to start or stop.

Therefore, the fourth switch is arranged on the comparator 10, so that the input end of the comparator 10 can be connected to the ground voltage or disconnected, power consumption is generated only when the comparator 10 performs sampling comparison, and the comparator is in a complete cut-off state when sampling comparison is not performed, so that power consumption can be reduced, and resources can be saved.

Optionally, the fourth switch is controlled by a third clock signal.

Therefore, the operating state of the comparator 10 can be controlled by the third clock signal, so that the comparator 10 can operate according to a preset period, and the controllability of the comparator 10 is improved.

Based on the same inventive concept, an embodiment of the present application further provides a comparator in which two MOS transistors with common gate bias are additionally mounted on the drain of the differential pair MOS transistor, please refer to fig. 4, and fig. 4 is a circuit structure diagram of the comparator in which two MOS transistors with common gate bias are additionally mounted on the drain of the differential pair MOS transistor according to the embodiment of the present application.

The differential pair 12 is formed by two MOS transistors M biased by common gate₃And M₄Connected with the load module 11, the MOS transistor M₃And M₄For increasing the amplification of the differential pair 12.

Wherein, MOS tube M₃And M₄One or more pairs of MOS transistors are connected in series, and the differential pair 12 and two load ends are respectively connected through the MOS transistors M₃And M₄The gate of (2) is inputted with a fixed bias voltage, so that the amplification factor of the differential pair 12 is increased, and the stability of the comparator 10 can be improved. In some embodiments, MOS transistor M₃And M₄The amplifier of the differential pair 12 may amplify the signal inputted to the differential pair 12.

Optionally, referring to fig. 5 and fig. 6 in combination, the load module 11 may include a plurality of MOS transistors and a voltage regulator, the voltage regulator is connected to the plurality of MOS transistors, the plurality of MOS transistors are paired in pairs and connected to the gates, and the voltage regulator is sequentially connected to the first load end and the second load end of the differential pair 12 from the voltage regulator. Fig. 5 is a structural diagram of a comparator using two MOS transistors and a voltage regulator as a load according to an embodiment of the present disclosure, and fig. 6 is an equivalent structural diagram of a comparator using more MOS transistors and a voltage regulator as a load according to an embodiment of the present disclosure.

In other embodiments, a resistor may also be used as the load module 11, please refer to fig. 7, and fig. 7 is a circuit structure diagram of a comparator using a resistor as a load according to an embodiment of the present disclosure.

It can be seen that the load provided to the comparator 10 can be provided in a variety of ways, and the configuration of the load block 11 of the comparator 10 can be selected according to the circuit configuration of operation, improving the applicability of the comparator 10.

In some embodiments, the plurality of MOS transistors in the differential pair and the load module may be Bipolar transistors, silicon carbide (SiC) transistors, gallium nitride (GaN) transistors, cubic indium phosphide (InP) transistors, gallium arsenide (GaAs) transistors, Field Effect Transistors (FETs), Junction Field-Effect transistors (JFETs), Heterojunction Bipolar Transistors (HBTs), or Insulated Gate Bipolar Transistors (IGBTs).

For example, please refer to fig. 8, fig. 8 is a schematic diagram of a comparator with a bipolar transistor structure according to an embodiment of the present application. Based on the circuit structure of the comparator, an embodiment of the present application further provides a general structure of the comparator, please refer to fig. 9, and fig. 9 is a general structure diagram of the comparator according to the embodiment of the present application.

The comparator 10 may include: a first switch, a second switch and a differential pair 12, wherein the differential pair comprises a first inverting amplifier OPA1 and a second inverting amplifier OPA2, a first input terminal of the first inverting amplifier OPA1 and a second input terminal of the second inverting amplifier OPA2 are respectively used for receiving comparison signals, the first input terminal is connected with a second output terminal of the second inverting amplifier OPA2 through the first switch, and the second input terminal is connected with a first output terminal of the first inverting amplifier OPA1 through the second switch.

The first and second inverting amplifiers OPA1 and OPA2 are used for outputting an amplified voltage signal when a signal to be compared is received and the first and second switches are open, and outputting a comparison result when the first and second switches are both closed.

Wherein the first switch may be the switch S1, the second switch may be the switch S2, and the first inverting amplifier OPA1 and the second inverting amplifier OPA2 have identical gain (i.e., -Av), speed, and drive capabilities.

It should be understood that the embodiments of the comparator circuit structure provided in the present application are only illustrative, the circuit structure of the comparator may be specifically configured according to the circuit in which the comparator operates, and the protection scope of the present application should not be limited to the specific circuit structure presented in the embodiments of the present application.

Based on the same inventive concept, the comparator 10 provided in the embodiment of the present application can also be used as a sense amplifier for a small signal, and can be applied to analog-to-digital mixed signal processing, a memory, a micro power consumption sensor, and a Very Large Scale Integration (VLSI).

In a second aspect, the embodiment of the present application further provides an electronic device, where the comparator 10 in the foregoing implementation manner is disposed on the electronic device.

In the embodiments provided in the present application, it should be understood that the disclosed circuit structure may be implemented in other manners. The above-described embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and there may be other divisions in actual implementation, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

Alternatively, all or part of the implementation may be in software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, composition, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the principle, idea, spirit and principle of the present application shall be included in the protection scope of the present application.