阅读说明：本技术 半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 黄则尧 于 2020-06-22 设计创作，主要内容包括：本公开提供一种半导体结构及其制备方法。该半导体结构具有一基底；一漏极,配置在该基底中；一漏极接触点,配置在该漏极中；一源极,配置在该基底中；一源极接触点,配置在该源极中；一栅极结构,配置在该漏极与该源极之间,具有一底部；一通道,配置在该栅极结构的该底部,连接该漏极与该源极；一漏极应力源,配置在该漏极中并位于该栅极结构与该漏极接触点之间；一漏极应变硅层,配置在该基底中,并围绕该漏极应力源,且连接该通道；一源极应力源,配置在该源极中,并位于该源极接触点与该栅极结构之间；以及一源极应变硅层,配置在该基底中,并围绕该源极应力源,且连接该通道。(The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure has a substrate; a drain electrode disposed in the substrate; a drain contact disposed in the drain; a source electrode disposed in the substrate; a source contact disposed in the source; a gate structure disposed between the drain and the source, having a bottom; a channel disposed at the bottom of the gate structure and connecting the drain and the source; a drain stressor disposed in the drain and located between the gate structure and the drain contact; a drain strained Si layer disposed in the substrate and surrounding the drain stressor and connected to the channel; a source stressor disposed in the source and located between the source contact and the gate structure; and a source strained silicon layer disposed in the substrate, surrounding the source stressor, and connecting the channel.)

1. A semiconductor structure, comprising:

a substrate;

a drain electrode disposed in the substrate;

a drain contact disposed in the drain;

a source electrode disposed in the substrate;

a source contact disposed in the source;

a gate structure having a bottom, the gate structure disposed between the drain and the source;

a channel disposed at the bottom of the gate structure and connecting the drain and the source;

a drain stressor disposed in the drain and located between the gate structure and the drain contact;

a drain strained Si layer disposed in the substrate and surrounding the drain stressor and connected to the channel;

a source stressor disposed in the source and located between the source contact and the gate structure; and

a source strained silicon layer disposed in the substrate, surrounding the source stressor, and connecting the channel.

2. The semiconductor structure of claim 1, wherein said gate structure comprises a first conductive layer.

3. The semiconductor structure of claim 2, wherein said gate structure further comprises a gate isolation layer separating said first conductive layer of said gate structure from said source, said drain and said channel.

4. The semiconductor structure of claim 2, further comprising a metal suicide layer disposed on said first conductive layer of said gate structure.

5. The semiconductor structure of claim 1 further comprising a bit line connecting said drain contact.

6. The semiconductor structure of claim 5, wherein the bit line comprises a first electrode and a second electrode, the first electrode is connected to the drain contact, and the second electrode is connected to the first electrode.

7. The semiconductor structure of claim 5, further comprising a bit line isolation layer disposed on the bit line and a bit line spacer disposed on a sidewall of the bit line.

8. The semiconductor structure of claim 1, further comprising a storage node connected to said source contact.

9. The semiconductor structure of claim 8, wherein said storage node comprises a lower contact plug and an upper contact plug, said lower contact plug connecting said source contact, said upper contact plug disposed on said lower contact plug.

10. The semiconductor structure of claim 9, further comprising a storage capacitor having a landing pad disposed on said upper contact plug and a storage node spacer covering sidewalls of said storage node.

11. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a drain and a source in the substrate;

forming a gate structure having a bottom in the substrate and between the drain and the source to form a channel connecting the drain and the source, wherein the channel is disposed at the bottom of the gate structure;

forming a drain strained silicon layer and a source strained silicon layer by forming a drain stressor in the drain and a source stressor in the source, wherein the drain strained silicon layer and the source strained silicon layer are connected through the channel; and

forming a drain contact in the drain and a source contact in the source, wherein the drain stressor is disposed between the drain contact and the gate structure and the source stressor is disposed between the source contact and the gate structure.

12. The method of claim 11, wherein the substrate comprises silicon.

13. The method of claim 12, wherein said drain stressor and said source stressor comprise silicon germanium.

14. A method of fabricating a semiconductor structure as claimed in claim 11, further comprising: a bit line is formed over the drain contact.

15. The method of claim 14, wherein the step of forming the bit line comprises the steps of:

forming a first electrode connected to the drain contact; and

forming a second electrode connected to the first electrode.

16. A method of fabricating a semiconductor structure as claimed in claim 15, further comprising the steps of:

forming a bit line isolation layer on the second electrode; and

a bit line spacer is formed on a sidewall of the bit line.

17. A method of fabricating a semiconductor structure as claimed in claim 15, further comprising: a storage node is formed over the source contact.

18. The method of fabricating a semiconductor structure according to claim 17, wherein the step of forming the storage node above the source contact comprises:

forming a lower contact plug above the source contact; and

an upper contact plug is formed over the lower contact plug.

19. The method of claim 18, wherein the lower contact plug is integrally formed with the first electrode of the bit line, and the upper contact plug is integrally formed with the second electrode of the bit line.

20. The method of fabricating a semiconductor structure according to claim 11, wherein the step of forming the gate structure comprises the steps of:

forming a gate trench in the substrate;

forming a gate isolation layer in the gate trench;

forming a first conductive layer in the gate trench and on the gate isolation layer; and

a second conductive layer is formed on the first conductive layer.

Technical Field

This application claims priority and benefit of us official application No. 16/547,331, filed on 21/08/2019, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure and a method for fabricating the same. More particularly, to a semiconductor structure having strained silicon and a method for fabricating the same, the semiconductor structure having a buried gate, a buried source, and a plurality of drain contacts.

Background

Semiconductor devices are widely used in the electronics industry because of their small size, multi-functional characteristics, and/or low manufacturing cost. Reducing the size of semiconductor devices results in improved performance, increased capacity, and/or reduced cost. However, semiconductor devices have been highly integrated during the advancement of the electronics industry. The width and space of patterns included in semiconductor devices have been reduced to increase the integration density of semiconductor devices. However, the reduction in size requires more complex integrated circuit fabrication techniques. The more difficult it is in continuous highly integrated semiconductor devices due to the need for new and/or expensive exposure techniques to form fine patterns. In order to continue to shrink the specifications of semiconductor devices, many techniques have been proposed in recent years for the development of future generations.

Furthermore, strained silicon (strained silicon) has been used to improve the performance of semiconductor devices. Strained silicon is a layer of silicon in which silicon atoms extend beyond the internal atomic distance (inter distance). Moving these atoms more apart reduces the atomic forces (atomic forces) that interfere with the electrons passing through the transistor, thereby improving carrier mobility, which results in better wafer performance and lower energy consumption. This may be accomplished by placing the silicon layer over a substrate, for example, a substrate comprising silicon germanium (SiGe), wherein the atomic arrangement of the SiGe substrate is spaced further apart than that of a silicon substrate.

The above "background" description merely provides background, and no admission is made that the above "background" description discloses subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of the above "background" should not be taken as an admission that such disclosure is prior art to the present disclosure.

Disclosure of Invention

According to an aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes: a substrate; a drain electrode disposed in the substrate; a drain contact disposed in the drain; a source electrode disposed in the substrate; a source contact disposed in the source; a gate structure having a bottom, the gate structure disposed between the drain and the source; a channel disposed at the bottom of the gate structure and connecting the drain and the source; a drain stressor disposed in the drain and located between the gate structure and the drain contact; a drain strained Si layer disposed in the substrate and surrounding the drain stressor and connected to the channel; a source stressor disposed in the source and located between the source contact and the gate structure; and a source strained silicon layer disposed in the substrate, surrounding the source stressor, and connecting the channel. In some embodiments of the present disclosure, the gate structure includes a first conductive layer.

In some embodiments of the present disclosure, the gate structure further includes a gate isolation layer separating the first conductive layer of the gate structure from the source, the drain, and the channel.

In some embodiments of the present disclosure, the semiconductor structure further comprises a metal silicide layer disposed on the first conductive layer of the gate structure.

In some embodiments of the present disclosure, the semiconductor structure further comprises a bit line connected to the drain contact.

In some embodiments of the present disclosure, the bit line includes a first electrode connected to the drain contact and a second electrode connected to the first electrode.

In some embodiments of the present disclosure, the semiconductor structure further includes a bit line isolation layer disposed on the bit line and a bit line spacer disposed on a sidewall of the bit line.

In some embodiments of the present disclosure, the semiconductor structure further comprises a storage node connected to the source contact.

In some embodiments of the present disclosure, the storage node includes a lower contact plug connected to the source contact and an upper contact plug disposed on the lower contact plug.

In some embodiments of the present disclosure, the semiconductor structure further comprises a storage capacitor having a landing pad disposed on the upper contact plug and a storage node spacer covering sidewalls of the storage node.

According to another aspect of the present disclosure, a method of fabricating a semiconductor structure is provided. The preparation method comprises the following steps: providing a substrate; forming a drain and a source in the substrate; forming a channel connecting the drain and the source by forming a gate structure having a bottom in the substrate and between the drain and the source, wherein the channel is disposed at the bottom of the gate structure; forming a drain strained silicon layer and a source strained silicon layer by forming a drain stressor in the drain and a source stressor in the source, wherein the drain strained silicon layer and the source strained silicon layer are connected through the channel; and forming a drain contact in the drain and a source contact in the source, wherein the drain stressor is disposed between the drain contact and the gate structure and the source stressor is disposed between the source contact and the gate structure.

In some embodiments of the present disclosure, the substrate comprises silicon.

In some embodiments of the present disclosure, the drain stressor and the source stressor comprise silicon germanium.

In some embodiments of the present disclosure, the method of fabricating the semiconductor structure further comprises: a bit line is formed over the drain contact.

In some embodiments of the present disclosure, the step of forming the bit line includes the steps of: forming a first electrode connected to the drain contact; and forming a second electrode connected to the first electrode.

In some embodiments of the present disclosure, the method of fabricating the semiconductor structure further comprises the steps of: forming a bit line isolation layer on the second electrode; and forming a bit line spacer on a sidewall of the bit line.

In some embodiments of the present disclosure, the method of fabricating the semiconductor structure further comprises: a storage node is formed over the source contact.

In some embodiments of the present disclosure, the step of forming the storage node above the source contact comprises: forming a lower contact plug above the source contact; and forming an upper contact plug over the lower contact plug.

In some embodiments of the present disclosure, the lower contact plug is integrally formed with the first electrode of the bit line, and the upper contact plug is integrally formed with the second electrode of the bit line.

In some embodiments of the present disclosure, the step of forming the gate structure comprises the steps of: forming a gate trench in the substrate; forming a gate isolation layer in the gate trench; forming a first conductive layer in the gate trench and on the gate isolation layer; and forming a second conductive layer on the first conductive layer.

The semiconductor structure of the present disclosure has a gate structure disposed in a gate trench; that is, the gate is buried in the substrate. The buried gate is completely buried under the surface of the substrate so that the sequentially formed structures can be at the same level as the top surface of the substrate, which results in a structure with smaller dimensions. Furthermore, the drain contact and the source contact are also embedded in the substrate and located below the surface of the substrate, which further enables size reduction.

In the present disclosure, the drain stressor and the source stressor serve to increase the interatomic spacing of the substrate, and thus also produce a layer having a strained silicon layer. The mobility of the carriers in the strained silicon layer may be significantly greater than that of conventional silicon layers. Combining the features of the buried gate structure and the plurality of buried contacts results in a product with better performance, lower energy consumption and better reliability.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure.

Drawings

The disclosure may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to further embodiments of the present disclosure.

Fig. 3 is a schematic flow chart of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 4-13 are schematic cross-sectional views of steps of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Description of reference numerals:

100 semiconductor structure

100a semiconductor structure

110 base

112 gate trench

114a drain stressor recess

114b source stressor recess

116a drain contact hole

116b source contact hole

120a drain electrode

120b source electrode

130 gate structure

132 first conductive layer

134 gate isolation layer

136 second conductive layer

138 bottom part

140a source of drain stressor

140b source stressor

142a strained silicon layer of drain

142b source strained silicon layer

150: channel

160a drain contact

160b source contact

170 bit line

171 first electrode

173 second electrode

175 bit line isolation layer

177 bit line spacer

180 storage node

181 lower contact pin

183 Upper contact pin

185 landing pad

187 storage node spacers

190 storage capacitor

191 lower electrode

193 upper electrode

195 dielectric layer

S11 step

S13 step

S15 step

S17 step

S19 step

Detailed Description

Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These repetitions are for simplicity and clarity and do not, in themselves, represent a particular relationship between the various embodiments and/or configurations discussed, unless specifically stated in the context.

Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the components in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. Please refer to fig. 1. The semiconductor structure 100 provided by the present disclosure includes a substrate 110. A drain 120a and a source 120b are disposed in the substrate 110. The semiconductor structure 100 further includes a gate structure 130 disposed in the substrate 110 and between the drain 120a and the source 120 b. In one embodiment, the gate structure 130 is a combination of a first conductive layer 132, a gate isolation layer 134 and a second conductive layer 136. The gate structure 130 results in the formation of a channel 150, the channel 150 being located at a bottom 138 of the gate structure 130 in the substrate 110. The channel 150 connects the drain 120a and the source 120 b. The gate structure 130 is mainly disposed in the substrate 110, so that the semiconductor structure 100 has a more compact structure.

A drain stressor 140a and a source stressor 140b are also disposed in the drain 120a and in the source 120b, respectively. Because the crystalline structure of the drain stressor 140a and the source stressor 140b have a relatively wide internal atomic space (inter space), the internal atomic space of the portion of the drain 120a surrounding the drain stressor 140a and the internal atomic space of the portion of the source 120b surrounding the source stressor 140b are extended. For example, in one embodiment, the substrate 110 may be a silicon substrate, and the drain stressor 140a and the source stressor 140b may be made of silicon germanium (SiGe). The wider inter-atomic space of sige affects the surrounding silicon crystal structure and creates a strained si layer 142a and a strained si layer 142b at the drain 120a and the source 120b, respectively. The wider inter-atom space in the drain strained silicon layer 142a and the source strained silicon layer 142b allows carriers to move in these regions with less interference with surrounding atoms, thereby also improving carrier mobility in the drain strained silicon layer 142a and the source strained silicon layer 142 b.

The semiconductor structure 100 further includes a drain contact 160a and a source contact 160b disposed in the drain 120a and the source 120b, respectively. The drain contact 160a and the source contact 160b are respectively buried in the drain 120a and the source 120b, which further reduces the overall size of the semiconductor structure 100. In some embodiments, when the semiconductor structure 100 is used in a semiconductor memory device, the drain contact 160a may be connected to a bit line and the source contact 160b may be connected to a storage node.

Fig. 2 is a schematic cross-sectional view of a semiconductor structure 100a according to some other embodiments of the present disclosure. Please refer to fig. 2. When integrated into a semiconductor memory device, the semiconductor structure 100a in the present disclosure includes a bit line 170 and a storage node 180 respectively connecting the drain contact 160a and the source contact 160 b. In some embodiments of the present disclosure, the bit line 170 may include a first electrode 171 and a second electrode 173, the first electrode 171 is connected to the drain contact 160a in the drain 120a, and the second electrode 173 is disposed on the first electrode 171. In one embodiment, the semiconductor structure 100a may further include a bit line isolation layer 175 and a bit line spacer 177, the bit line isolation layer 175 is disposed on the second electrode 173, and the bit line spacer 177 covers sidewalls of the bit line 170. In some embodiments, the storage node 180 is configured to connect the source contact 160b to a storage capacitor (not shown), and may have a lower contact plug 181 and an upper contact plug 183. The lower contact plug 181 is connected to the source contact 160b, and the upper contact plug 183 is disposed on the lower contact plug 181. In one embodiment, the upper contact plug 183 of the storage node 180 contacts a landing pad 185, the landing pad 185 is disposed on the upper contact plug 183, and a storage node spacer 187 covers the side of the storage node 180 and the landing pad 185.

The semiconductor structure 100 and the method of fabricating the semiconductor structure 100a are described as follows. Fig. 3 is a schematic flow chart of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure, and fig. 4-13 are schematic cross-sectional views of steps of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. Please refer to fig. 3 and fig. 4. In step S11 of the method for fabricating the semiconductor structure 100, a substrate 110 is provided. The substrate 110 may be a bulk silicon substrate (bulk silicon substrate) or a silicon-on-insulator (SOI) substrate.

Please refer to fig. 5. In step S13, a drain 120a and a source 120b are formed in the substrate 110. In some embodiments, the substrate 110 may be doped to form the drain 120a and the source 120 b. For example, the substrate 110 may be implanted using a diffusion implantation process (diffusion implantation) in which a gas containing a dopant is introduced into the substrate 110, or an ion implantation process (ion implantation) in which the dopant is vertically and horizontally diffused into the exposed surface of the substrate 110; the ion implantation directs a beam of pure dopant ions to scan across the surface of the substrate 110 and coat its exposed surface. In some embodiments, an ion implantation mask (not shown) may be formed on the substrate 110, and an ion implantation process may be performed using the ion implantation mask to form the drain electrode 120a and the source electrode 120 b. In some embodiments, the ion implantation process may be performed without an ion implantation mask.

Next, in step S15, a gate structure 130 is formed in the substrate 110 between the drain 120a and the source 120 b. In some embodiments, the formation of the gate structure 130 may also include a number of steps. For example, referring to fig. 6, a gate trench 112 is formed on the substrate 110 and between the drain 120a and the source 120 b. In some embodiments, the gate trench 112 may be formed by selective etching. For example, in an embodiment where the substrate 110 is a silicon substrate, the substrate 110 may be vapor hydrofluoric acid (VHF) etched.

Next, referring to fig. 7, a gate isolation layer 134 is formed in the gate trench 112. For example, the gate isolation layer 134 may be formed to cover an inner surface of the gate trench 112. The gate isolation layer 134 may be formed of an isolation material, such as a silicon oxide layer. In some embodiments, the gate isolation layer 134 may be formed by performing a thermal process on the substrate 100, wherein the thermal process oxidizes the exposed surface of the substrate 110 and forms a passivation oxide layer on the substrate 110, which includes the inner surface of the gate trench 112.

Next, in fig. 8, a first conductive layer 132 is formed in the gate trench 112 and on the gate isolation layer 134. In some embodiments, the first conductive layer 132 can be formed by depositing a metal layer (not shown) on the substrate 110 and in the gate trench 112, and then processing the metal layer until the metal layer is not higher than the surface of the substrate 110 and the remaining metal layer is only in the gate trench 112. In this case, the metal layer may comprise, for example, a titanium nitride layer, a tantalum nitride layer, a tungsten layer, or the like. The metal layer may then be planarized by Chemical Mechanical Polishing (CMP) or the like. Next, the metal layer is etched back and cleaned in such a manner that the metal layer is buried only in some portions of the gate trench, so that the first conductive layer 132 is formed. In some embodiments, the first conductive layer 132 may also be a non-metal, such as polysilicon. In such embodiments, a polysilicon layer (not shown) may be formed on the surface of the substrate 110 and in the gate trench 112 by Low Pressure Chemical Vapor Deposition (LPCVD). The polysilicon layer on the surface of the substrate 110 is then planarized back or by chemical mechanical polishing so that only the polysilicon layer in the gate trench 112 remains, thus forming the first conductive layer 132. By forming the first conductive layer 132, a channel 150 is defined at the bottom 138 of the gate structure 130. The channel 150 connects the drain 120a and the source 120 b.

In some embodiments, a second conductive layer 135 can be formed on the first conductive layer 132. Please refer to fig. 9. In some embodiments, the gate structure 130 may further include a second conductive layer 136 formed on the first conductive layer 132. In some embodiments where the first conductive layer 132 is a metal, the second conductive layer 136 may be formed by depositing a titanium nitride layer and a tantalum nitride layer, or for example, by sequentially depositing a titanium nitride layer, a tantalum nitride layer, and a tungsten layer to form the first conductive layer 132 and the second conductive layer 136. In some other embodiments where the first conductive layer 132 is polysilicon, the second conductive layer 136 can be a metal silicide layer.

Next, in step S17, drain stressor 140a and source stressor 140b are formed in drain 120a and source 120b, respectively. In some embodiments, step S17 may further include forming a drain stressor recess 114a and a source stressor recess 114 b. The formation of the drain stressor recesses 114a and the source stressor recesses 114b may be accomplished by a selective etch in some embodiments. For example, a hard mask (not shown) may be formed in a photolithography process, the hard mask defining the drain stressor recesses 114a and the source stressor recesses 114 b; for example, the drain stressor recesses 114a and the source stressor recesses 114b may be formed using a wet etch process that is selective to the material of the substrate 110, wherein the wet etch process uses a hard mask to form the drain stressor recesses 114a and the source stressor recesses 114 b. For example, the wet etching process may be performed using an etchant (etchant) such as carbon tetrafluoride (CF 4), tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, and the drain stressor recess 114a and the source stressor recess 114b are formed.

Next, drain stressors 140a and source stressors 140b are formed in the drain stressor recesses 114a and the source stressor recesses 114b, respectively. Please refer to fig. 10 and fig. 11. In some embodiments, drain stressor 140a and source stressor 140b may be formed by a Cyclic Deposition and Etching (CDE) process. The CDE process includes an epitaxial deposition/partial etch process that is repeated one or more times. In this example, a silicon-containing layer (not shown) is epitaxially deposited in the drain stressor recess 114a and the source stressor recess 114 b. In some embodiments, the Metal Oxide Semiconductor (MOS) device produced is an nMOS device, and the silicon-containing layer can be formed of, for example, silicon carbide, other semiconductor materials, and-Or a combination thereof. The silicon-containing layer may be deposited using at least one silicon-containing precursor (e.g., silane, SiH)₄) Trisilane (Si)₃H₈) Disilane (Si)₂H₆) Dichlorosilane (SiH)₂Cl₂) Other silicon-containing precursors, and/or combinations thereof. In some embodiments, the deposition of the silicon-containing layer may include in-situ doping of the silicon-containing layer. When the MOS device is an nMOS device, an n-type dopant precursor, such as Phosphine (PH), can be used₃) And/or other n-type dopant precursors. As a result, a drain strained silicon layer 142a and a source strained silicon layer 142b are formed in the drain 120a and the source 120b, respectively.

Finally, in step S19, as shown in fig. 12 and 1, a drain contact 160a is formed in the drain 120a and a source contact 160b is formed in the source 120 b. In some embodiments, the substrate 110 may be etched to form a drain contact hole 116a and a source contact hole 116 b. Next, a conductive layer may be formed on the substrate 110 and in the drain contact hole 116a and the source contact hole 116 b. In some embodiments, a planarization process (e.g., CMP) or an etch-back process may be performed on the conductive layer until only the conductive layer remains in the drain and source contact holes 116a and 116b, thereby forming the drain and source contacts 160a and 160 b. The drain contact 160a and the source contact 160b may include at least one of: a metal silicide, doped polysilicon, a metal nitride, or a metal.

Please refer to fig. 13. In some embodiments, when the semiconductor structure 100 is used in a semiconductor memory device, a bit line 170 and a storage node 180 may be formed, the bit line 170 being connected to the drain contact 160a, and the storage node 180 being connected to the source contact 160 b. In some embodiments, the bit line 170 may have a first electrode 171 and a second electrode 173 sequentially stacked on the drain contact 160 a. For example, the first electrode 171 may include doped polysilicon. The second electrode 173 may include at least one of: tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co). In one embodiment, a diffusion barrier layer (not shown) may be formed between the first electrode 171 and the second electrode 173. The diffusion barrier layer may be a diffusion barrier metal, which may comprise TiN, Ti/TiN, TiSiN, TaN, or WN, for example. In some embodiments, the semiconductor structure 100a may further include a bit line isolation layer 175 and a bit line spacer 177, the bit line isolation layer 175 is disposed on the second electrode 173, and the bit line spacer 177 covers sidewalls of the bit line 170.

In some embodiments, a storage node 180 may be formed in connection with the source contact 160 b. For example, the storage node 180 may include a lower contact plug 181 and an upper contact plug 183, the upper contact plug 183 disposed on the lower contact plug 181. The storage node 180 may be formed in a process similar to the process of forming the bit line 170, for example, the lower contact plug 181 is integrally formed with the first electrode 171 of the bit line 170, and the upper contact plug 183 is integrally formed with the second electrode 173 of the bit line 170. In some embodiments, a landing pad 185 is formed on the storage node 180, and then a storage node spacer 187 is formed to cover the sidewalls of the storage node 180. In some embodiments, a storage capacitor 190 is disposed on the landing pad 185 and has a lower electrode 191, an upper electrode 193, and a dielectric layer 195, the dielectric layer 195 being disposed between the lower electrode 191 and the upper electrode 193.

The gate structure 130 is disposed in the gate trench 112 in the substrate 110, the drain contact 160a is disposed in the drain contact hole 116a, and the source contact 160b is disposed in the source contact hole 116 b. That is, the gate structure 130, the drain contact 160a, and the source contact 160b are embedded in the substrate 110 and located below the surface of the substrate 110. The multiple buried portions reduce the height of the semiconductor structure 100 so that other semiconductor structures formed on the semiconductor structure 100 may be formed with a tighter profile.

Further, drain stressor 140a and source stressor 140b create drain strained silicon layer 142a and source strained silicon layer 142b in drain 120a and source 120b, respectively. The ions of the drain strained silicon layer 142a and the source strained silicon layer 142b are further separated from each other by the extension of the drain stressor 140a and the source stressor 140b, which leaves carriers with a larger internal atomic space. The carriers are thus less susceptible to internal atomic forces (interactions) when moving in the drain strained silicon layer 142a and the source strained silicon layer 142b resulting in better mobility of the carriers in these regions. In combination with this feature of the buried gate, the product has lower cost, more functions, higher performance, lower energy consumption and better reliability.

The present disclosure provides a semiconductor structure comprising: the device comprises a substrate, a drain electrode contact point, a source electrode contact point, a grid structure and a channel. The drain and the source are disposed in the substrate, and the drain contact is disposed in the drain while the source contact is disposed in the source. The grid structure is provided with a bottom and arranged in the substrate and is positioned between the drain electrode and the source electrode. The channel is arranged at the bottom of the grid structure and is connected with the drain electrode and the source electrode. The semiconductor structure further includes a drain stressor, a drain strained silicon layer, a source stressor, and a source strained silicon layer. A drain stressor is disposed in the drain and between the gate structure and the drain contact. The source stressor is disposed in the source and between the source contact and the gate structure. The drain strained silicon layer is disposed in the substrate and surrounds the drain stressor, and connects the channel. The source strained silicon layer is disposed in the substrate and surrounds the source stressor, and connects the channel.

The present disclosure further provides a method for fabricating a semiconductor structure. The method begins with the step of providing a substrate. Then, a drain and a source are formed in the substrate. Then, a gate structure with a bottom is formed in the substrate and between the drain and the source to form a channel connecting the drain and the source. The channel is configured at the bottom of the gate structure. Then, a drain strained silicon layer and a source strained silicon layer are formed by forming a drain stressor in the drain and a source stressor in the source. The drain strained silicon layer is in channel connection with the source strained silicon layer. Finally, a drain contact and a source contact are formed on the drain and the source, respectively. The drain stressor is disposed between the drain contact and the gate structure, and the source stressor is disposed between the source contact and the gate structure.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are intended to be included within the scope of the present claims.