阅读说明：本技术 负微分电阻电路以及神经元晶体管结构 (Negative differential resistance circuit and neuron transistor structure ) 是由 唐可忱 赵帆 于 2020-11-09 设计创作，主要内容包括：本发明公开了一种神经元晶体管结构,包括：权重加和电路,包括并联的至少两个突触部、第一负微分电阻；各突触部的源极与第一负微分电阻的发射极分别连接至神经元晶体管的输出端；各突触部的漏极与第一负微分电阻的集电极分别连接至神经元晶体管的时钟电源端；阈值电路,包括突触缩放控制部和第二负微分电阻；突触缩放控制部的漏极与神经元晶体管的输出端连接、突触缩放控制部的源极与第二负微分电阻连接地；第一负微分电阻的发射极端与第二负微分电阻的集电端连接以作为神经元晶体管输出端；解决了现有技术中神经元晶体管功耗大的问题,优化了人工智能芯片的内部构造,以大幅度减少人工智能芯片的面积。(The invention discloses a neuron transistor structure, comprising: a weight summing circuit comprising at least two synapses connected in parallel, a first negative differential resistance; the source electrode of each synapse part and the emitter electrode of the first negative differential resistance are respectively connected to the output end of the neuron transistor; the drain electrode of each synapse part and the collector electrode of the first negative differential resistance are respectively connected to a clock power supply end of the neuron transistor; a threshold circuit comprising a synapse scaling control and a second negative differential resistance; the drain electrode of the synapse scaling control part is connected with the output end of the neuron transistor, and the source electrode of the synapse scaling control part is connected with the second negative differential resistance; the emitter end of the first negative differential resistor is connected with the collector end of the second negative differential resistor to serve as the output end of the neuron transistor; the problem of neuron transistor consumption among the prior art big is solved, the internal structure of artificial intelligence chip has been optimized to reduce artificial intelligence chip's area by a wide margin.)

1. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is characterized by at least comprising one or more than one folded insertion finger structures, and the MOSFET comprises:

a P-type substrate;

at least 3 active regions which are sequentially arranged at intervals and formed in the P-type substrate;

a gate layer over the substrate region spaced between each two active regions; the MOS structure corresponding to each grid layer is defined as an insertion structure;

wherein a portion of the spaced active regions are electrically connected to each other to form source regions, the remaining spaced active regions are electrically connected to each other to form drain regions, and all gate layers are electrically connected to each other.

2. The mosfet of claim 1, wherein the number of active regions is odd, thereby forming an even number of fingers.

3. A negative differential resistance circuit structure provided with an emitter terminal, a collector terminal and a base terminal, comprising:

the self grid electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the base electrode terminal and is connected with the self drain electrode;

the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end;

and the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal.

4. The negative differential resistance circuit structure of claim 3, wherein the second N-channel MOSFET and the third N-channel MOSFET are the MOSFETs of claims 1 or 2.

5. The negative differential resistance circuit arrangement of claim 3, further comprising:

and the grid electrode and the drain electrode of the fourth N-channel metal oxide semiconductor field effect transistor are connected to the collector terminal, and the source electrode of the fourth N-channel metal oxide semiconductor field effect transistor is connected to the emitter terminal.

6. A neuron transistor structure applied to a neural network is characterized by comprising:

a weight summing circuit comprising at least two synapses connected in parallel, a first negative differential resistance; and each synapse part is an N-channel metal oxide semiconductor field effect transistor with different grid widths; the source electrode of each synapse part and the emitter electrode of the first negative differential resistance are respectively connected to the output end of the neuron transistor; the drain electrode of each synapse part and the collector electrode of the first negative differential resistance are respectively connected to a clock power supply end of the neuron transistor;

a threshold circuit comprising a synapse scaling control and a second negative differential resistance; the drain electrode of the synapse scaling control part is connected with the output end of the neuron transistor, and the source electrode of the synapse scaling control part is connected with the second negative differential resistance;

the emitter terminal of the first negative differential resistor is connected with the collector terminal of the second negative differential resistor to serve as a neuron transistor output terminal.

7. The neuron transistor structure of claim 6, wherein the at least two synapses comprise: a first synapse portion, a second synapse portion through an ith synapse portion; and the ratio of the gate width of the N-channel metal oxide semiconductor field effect transistor from the first synapse part to the second synapse part to the ith synapse part is 1:2: … … 2^i-1Wherein i is greater than or equal to 3.

8. The neuron transistor structure of claim 7, wherein the first synapse portion, the second synapse portion, and up to the ith synapse portion employ metal-oxide-semiconductor field-effect transistors of claims 1 or 2.

9. The neuron transistor structure of claim 8, wherein the neural network comprises at least one neuron transistor.

10. A method of using a neuron transistor with the neuron transistor structure according to any one of claims 6-8, comprising:

inputting a clock signal from a neuron transistor clock power supply terminal;

inputting a weight control signal from a synapse;

carrying out weighted summation on the weight control signals, comparing the weighted summation with a preset threshold, outputting a high level when the weighted summation is greater than the preset threshold, and outputting a low level when the weighted summation is less than the preset threshold;

according to the output voltage, a threshold voltage of a synapse scaling control may be adjusted to achieve synapse scaling.

Technical Field

The invention relates to the technical field of neuron transistors, in particular to a negative differential resistance circuit and a neuron transistor structure.

Background

An AGI chip has a very wide application prospect in specific tasks such as image classification, language processing, voice recognition and the like. Non-spiking Artificial Neural Networks (ANNS), inspired by brain structures, are currently the focus of research.

The technical problems existing in the using process of ANNS chips in the prior art are as follows: firstly, the method comprises the following steps: the occupied area of the chip is large, and the power consumption ratio of the artificial neuron transistor is large; secondly, the method comprises the following steps: the AGI chip has a von Neumann structure, and the function of threshold operation after weighted summation of biological neurons is realized based on the existing digital circuit theory, so that the circuit structure is relatively complex.

Therefore, it is important to design a neuron transistor circuit without a capacitor structure based on a negative differential resistance with a finger insertion structure, and to implement a general artificial intelligence neural network by interconnecting a plurality of neuron transistor circuits.

Disclosure of Invention

The invention mainly aims to provide a negative differential resistance circuit and a neuron transistor structure based on the negative differential resistance circuit, and aims to solve the problems that a general artificial intelligent chip in the prior art occupies a large area, an artificial neuron transistor is large in power consumption ratio and low in response speed.

In order to achieve the above object, the present invention provides a mosfet, which at least includes a folded finger structure, and the mosfet includes:

a P-type substrate;

at least 3 active regions which are sequentially arranged at intervals and formed in the P-type substrate;

a gate layer over the substrate region spaced between each two active regions; the MOS structure corresponding to each grid layer is defined as an insertion structure;

wherein a portion of the spaced active regions are electrically connected to each other to form source regions, the remaining spaced active regions are electrically connected to each other to form drain regions, and all gate layers are electrically connected to each other.

In one embodiment, the number of active regions is odd, thereby forming an even number of interdigitated structures.

To achieve the above object, the present invention further provides a negative differential resistance circuit structure, which has an emitter terminal, a collector terminal, and a base terminal, and includes:

the self grid electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the base electrode terminal and is connected with the self drain electrode;

the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end;

and the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal.

In an embodiment, the second N-channel mosfet and the third N-channel mosfet are both the aforementioned mosfets.

In one embodiment, the negative differential resistance circuit structure further includes:

and the grid electrode and the drain electrode of the fourth N-channel metal oxide semiconductor field effect transistor are connected to the collector terminal, and the source electrode of the fourth N-channel metal oxide semiconductor field effect transistor is connected to the emitter terminal.

In order to achieve the above object, the present invention further provides a neuron transistor structure applied in a neuron network, including: a weight summing circuit comprising at least two synapses connected in parallel, a first negative differential resistance; and each synapse part is an N-channel metal oxide semiconductor field effect transistor with different grid widths; the source electrode of each synapse part and the emitter electrode of the first negative differential resistance are respectively connected to the output end of the neuron transistor; the drain electrode of each synapse part and the collector electrode of the first negative differential resistance are respectively connected to a clock power supply end of the neuron transistor;

a threshold circuit comprising a synapse scaling control and a second negative differential resistance; the drain electrode of the synapse scaling control part is connected with the output end of the neuron transistor, and the source electrode of the synapse scaling control part is connected with the second negative differential resistance;

the emitter terminal of the first negative differential resistor is connected with the collector terminal of the second negative differential resistor to serve as a neuron transistor output terminal.

In an embodiment, the at least two synapses comprise: a first synapse portion, a second synapse portion through an ith synapse portion; and the ratio of the gate width of the N-channel metal oxide semiconductor field effect transistor from the first synapse part to the second synapse part to the ith synapse part is 1:2: … … 2^i-1Wherein i is greater than or equal to 3.

In an embodiment, the metal oxide semiconductor field effect transistor is adopted in the first synapse part, the second synapse part and up to the ith synapse part.

In one embodiment, the neuron network structure comprises at least one neuron transistor.

In order to achieve the above object, the present invention further provides a method for applying a neuron transistor, which is applied to the neuron transistor structure described in any one of the above, the method comprising:

inputting a clock signal from a neuron transistor clock power supply terminal;

inputting a weight control signal from a synapse;

carrying out weighted summation on the weight control signals, comparing the weighted summation with a preset threshold, outputting a high level when the weighted summation is greater than the preset threshold, and outputting a low level when the weighted summation is less than the preset threshold;

according to the output voltage, a threshold voltage of a synapse scaling control may be adjusted to achieve synapse scaling.

The technical scheme of the negative differential resistance circuit and the neuron transistor structure provided in the embodiment of the application at least has the following technical effects:

1. because a negative differential resistor is adopted, the connection relationship of the internal circuit of the negative differential resistor is as follows: the self grid electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the base electrode terminal and is connected with the self drain electrode; the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end; and the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal, so that the negative differential resistor with the emitter terminal, the collector terminal and the base terminal is formed, the problem of large occupied area of a chip in the prior art is solved, and the occupied area of the chip is reduced by reducing the number of the metal oxide semiconductor field effect.

2. Because a neuron transistor structure is adopted, the neuron transistor adopts a weight summation circuit and a threshold summation circuit, and a neuron transistor circuit without a capacitor structure is designed by using a negative differential resistor with an insertion finger structure, the problem of complex circuit structure in the prior art is solved, the response speed of the neuron transistor is improved, and the power consumption of the neuron is reduced

Drawings

FIG. 1 is a schematic diagram of a MOSFET structure;

FIG. 2 is a schematic diagram of a MOSFET finger structure;

FIG. 3 is a schematic diagram of the circuit structure connection of the inverted V-shaped negative differential resistor;

FIG. 4 is a schematic diagram of the connection of the circuit structure of the N-type negative differential resistor;

FIG. 5 is a schematic diagram of the operation of a neuron transistor;

FIG. 6 is a schematic diagram of a circuit structure of a neuron transistor;

FIG. 7 is a schematic diagram of the application flow of a neuron transistor;

the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

This application has adopted a neuron transistor structure in order to solve the big problem of neuron transistor consumption among the prior art, includes: a weight summing circuit comprising at least two synapses connected in parallel, a first negative differential resistance; and each synapse part is an N-channel metal oxide semiconductor field effect transistor with different grid widths; the source electrode of each synapse part and the emitter electrode of the first negative differential resistance are respectively connected to the output end of the neuron transistor; the drain electrode of each synapse part and the collector electrode of the first negative differential resistance are respectively connected to a clock power supply end of the neuron transistor; a threshold circuit comprising a synapse scaling control and a second negative differential resistance; the drain electrode of the synapse scaling control part is connected with the output end of the neuron transistor, and the source electrode of the synapse scaling control part is connected with the second negative differential resistance; the emitter terminal of the first negative differential resistor is connected with the collector terminal of the second negative differential resistor to serve as the output terminal of the neuron transistor; the application also adopts the metal oxide field effect transistor with the finger inserting structure, the negative differential resistance circuit structure and the application method of the neuron transistor, so that the problem of high power consumption of the neuron transistor is solved, the internal structure of the artificial intelligent chip is optimized, and the area of the artificial intelligent chip is greatly reduced.

For a better understanding of the above technical solutions, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As shown in fig. 1, the operation principle of the mosfet of fig. 1 is as follows:

current I from drain region to source region_DSSee the formula:

I_DS＝Q_DSv

wherein Q is_DSIs the charge density in the direction of current flow, in units of C/m; v is the speed of movement of the charge, in unitsIs m/s.

Q_DS＝WC_ox(U_G-U_TH)

In fig. 1, W is the width of the mosfet and is expressed in m; c_oxMultiplied by W denotes the total capacitance, C_oxThe unit of (A) is C/m; u shape_GIs the voltage of the gate, in units of V; u shape_THIs the gate voltage when the in-channel electron concentration is equal to the hole concentration when the P-type substrate is not biased, also referred to as the threshold voltage, and has the unit V.

When the drain region voltage is greater than zero, the channel potential is 0V at the source region to the drain region U_DSo that the local voltage difference between the gate region and the channel is in U_GTo (U)_G-U_D) The charge density at the x point of the channel can be written as:

Q_DS(x)＝WC_ox[U_G-U(x)-U_TH]

where U (x) is the potential at x in the channel.

From formula I_DS＝Q_DSv knowing the drain to source current I_DSComprises the following steps:

I_DS＝-WC_ox[U_G-U(x)-U_TH]v

in the trench shown in FIG. 1, "-" is inserted because this is a P-type substrate, so at gate voltage U_GUnder the action of (1), the channel is inverted, the carrier in the channel is electrons, v is the electron velocity in the channel:

v＝μ_nE

μ_Nis the electron mobility, E is the electric field, see formula:

E(x)＝-dU/dx

when the boundary condition is satisfied, U (0) is 0, and U (l) is U_DS. Multiplying two sides by dx simultaneously, and integrating to obtain:

it can be seen that I_DSProportional to W, i.e.:

therefore, when W is larger, the mosfet is made into a folded finger structure, and when W of each finger is fixed, the number of fingers determines the total W of the mosfet, and at the same time, the number of fingers controls the weight of the neuron transistor, and the specific control method is described in the neuron transistor structure part, and is not described herein again.

As an implementation manner, as shown in fig. 2, fig. 2 is a schematic diagram of a mosfet finger structure, where the mosfet at least includes one or more folded finger structures, and the folded finger structures can reduce the resistance of a gate and improve the response speed of a neuron transistor circuit; the finger inserting structure refers to a grid electrode of a folded metal oxide semiconductor field effect transistor, when the grid electrode width of the metal oxide semiconductor field effect transistor is larger, the metal oxide semiconductor field effect transistor is manufactured into the folded finger inserting structure, when the grid electrode width of the metal oxide semiconductor field effect transistor is fixed, the total width of the grid electrode of the metal oxide semiconductor field effect transistor is determined by the number of fingers, and the width of the grid electrode corresponds to the number of fingers. For example, when the widths of the gates of the mosfets are 240nm, 1.8 μm, and 1.8 μm, respectively, the number of fingers is 1, 2, and 6, respectively.

The metal oxide semiconductor field effect transistor comprises: a P-type substrate.

The metal oxide semiconductor field effect transistor further comprises: at least 3 active regions arranged in sequence at intervals are positioned in the P-type substrate, the active regions are source regions or drain regions of the metal oxide semiconductor field effect transistor, the source regions or the drain regions are mutually connected, as shown in fig. 2, fig. 2 is the metal oxide semiconductor field effect transistor with two folded insertion finger structures, a part of the mutually spaced active regions are mutually and electrically connected to form the source regions, the rest mutually spaced active regions are mutually and electrically connected to form the drain regions, and all gate layers are mutually and electrically connected.

The metal oxide semiconductor field effect transistor further comprises: a gate layer located above the substrate region spaced between every two active regions, and defining the MOS structure corresponding to each gate layer as an inter-digitated structure, where the number of the inter-digitated structures is related to the number of the active regions, for example, when the number of the active regions is odd, an even number of inter-digitated structures are formed, that is, as shown in fig. 2, when the number of the active regions is 3, an inter-digitated structure with 2 inter-digitated fingers is formed; it is also possible to form an odd number of finger structures when the number of active regions is even.

Because the technical scheme that a part of the mutually spaced active regions are mutually and electrically connected to form a source region, the rest of the mutually spaced active regions are mutually and electrically connected to form a drain region, all gate layers are mutually and electrically connected, and the MOS structure corresponding to each gate layer is defined as an insert finger structure is adopted, because of the folding structure, the junction capacitance of the drain region is much smaller than that of the drain region when the drain region is not folded, but the same width-length ratio W/L can be provided, and because the resistivity of the polysilicon of the gate region cannot be completely ignored, the resistance of the polysilicon is changed from series connection to parallel connection, and the resistance can be greatly reduced.

Based on the same inventive concept, the invention also provides a negative differential resistance circuit structure, which is provided with an emitter terminal V as shown in FIG. 3_eCollector terminal V_cAnd base terminal V_b(ii) a The number of the metal oxide semiconductor field effect transistors in the negative differential resistance circuit structure at least comprises 3, specifically, when the number of the metal oxide semiconductor field effect transistors is 3, the Λ -type negative differential resistance circuit structure shown in fig. 3 is formed, and the Λ -type negative differential resistance circuit structure includes: a first N-channel metal oxide semiconductor field effect transistor MN1, a second N-channel metal oxide semiconductor field effect transistor MN2,A third N-channel mosfet MN3, wherein the gate of the first N-channel mosfet is connected to the base terminal, and the base of the first N-channel mosfet itself is connected to the drain thereof; the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end; the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal.

In the Λ -type negative differential resistance circuit structure, the second N-channel mosfet and the third N-channel mosfet adopt the mosfet as shown in fig. 2, and the second N-channel mosfet and the third N-channel mosfet adopt the folded insertion finger structure, wherein the gate widths of the second N-channel mosfet and the third N-channel mosfet in the Λ -type negative differential resistance circuit structure are W_MN2＝1.8μm、W_MN31.8 μm, the number of fingers of the second N-channel mosfet is 2, and the number of fingers of the third N-channel mosfet is 6.

As shown in the Λ -type negative differential resistance circuit structure of fig. 3, the process of the Λ -type negative differential resistance to generate the negative resistance is as follows: grounding of emitter and substrate of inverted V-shaped negative differential resistor_bAt a fixed certain value, when V_c0, gate voltage of MN2 is 0, and threshold voltage U of MN2 is not reached_THThere is no current in the MN2 channel. Therefore, the sum of the voltage between the gate and the source of MN1 and the voltage between the gate and the source of MN3 is V_b(ii) a When V is_cAt the beginning of the increase, since the current of MN1 can not pass through the channel reached by the gate of MN3, MN1 is not conductive, and V_bAll acted on MN3, measured I_cIs the source drain current of MN 3. According to the formulaWith V_cThe source-drain current of MN3 begins to increase; when V is_cGradually increases to the threshold voltage U of MN2_THWhen the current is relatively high, both MN2 and MN1 are conducted, and the current flows to the emitter terminal E through MN 2; when V is_cGreater than U_TH2When current starts to flow in MN1 and MN 2. Therefore, the gate and source voltages V of the first N-channel MOSFET_GS1Increasing the gate and source voltage V of the third N-channel MOSFET_GS3＝V_b-V_GS1Necessarily decreases, and the current in MN3 necessarily decreases until V_cWhen the value is larger, V_GS3Less than the threshold, MN3 turns off and the current is zero, resulting in a negative resistance.

When the number of the metal oxide semiconductor field effect transistors is 4, an N-type negative differential resistance circuit structure shown in fig. 4 is formed, and the N-type negative differential resistance circuit structure includes: a first N-channel metal oxide semiconductor field effect transistor MN1, a second N-channel metal oxide semiconductor field effect transistor MN2, a third N-channel metal oxide semiconductor field effect transistor MN3 and a fourth N-channel metal oxide semiconductor field effect transistor MN 4; the grid electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the base electrode end, and the base electrode of the first N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the first N-channel metal oxide semiconductor field effect transistor; the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end; the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal; the grid electrode and the drain electrode of the fourth N-channel metal oxide semiconductor field effect transistor are connected to the collector terminal, and the source electrode and the emitter terminal of the fourth N-channel metal oxide semiconductor field effect transistor are connected to the collector terminal and the emitter terminal.

The structure of the N-type negative differential resistance circuit is similar to that of the reversed V-type negative differential resistance circuit, except that the N-type negative differential resistance circuit is additionally provided with a fourth N-channel metal oxide semiconductor field effect transistor with larger size, wherein the grid width of each metal oxide semiconductor field effect transistor in the N-type negative differential resistance circuit is W_MN1＝240nm、W_MN2＝1.8μm、W_MN31.8 μm and W_MN4The number of the fingers is 1, 2, 6 and 30 respectively, which also meets the design requirement of the negative resistance type logic circuit.

The negative differential resistor is provided with an emitter terminal, a collector terminal and a base terminal; the negative differential resistance circuit comprises an inverted V-shaped or N-shaped connection form, wherein the inverted V-shaped negative differential resistance comprises three N-channel metal oxide semiconductor field effect transistors, and the circuit connection comprises: the self grid electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the base electrode end and connected with the self drain electrode; the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the source electrode of the first N-channel metal oxide semiconductor field effect transistor, the grid electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the collector electrode end, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is connected with the emitter electrode end; the grid electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the drain electrode of the second N-channel metal oxide semiconductor field effect transistor, the source electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the emitter terminal, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is connected with the collector terminal; the N-type negative differential resistor comprises four N-channel metal oxide semiconductor field effect transistors, a fourth N-channel metal oxide semiconductor field effect transistor is added on the basis of the original inverted V-type negative differential resistor structure, the grid electrode and the drain electrode of the fourth N-channel metal oxide semiconductor field effect transistor are connected to the collector electrode end, and the source electrode of the fourth N-channel metal oxide semiconductor field effect transistor is connected to the emitter electrode end. The problem of among the prior art chip area occupation big is solved, through reducing the quantity of metal oxide semiconductor field effect transistor, the area occupation of chip has been reduced.

Based on the same inventive concept, the present invention further provides a neuron transistor structure, which is applied to a neuron network, wherein the neuron network comprises one or even a plurality of neuron transistors, the neuron network is described by taking the example that the neuron transistor is included in the neuron network, and the neuron network formed by the other plurality of neuron transistors is connected with the neuron transistor described in the application, which is not described herein again.

As shown in fig. 5, fig. 5 is a schematic diagram of the operation of the neuron transistor, and the operation principle of the neuron transistor is as follows: the function of the neuron transistor is to simulate biological neuron cells, and realize the following functions of weight addition and threshold comparison:

S＝∑W_ix_i(i＝1,2,3)

O＝μ(S-L_th)

wherein W_iAnd x_i(x_iProduct of either 0 or 1) is V_g1，V_g2And V_g3The weight values (i ═ 1, 2, 3) of the input signals at the three inputs, S is the sum of the weights, and O is the output voltage V of the neuron transistor_out，L_thIs a threshold value. Mu (S-L)_th) Is a step function, S-L_thO is equal to 0 when less than 0, and S-L is_thGreater than 0, O equals 1, the threshold is a digital logic form of the threshold voltage, and the threshold is controlled by the threshold voltage; when outputting V_outIs high level and is represented by digital logic '1', when the output V is_outHigh, represented by a digital logic "0".

The structure of the neuron transistor comprises a neuron transistor circuit structure shown in fig. 6, and the neuron transistor circuit structure provided by the invention is applied to a neural network and comprises a weight summation circuit and a threshold circuit.

The weight summation circuit comprises at least two synapses connected in parallel and a first negative differential resistance; specifically, the at least two synapses comprise a first synapse and a second synapseTo the ith synapse; and the ratio of the gate width of the N-channel metal oxide semiconductor field effect transistor from the first synapse part to the second synapse part to the ith synapse part is 1:2: … … 2^i-1The first synapse part, the second synapse part and the ith synapse part adopt Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) as shown in FIG. 2, wherein i is greater than or equal to 3, and the synapse parts are used for sensing a trigger signal; each synapse part is an N-channel metal oxide semiconductor field effect transistor with different grid widths, and the total width of each synapse part, namely the metal oxide semiconductor field effect transistor, controls the synapse weight; the weighted sum can be reduced to a weight multiplied by the sum of the input voltage signals ("0" or "1") of the respective synapse gates, e.g.: if the width of each synapse gate is 1.8 μm and includes 1, 2 and 4 fingers, the ratio of the gate widths of the N-channel mosfets in the first synapse, the second synapse, and up to the ith synapse is 1:2: 4, the weight ratio is also 1:2: 4. in the weight summation circuit, the source of the first synapse and the second synapse to the ith synapse is connected to the output end of the neuron transistor, and the emitter of the first negative differential resistance is also connected to the output end of the neuron transistor; the drains of the first synapse, the second synapse, and up to the ith synapse are connected to a clock supply terminal of a neuron transistor, and the collector of the first negative differential resistance is also connected to the clock supply terminal of the neuron transistor.

A threshold circuit comprising a synapse scaling control and a second negative differential resistance; the connection relationship of the threshold circuit is as follows: the drain of the synapse scaling control part is connected with the output end of the neuron transistor, and the source of the synapse scaling control part is connected with the second negative differential resistance. The synapse scaling control part adopts a metal oxide semiconductor field effect transistor as shown in fig. 2, and the threshold value of the synapse scaling control part can be adjusted according to the surrounding environment, so that the neural network becomes stable.

The connection relation between the weight summation circuit and the threshold circuit is as follows: and connecting the emitter terminal of the first negative differential resistor and the collector terminal of the second negative differential resistor to serve as the output terminal of the neuron transistor, so as to form a complete neuron transistor structure.

As shown in fig. 6, when the output is off, the current flowing through the first and second negative differential resistances is equal, and the circuit should operate in a state similar to an unstable state. When a load is present and the current in the weighted sum circuit is greater than the current of the threshold circuit, the excess current must charge the load capacitance of the circuit output. When the current in the first NDR is further increased, the current in the second NDR is decreased, resulting in a further increase in the influence of the output voltage on the load capacitance. Finally the output voltage remains in a stable high state, corresponding to a "1" of the digital logic. Due to V_conThe pull-down current generated in the voltage controlled MOSFET must flow through the first NDR, thereby generating a voltage across the NDR load, which in turn causes the output voltage to be lower than the clock voltage V_CC。

The magnitude relation between the current in the weight summation circuit and the current in the threshold circuit is determined by the weight voltage V_g1，V_g2And V_g3And a threshold voltage V_conAnd (4) controlling together. When the weight voltage V_g1，V_g2And V_g3When determined, the threshold voltage V_conAn increase will result in an increase in current to the threshold logic circuit, no charging of the load, and an output shutdown. However, in order to ensure that the current in the weight summing circuit is equal to the current in the threshold logic circuit, the current in the first negative differential resistor must be increased, which causes the output point voltage to decrease, the output voltage is maintained in a stable low state, corresponding to "0" of the digital logic, and the state of the output voltage of the neuron transistor is detected by the digital logic state of the output voltage.

Due to the adoption of a neuron transistor structure, the neuron transistor adopts two parts of a weight summation circuit and a threshold summation circuit, wherein the weight summation circuit comprises at least two synapses connected in parallel and a first negative differential resistance; and each synapse part is an N-channel metal oxide semiconductor field effect transistor with different grid widths; the source electrode of each synapse part and the emitter electrode of the first negative differential resistance are respectively connected to the output end of the neuron transistor; the drain electrode of each synapse part and the collector electrode of the first negative differential resistance are respectively connected to a clock power supply end of the neuron transistor; a threshold circuit comprising a synapse scaling control and a second negative differential resistance; the drain electrode of the synapse scaling control part is connected with the output end of the neuron transistor, and the source electrode of the synapse scaling control part is connected with the second negative differential resistance; the emitter terminal of the first negative differential resistor is connected with the collector terminal of the second negative differential resistor to serve as the output end of the neuron transistor, and the neuron transistor without a capacitor structure is designed by using the negative differential resistor with the finger insertion structure, so that the problem of complex circuit structure in the prior art is solved, and the power consumption of the neuron transistor is reduced.

Based on the same inventive concept, the present invention further provides an application method of a neuron transistor, which is applied to the structure of the neuron transistor, as shown in fig. 7, fig. 7 is a schematic diagram of an application flow of the neuron transistor, and the application of the neuron transistor specifically includes the following steps:

in step S110, a clock signal is input from the neuron transistor clock power supply terminal.

In this embodiment, a clock signal is input to a clock power supply terminal of the neuron transistor to control the operating state of the neuron transistor, thereby reducing the power consumption of the neuron transistor.

In step S120, a weight control signal is input from the synapse.

And step S130, performing weighted summation on the weight control signals, comparing the weighted summation with a preset threshold, outputting a high level when the weighted summation is greater than the preset threshold, and outputting a low level when the weighted summation is less than the preset threshold.

In step S140, according to the output voltage, a threshold voltage of the synapse scaling control portion may be adjusted to achieve synapse scaling.

In this embodiment, synaptic scaling is defined as that a threshold of a certain neuron in the neural network can be adjusted according to the surrounding environment, which has the effect of stabilizing the neural network, and since the environment of the neuron is unstable, the neuron needs to maintain high sensitivity to the environment, and can be adjusted according to the current environmental conditions, and also can learn and accumulate certain experience from the occurred situations to better cope with the change of the current environment. The neuron transistor provided by the application has a first negative differential resistance and a second negative differential resistance, the sensitivity of an artificial neural network can be improved, on the premise that the weight is kept unchanged, the weight control signal is subjected to weighted summation and is compared with a preset threshold, a high level is output when the weight control signal is larger than the preset threshold, a low level is output when the weight control signal is smaller than the preset threshold, and the threshold voltage of a synapse scaling control part can be adjusted according to the output voltage to realize synapse scaling.

In the present embodiment, in fig. 6, V_conIs a threshold voltage, V_outFor neuron transistor outputs, the sum of the input weight control signals for each synapse is calculated, e.g. V_g1，V_g2And V_g3The sum of the input signals; the threshold value can be controlled by the threshold voltage, the threshold voltage is processed digitally, namely when the threshold voltage is controlled, the threshold value is in the digital logic form of the threshold voltage, in the application, the base terminal voltage V of different first negative differential resistors is controlled by the threshold voltage_b(load)A base terminal voltage V of the second negative differential resistor_b(driver)In this case, the relationship between the threshold value and the threshold voltage is as follows:

when the sum of the input weight control signals of all synapses exceeds a threshold value, the output end of the neuron transistor outputs a high-level control signal; when the sum of the input weight control signals of the synapses does not exceed a threshold, the neuron transistor output outputs a low level control signal. Synaptic scaling is achieved by adjusting the threshold voltage.

In other embodiments, the neuron transistor may be controlled by a clock signal or data, depending on the position and role of its connection in the neural network or artificial intelligence chip, and the neuron structure may make adjustments, such as increasing or decreasing the number of synapses, adjusting the magnitudes of the first NDR base voltage, the second NDR base voltage, and the neuron transistor clock supply voltage, etc.

The clock signal is input from a clock power supply end of a neuron transistor, the weight control signal is input from a synapse part, the weight control signal is subjected to weighted summation and is compared with a preset threshold value, a high level is output when the weight control signal is larger than the preset threshold value, a low level is output when the weight control signal is smaller than the preset threshold value, and the threshold voltage of a synapse scaling control part can be adjusted according to the output voltage to realize synapse scaling.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.