阅读说明：本技术 金属氧化物薄膜晶体管及其制作方法 (Metal oxide thin film transistor and manufacturing method thereof ) 是由 何佳新 于 2020-11-09 设计创作，主要内容包括：本发明提供一种金属氧化物薄膜晶体管及其制作方法,该方法包括在栅极绝缘层上形成非晶态的金属氧化物半导体薄膜；形成覆盖金属氧化物半导体薄膜的第二金属层,对第二金属层进行图形化以形成源极/漏极层的图形,其中,第二金属层包括与非晶态的金属氧化物半导体薄膜接触的晶化诱导层；对形成有源极/漏极层的图形和非晶态的金属氧化物半导体薄膜的基板进行诱导晶化退火,在晶化诱导层的诱导下,使非晶态的金属氧化物半导体薄膜转变为结晶态的金属氧化物半导体薄膜,以形成由结晶态的金属氧化物半导体薄膜构成的有源层。本发明在提高金属氧化物薄膜晶体管的载流子迁移率和工艺集成度的同时,降低了生产成本。(The invention provides a metal oxide thin film transistor and a manufacturing method thereof, wherein the method comprises the steps of forming an amorphous metal oxide semiconductor thin film on a grid insulation layer; forming a second metal layer covering the metal oxide semiconductor film, and patterning the second metal layer to form a pattern of the source/drain layer, wherein the second metal layer comprises a crystallization inducing layer in contact with the amorphous metal oxide semiconductor film; and performing induced crystallization annealing on the substrate on which the pattern of the source/drain layer and the amorphous metal oxide semiconductor film are formed, and converting the amorphous metal oxide semiconductor film into the crystalline metal oxide semiconductor film under the induction of the crystallization inducing layer so as to form the active layer consisting of the crystalline metal oxide semiconductor film. The invention improves the carrier mobility and the process integration level of the metal oxide thin film transistor and reduces the production cost.)

1. A method for fabricating a metal oxide thin film transistor, comprising:

forming a first metal layer on a substrate, and patterning the first metal layer to form a grid;

forming a gate insulating layer covering the gate electrode on the substrate;

forming an amorphous metal oxide semiconductor film on the gate insulating layer;

forming a second metal layer covering the metal oxide semiconductor film, and patterning the second metal layer to form a pattern of a source/drain layer, wherein the second metal layer includes a crystallization inducing layer in contact with the metal oxide semiconductor film in an amorphous state;

performing induced crystallization annealing on the substrate on which the pattern of the source/drain layer and the amorphous metal oxide semiconductor film are formed, and converting the amorphous metal oxide semiconductor film into the crystalline metal oxide semiconductor film under the induction of the crystallization inducing layer so as to form an active layer composed of the crystalline metal oxide semiconductor film;

patterning the crystallization inducing layer, removing the crystallization inducing layer exposed from the channel region to form a source electrode and a drain electrode on the pattern of the source/drain electrode layer;

and forming a pixel electrode on the substrate, wherein the pixel electrode is electrically connected with the drain electrode.

2. The method of claim 1, wherein the patterning the second metal layer to form a pattern of source/drain layers comprises:

coating a photoresist on the second metal layer, exposing and developing the photoresist, and etching the second metal layer by using a photoresist pattern left after development as a mask to form the second metal layer in the TFT region;

removing the light resistance on the TFT area;

forming a transparent conductive layer covering the second metal layer, coating a photoresist on the transparent conductive layer, exposing and developing the photoresist, and etching the transparent conductive layer by using a photoresist pattern left after development as a mask to form the transparent conductive layer positioned in a source/drain region and a pixel electrode region;

continuously etching and removing part of the second metal layer positioned in the channel region by taking the patterned photoresist as a mask, wherein the crystallization inducing layer is exposed from the channel region so as to form a pattern of a source/drain layer on the second metal layer;

and stripping the photoresist.

3. The method of claim 1, wherein the patterning the second metal layer to form a pattern of source/drain layers comprises:

coating a photoresist on the second metal layer, and exposing and developing the photoresist by adopting a half-tone mask, so that the thickness of the photoresist on the channel region is smaller than that of the photoresist on the source/drain region in the photoresist left after development;

etching the second metal layer by using the photoresist pattern left after the development as a mask to form the second metal layer positioned in the TFT area;

ashing the photoresist to expose the second metal layer in the channel region;

etching the exposed second metal layer by using the retained photoresist pattern as a mask, wherein the crystallization inducing layer is exposed from the channel region to form a pattern of a source/drain layer on the second metal layer;

and stripping the photoresist.

4. The method of manufacturing a metal oxide thin film transistor according to claim 2 or 3, wherein the step of forming a pixel electrode on the substrate comprises:

and forming a transparent conductive layer covering the second metal layer, and patterning the transparent conductive layer to form a pixel electrode and a transparent conductive layer superposed on the source/drain layer pattern.

5. The method of claim 3, wherein the step of forming a pixel electrode on the substrate comprises:

forming a first insulating layer covering the gate insulating layer, the active layer, the source electrode and the drain electrode;

forming a contact hole on the first insulating layer, wherein the drain electrode is exposed from the contact hole;

and forming a pixel electrode on the first insulating layer, the pixel electrode being electrically connected to the drain electrode through the contact hole.

6. The method of fabricating a metal oxide thin film transistor according to claim 1, wherein the step of forming the active layer pattern comprises:

forming an amorphous metal oxide semiconductor film on the whole surface of the gate insulating layer;

forming a second metal layer covering the metal oxide semiconductor film, coating a photoresist on the second metal layer, and exposing and developing the photoresist by adopting a halftone mask, so that the thickness of the photoresist on the channel region and the pixel electrode region is smaller than that of the photoresist on the source/drain electrode region in the photoresist left after development;

etching the second metal layer and the metal oxide semiconductor film by using the photoresist pattern left after development as a mask, and forming the second metal layer and the metal oxide semiconductor film which are overlapped up and down in a TFT area and a pixel electrode area;

ashing the photoresist to expose the second metal layer in the channel region and the pixel electrode region;

etching the second metal layer by using the retained photoresist pattern as a mask, wherein the crystallization inducing layer is exposed from the channel region to form a pattern of a source/drain layer on the second metal layer;

inducing the amorphous metal oxide semiconductor thin film to be transformed into a crystalline state by the crystallization inducing layer to form an active layer composed of the crystalline metal oxide semiconductor thin film.

7. The method of claim 6, wherein the active layer and the source and drain are formed by etching in a same mask process, and the pixel electrode and the active layer are in a same layer.

8. The method according to claim 5 or 7, wherein the second metal layer further comprises a passivation layer, the passivation layer and the crystallization inducing layer are disposed opposite to each other in an up-down direction, and the passivation layer is used for preventing the second metal layer located below the passivation layer from being oxidized.

9. The method of claim 1, wherein an etch rate of the second metal layer is greater than an etch rate of the gate insulating layer, the active layer, and the pixel electrode.

10. A metal oxide thin film transistor, comprising the metal oxide thin film transistor according to any one of claims 1 to 9.

Technical Field

The invention relates to the technical field of display, in particular to a metal oxide thin film transistor and a manufacturing method thereof.

Background

Thin Film Transistors (TFTs) are a core component of flat panel displays, and any active matrix flat panel display relies on the control and driving of TFTs. The switching elements currently used in displays are still mainly amorphous silicon (a-Si) thin film transistors and polycrystalline silicon (p-Si) thin film transistors, among which amorphous silicon thin film transistors are most widely used, but amorphous silicon thin film transistorsThe transistor has low electron mobility (only 0.3-1 cm)²Problems with/V · s); although the mobility of the polysilicon thin film transistor is higher than that of the amorphous silicon thin film transistor, the polysilicon thin film transistor has the problems of complex structure, poor uniformity, large leakage current and the like. With the rapid development of display technology, higher and higher requirements are put on the performance of thin film transistors, and amorphous silicon thin film transistors and polysilicon thin film transistors have not been able to fully meet these requirements. Therefore, the conventional flat panel display industry has adopted a metal oxide semiconductor TFT to improve the above problems, for example, an Indium Gallium Zinc Oxide (IGZO) TFT is adopted, which is more compatible with a large-sized and high-resolution (PPI) display device.

However, in a thin film transistor using a metal oxide semiconductor as an active layer material, a vapor deposition method such as sputtering (sputtering), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), or Metal Organic Chemical Vapor Deposition (MOCVD), or a liquid deposition method such as solution coating (solution coating) or ink jet printing (ink jet printing) is generally used in film formation, and since a metal oxide semiconductor thin film deposited by any of the above deposition methods contains a large number of microstructure defects such as microvoids (void), vacancies (vacancy), dislocations, and chemical bond length/bond angle strain (strain), the thin film is generally in an amorphous state.

However, the amorphous metal oxide semiconductor easily captures channel carriers at a portion of the TFT channel layer, which causes a reduction in channel carrier mobility, which is about 5 to 10cm in electron mobility²V s. With the rapid development of the technologies of the liquid crystal display panel and the AMOLED display panel, such as high resolution, high refresh rate, narrow frame, low power consumption, and DeMUX, the existing electron mobility thereof is gradually insufficient. Therefore, it is necessary to develop a metal oxide semiconductor TFT having higher electron mobility.

Currently, the development of high electron mobility metal oxide TFTs is mainly based on new high electron mobility metal oxide semiconductor materials (targets, inks, process characteristics, etc.). However, the novel metal oxide semiconductor material has the problems of long development period, high technical difficulty, high cost and the like, and according to the general industrial production rule, the related production and application cost of the novel material at the initial stage of mass production is obviously higher than that of the existing material which is subjected to mass production for a long time. The subsequent cost reduction depends on the mass spread of new materials and the establishment of a stable mass production system upstream of the supply chain, which cannot be achieved in the short term.

Disclosure of Invention

The invention aims to provide a metal oxide thin film transistor and a manufacturing method thereof, which can improve the carrier mobility and the process integration level of the metal oxide thin film transistor and reduce the production cost.

The invention provides a method for manufacturing a thin film transistor, which comprises the following steps:

forming a first metal layer on a substrate, and patterning the first metal layer to form a grid;

forming a gate insulating layer covering the gate electrode on the substrate;

forming an amorphous metal oxide semiconductor film on the gate insulating layer;

forming a second metal layer covering the metal oxide semiconductor film, and patterning the second metal layer to form a pattern of a source/drain layer, wherein the second metal layer includes a crystallization inducing layer in contact with the metal oxide semiconductor film in an amorphous state;

performing induced crystallization annealing on the substrate on which the pattern of the source/drain layer and the amorphous metal oxide semiconductor film are formed, and converting the amorphous metal oxide semiconductor film into the crystalline metal oxide semiconductor film under the induction of the crystallization inducing layer so as to form an active layer composed of the crystalline metal oxide semiconductor film;

patterning the crystallization inducing layer, removing the crystallization inducing layer exposed from the channel region to form a source electrode and a drain electrode on the pattern of the source/drain electrode layer;

and forming a pixel electrode on the substrate, wherein the pixel electrode is electrically connected with the drain electrode.

Further, the patterning the second metal layer to form a pattern of a source/drain layer includes:

coating a photoresist on the second metal layer, exposing and developing the photoresist, and etching the second metal layer by using a photoresist pattern left after development as a mask to form the second metal layer in the TFT region;

removing the light resistance on the TFT area;

forming a transparent conductive layer covering the second metal layer, coating a photoresist on the transparent conductive layer, exposing and developing the photoresist, and etching the transparent conductive layer by using a photoresist pattern left after development as a mask to form the transparent conductive layer positioned in a source/drain region and a pixel electrode region;

continuously etching and removing part of the second metal layer positioned in the channel region by taking the patterned photoresist as a mask, wherein the crystallization inducing layer is exposed from the channel region so as to form a pattern of a source/drain layer on the second metal layer;

and stripping the photoresist.

Further, the patterning the second metal layer to form a pattern of a source/drain layer includes:

coating a photoresist on the second metal layer, and exposing and developing the photoresist by adopting a half-tone mask, so that the thickness of the photoresist on the channel region is smaller than that of the photoresist on the source/drain region in the photoresist left after development;

etching the second metal layer by using the photoresist pattern left after the development as a mask to form the second metal layer positioned in the TFT area;

ashing the photoresist to expose the second metal layer in the channel region;

etching the exposed second metal layer by using the retained photoresist pattern as a mask, wherein the crystallization inducing layer is exposed from the channel region to form a pattern of a source/drain layer on the second metal layer;

and stripping the photoresist.

Further, the step of forming a pixel electrode on the substrate includes:

and forming a transparent conductive layer covering the second metal layer, and patterning the transparent conductive layer to form a pixel electrode and a transparent conductive layer superposed on the source/drain layer pattern.

Further, the step of forming a pixel electrode on the substrate includes:

forming a first insulating layer covering the gate insulating layer, the active layer, the source electrode and the drain electrode;

forming a contact hole on the first insulating layer, wherein the drain electrode is exposed from the contact hole;

and forming a pixel electrode on the first insulating layer, the pixel electrode being electrically connected to the drain electrode through the contact hole.

Further, the step of forming the active layer pattern includes:

forming an amorphous metal oxide semiconductor film on the whole surface of the gate insulating layer;

forming a second metal layer covering the metal oxide semiconductor film, coating a photoresist on the second metal layer, and exposing and developing the photoresist by adopting a halftone mask, so that the thickness of the photoresist on the channel region and the pixel electrode region is smaller than that of the photoresist on the source/drain electrode region in the photoresist left after development;

etching the second metal layer and the metal oxide semiconductor film by using the photoresist pattern left after development as a mask, and forming the second metal layer and the metal oxide semiconductor film which are overlapped up and down in a TFT area and a pixel electrode area;

ashing the photoresist to expose the second metal layer in the channel region and the pixel electrode region;

etching the second metal layer by using the retained photoresist pattern as a mask, wherein the crystallization inducing layer is exposed from the channel region to form a pattern of a source/drain layer on the second metal layer;

inducing the amorphous metal oxide semiconductor thin film to be transformed into a crystalline state by the crystallization inducing layer to form an active layer composed of the crystalline metal oxide semiconductor thin film.

Furthermore, the active layer and the source and the drain are formed by etching in the same photomask process, and the pixel electrode and the active layer are located in the same layer.

Further, the second metal layer further comprises a passivation layer, the passivation layer and the crystallization inducing layer are arranged oppositely from top to bottom, and the passivation layer is used for preventing the second metal layer below the passivation layer from being oxidized.

Further, an etching rate of the second metal layer is greater than etching rates of the gate insulating layer, the active layer, and the pixel electrode.

The invention also provides a metal oxide thin film transistor which is formed by the manufacturing method of the metal oxide thin film transistor.

According to the metal oxide semiconductor thin film transistor and the manufacturing method thereof, the amorphous metal oxide semiconductor thin film is formed on the grid insulation layer, the second metal layer covering the metal oxide semiconductor thin film is formed, wherein the second metal layer comprises the crystallization inducing layer which is in contact with the amorphous metal oxide semiconductor thin film, and in the process of forming the source electrode/the drain electrode on the second metal layer, the amorphous metal oxide semiconductor thin film forms the active layer formed by the crystalline metal oxide semiconductor thin film under the induction of the crystallization inducing layer.

Drawings

Fig. 1 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a first embodiment of the present invention;

fig. 2a to fig. 2i are schematic diagrams illustrating a process of fabricating a metal oxide thin film transistor according to a first embodiment of the invention;

fig. 3 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a second embodiment of the present invention;

fig. 4a to fig. 4j are schematic views illustrating a manufacturing process of a metal oxide thin film transistor according to a second embodiment of the present invention;

fig. 5 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a third embodiment of the present invention;

fig. 6a to fig. 6g are schematic views illustrating a manufacturing process of a metal oxide thin film transistor according to a third embodiment of the present invention;

fig. 7 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a fourth embodiment of the present invention;

fig. 8a to 8i are schematic views illustrating a manufacturing process of a metal oxide thin film transistor according to a fourth embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.

Example one

Fig. 1 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor in a first embodiment of the present invention, and fig. 2a to 2i are schematic cross-sectional structures of a metal oxide thin film transistor in a first embodiment of the present invention, and in combination with fig. 1 and fig. 2a to 2i, a method for manufacturing a metal oxide thin film transistor provided in an embodiment of the present invention includes:

the substrate 11 is cleaned, and the substrate 11 may be a glass substrate or a quartz substrate.

A first metal layer (not shown) is formed on the substrate 11, and the first metal layer is patterned by using an etching process to form the gate electrode 12 and the scan line (not shown).

A gate insulating layer 13 is formed on the substrate 11 to cover the gate electrode 12 and the scan line, and the gate insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a combination thereof, and preferably has a film thickness of 10 to 1000 nm.

An amorphous metal oxide semiconductor thin film 14 is formed on the gate insulating layer 13. The metal oxide semiconductor thin film 14 may be formed by a vapor deposition method such as sputtering (sputtering), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), Metal Organic Chemical Vapor Deposition (MOCVD), or a liquid deposition method such as solution coating (solution coating), ink jet printing (ink jet printing). The metal oxide semiconductor film 14 deposited by any of the foregoing deposition methods generally has an amorphous state because it contains a large number of microstructure defects, such as microvoids (void), vacancies (vacancy), dislocations, chemical bond length/bond angle strain (strain), and the like. The metal oxide semiconductor material optionally contains an oxide of at least one or more elements of zinc, indium, gallium, tin, aluminum, silicon, scandium, titanium, vanadium, yttrium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, and lanthanoids, among others. Typical metal oxide semiconductor materials are Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Indium Gallium Zinc Tin Oxide (IGZTO), and the like. The film thickness is preferably 5 to 100 nm.

An active island (active island) pattern is formed by performing a photolithography process on the amorphous metal oxide semiconductor film 14.

Referring to fig. 2a, a second metal layer 15 covering the metal oxide semiconductor thin film 14 is formed on the active layer pattern, and the second metal layer 15 is made of a material capable of being dry etched, so as to prevent the second metal layer 15 from being corroded by a subsequent wet etching process. The second metal layer 15 preferably has a multilayer metal laminated structure of titanium/aluminum/titanium (Ti/Al/Ti), titanium/aluminum/tantalum (Ti/Al/Ta), titanium nitride/aluminum/titanium nitride (TiN/Al/TiN), titanium nitride/aluminum/tantalum nitride (TiN/Al/TaN), or a single-layer metal structure of titanium, tantalum, titanium nitride, tantalum nitride, or the like, which is stacked in this order from top to bottom. The crystallization inducing layer 151 (the film layer located at the bottom layer) of the second metal layer 15 contacting the amorphous metal oxide semiconductor film 14 is only required to be made of titanium, tantalum, titanium nitride or tantalum nitride, the film thickness of the crystallization inducing layer 151 is preferably 5 to 100nm, and further preferably 10 to 50nm, and the film thicknesses of the intermediate layer 152 and the top layer are not particularly limited in the present invention.

In the present embodiment, the second metal layer 15 has a three-layer metal stacked structure, which includes, from bottom to top, a crystallization inducing layer 151, an intermediate layer 152 and a top layer 153, such as, but not limited to, ti/al/ti.

It should be noted that, as shown by research, the amorphous metal oxide semiconductor thin film 14 can be induced to be transformed into a crystalline state by annealing at a temperature of 200 ℃ or higher in a manner that titanium, tantalum, titanium nitride, and tantalum nitride are in contact with the amorphous metal oxide semiconductor thin film 14. In contrast, the amorphous indium gallium zinc oxide film can be converted into a polycrystalline state by annealing at 600-800 ℃ without an induction layer, so that the production cost and the energy consumption are increased.

The second metal layer 15 is then patterned to form a pattern of source/drain layers.

Specifically, the step of patterning the source/drain layer includes: referring to fig. 2b, a photoresist 21 is coated on the second metal layer 15, and a photoresist 21 pattern corresponding to the pattern of the TFT region is formed by exposure and development, wherein the TFT region includes a region corresponding to the source 15a and the drain 15b and a region corresponding to the channel, which is different from the conventional method that the photoresist 21 is protected on the TFT back channel (back channel), that is, the developed photoresist 21 covers both the source/drain region and the channel region;

dry etching the second metal layer 15 by using the photoresist pattern left after the development as a mask to remove the second metal layer 15 outside the source/drain region and the channel region, and defining a pattern of the second metal layer 15 on the substrate 11 in the TFT region, wherein the dry etching process gas is preferably boron trichloride (BCl)₃) And chlorine (Cl)₂) Optionally oxygen (O)₂) Argon (Ar), carbon tetrachloride (CCl)₄) Silicon tetrachloride (SiCl)₄) Tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) Etc.;

removing the photoresist 21 on the TFT region;

forming a transparent conductive layer 160 (transparent conductive metal oxide, TCO) covering the second metal layer 15, preferably made of ITO, IZO, with a thickness of preferably 10-100 nm, as shown in fig. 2c, coating a photoresist 21 on the transparent conductive layer 160, exposing and developing the photoresist 21, wet etching the transparent conductive layer 160 using the photoresist pattern left after development as a mask, and removing the transparent conductive layer 160 outside the source/drain region and the pixel electrode region to form the transparent conductive layer in the source/drain region and the pixel electrode region, wherein the photoresist 21 pattern left covers the source/drain region and the pixel electrode region, and the transparent conductive layer 160 on the channel region is etched and removed because the channel region of the TFT is not protected by the photoresist 21, and the transparent conductive layer 160 left overlaps the source/drain layer 15 in the source/drain region In the pattern, the oxidation of the metal oxide semiconductor is prevented in a subsequent annealing process required by the induction crystallization of the amorphous metal oxide semiconductor, so that the effect of saving additional process steps related to the manufacture of the anti-oxidation protective layer of the source electrode 15 a/the drain electrode 15b is achieved; the pixel electrode 16 is formed in the pixel electrode region, and the etching solution is preferably an organic acid such as oxalic acid, and only the transparent conductive metal oxide is etched without etching the second metal layer 15.

Referring to fig. 2e, still using the photoresist 21 pattern as a mask, dry etching is performed to remove a portion of the second metal layer 15 in the channel region, so as to expose the crystallization-inducing layer 151 from the channel region, wherein the process gas of the dry etching is preferably boron trichloride (BCl)₃) And chlorine (Cl)₂) Optionally oxygen (O)₂) Argon (Ar), carbon tetrachloride (CCl)₄) Silicon tetrachloride (SiCl)₄) Tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) Etc.;

as shown in fig. 2f, the photoresist 21 is then stripped to form a pattern of source/drain layers.

Performing induced crystallization annealing on the substrate 11 with the source/drain layer pattern and the amorphous metal oxide semiconductor film 14, wherein the annealing temperature is preferably 200-400 ℃, and the annealing furnace is preferably filled with dry compressed air (CDA) and O₂、N₂The annealing time is preferably 0.2 to 2 hours.By the induced crystallization annealing, the amorphous metal oxide semiconductor film 14 is transformed into the crystalline metal oxide semiconductor film 14 under the induction of the crystallization inducing layer 151 to form the active layer 140 composed of the crystalline metal oxide semiconductor film 14.

In this embodiment, in the process of forming the source electrode 15a and the drain electrode 15b by using the second metal layer 15, the amorphous metal oxide semiconductor thin film 14 is converted into the crystalline metal oxide semiconductor thin film 14, that is, the processes of forming the source electrode 15a and the drain electrode 15b and inducing crystallization of the amorphous metal oxide semiconductor are completed in one step, and compared with the process of forming the source electrode 15a and the drain electrode 15b and the thin film pattern inducing crystallization of the amorphous metal oxide semiconductor, an additional inducing layer is not required to be added between the active layer 140 and the source electrode 15a and the drain electrode 15b, so the size of the TFT is greatly reduced.

The carrier mobility of the transistor (TFT) of the metal oxide semiconductor thin film 14 is greatly improved due to the greatly reduced structural defects such as metal-oxygen weak bonds, interstitial oxygen elements, hydrogen-oxygen bonds (hydroxyl groups), and the like in the crystalline metal oxide semiconductor thin film 14 and the greatly improved ordering of atomic arrangement. Meanwhile, the titanium Ti, tantalum Ta, titanium nitride TiN or tantalum nitride TaN in the second metal layer 15 in the TFT back channel is oxidized due to exposure to the annealing atmosphere, but the low-temperature (200-400 ℃) oxide film generated at the position is not a good insulator meeting the stoichiometric ratio, and the resistivity is not high enough due to insufficient oxidation, so that a certain leakage current is still allowed to pass through, and therefore, the titanium Ti, the tantalum Ta, the titanium nitride TiN or the tantalum nitride TaN must be removed by etching to reduce the leakage current so as to obtain good TFT electrical property.

In the present embodiment, the etching rate selectivity (selectivity) of the second metal layer 15 with respect to the other underlying layer materials is larger (up to 5 or more). As shown in fig. 2g, the substrate 11 is directly dry-etched without forming a photoresist 21 mask pattern (yellow light process), and the crystallization inducing layer 151 of the oxidized portion exposed from the channel region is removed to form the source electrode 15a and the drain electrode 15b on the pattern of the source/drain electrode layer, thereby improving the electrical properties and the electrical stability of the TFT without additionally forming a photoresist 21 pattern to protect other film regions and then removing the TFT back channel by etchingThe portion is oxidized of the second metal layer 15, and the pixel electrode 16 is electrically connected to the drain electrode 15 b. The dry etching process gas is preferably boron trichloride (BCl)₃) And chlorine (Cl)₂) Optionally oxygen (O)₂) Argon (Ar), carbon tetrachloride (CCl)₄) Silicon tetrachloride (SiCl)₄) Tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) And the like. Preferably, the etching rate of the second metal layer 15 is greater than that of the lower layer, wherein the etching rate selectivity of the oxide film of the crystallization inducing layer 151 to the transparent conductive layer 160, to the metal oxide semiconductor thin film 14, and to the gate insulating layer 13 (silicon oxide) is up to 5 or more, so that when the oxide film of Ti, Ta, TiN or TaN of Ti, TiN or TaN in the second metal layer 15 in the TFT back channel is completely etched and removed, the film thickness loss in other film regions of the substrate 11 is still within an acceptable range.

In the present embodiment, the drain electrode 15b may directly contact the pixel electrode 16 below, and a via hole (via hole) is not required to be formed in an area to electrically connect the drain electrode 15b and the pixel electrode 16.

As shown in fig. 2h, a second insulating layer 18 covering the gate insulating layer 13, the active layer 140, the transparent conductive layer 160 and the pixel electrode 16 is next formed.

As shown in fig. 2i, a common electrode 19 is formed on the second insulating layer 18.

In the method for manufacturing the metal oxide semiconductor thin film 14 transistor provided in the embodiment of the present invention, the amorphous metal oxide semiconductor thin film 14 is formed on the gate insulating layer 13, and the second metal layer 15 covering the metal oxide semiconductor thin film 14 is formed, wherein the second metal layer 15 includes the crystallization inducing layer 151 in contact with the amorphous metal oxide semiconductor thin film 14, and in the process of forming the source electrode 15 a/the drain electrode 15b on the second metal layer 15, the amorphous metal oxide semiconductor thin film 14 forms the active layer 140 formed by the crystalline metal oxide semiconductor thin film 14 under the induction of the crystallization inducing layer 151.

Example two

The present embodiment is the same as the first embodiment, and please refer to the first embodiment for the same parts, such as the gate 12, the gate insulating layer 13, and the fabrication of the amorphous metal oxide semiconductor active layer pattern, which are not described herein again, except that:

fig. 3 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a second embodiment of the present invention, and fig. 4a to 4j are schematic cross-sectional structures of a metal oxide thin film transistor according to a second embodiment of the present invention, and with reference to fig. 3, as shown in fig. 4a, a second metal layer 15 is formed overlying the metal oxide semiconductor film 14, the second metal layer 15 is patterned to form a pattern of a source/drain electrode layer, the second metal layer 15 is a crystallization inducing layer 151 and a top layer 153 from bottom to top, the material preferably adopts copper/titanium (Cu/Ti), copper/tantalum (Cu/Ta), copper/titanium nitride (Cu/TiN), copper/tantalum nitride (Cu/TaN) and the like which are sequentially overlapped from top to bottom, and the film thickness of the titanium Ti, the tantalum Ta, the titanium nitride TiN and the tantalum nitride TaN is preferably 5-100 nm, and further preferably 10-50 nm.

Specifically, the step of patterning the source/drain layer includes: referring to fig. 4b, coating a photoresist 21 on the second metal layer 15, exposing and developing the photoresist 21 by using a half-tone (half-tone) mask, and developing to form a photoresist 21 pattern corresponding to the source/drain layer, wherein the TFT back channel region is a half-tone region of the photoresist 21, so that the thickness of the photoresist 21 on the channel region is less than the thickness of the photoresist 21 on the source/drain region in the photoresist 21 left after development;

the second metal layer 15 is etched using the photoresist pattern left after the development as a mask to form the second metal layer 15 in the TFT region. Specifically, the etching solution capable of etching the Cu and Ti (or Ta) composite film is used for first wet etching, the second metal layer 15 outside the channel region and the source/drain region is removed by etching, and a pattern of the TFT region is manufactured, wherein the source 15a and the drain 15b are not separated above the TFT back channel;

referring to fig. 4c, the photoresist 21 on the channel region is ashed (ashing) to expose the second metal layer 15 in the channel region, and the ashing is performed using an O2 processGas, optionally with addition of tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) Waiting for fluorine-containing process gas to expose the second metal layer 15 above the TFT back channel;

continuously etching the exposed second metal layer 15 by using the retained photoresist pattern as a mask, performing second wet etching by using an etching solution which only etches copper (Cu) and does not damage titanium (Ti) or tantalum (Ta), and removing an upper film layer in the second metal layer 15 above the TFT channel region to expose the crystallization inducing layer 151 from the channel region;

as shown in fig. 4d, the photoresist 21 is removed to form a pattern of the source/drain layer.

Referring to fig. 4e, a transparent conductive layer 160 (pixel electrode layer transparent conductive metal oxide) is deposited next, preferably made of ITO or IZO, with a thickness of 10-100 nm. Then coating a photoresist 21, exposing and developing the photoresist 21, and referring to fig. 4f, performing wet etching to remove the transparent conductive layer 160 outside the source/drain region and the pixel electrode region, leaving a photoresist 21 pattern covering the source/drain region and the pixel electrode region, leaving the transparent conductive layer 160 overlying the source/drain layer pattern in the source/drain region, and forming the pixel electrode 16 in the pixel electrode region.

As shown in fig. 4f, the photoresist 21 is then stripped.

As shown in fig. 4g, induced crystallization annealing is then performed on the substrate 11 on which the pattern of the source/drain layer and the amorphous metal oxide semiconductor thin film 14 are formed, and as shown in fig. 4h, the oxide film of the crystallization inducing layer 151 exposed in the TFT channel region is directly removed by dry etching without a photolithography process to form the source electrode 15a and the drain electrode 15b on the second metal layer 15, and the pixel electrode 16 is electrically connected to the drain electrode 15 b.

As shown in fig. 4i and 4j, the second insulating layer 18 and the common electrode 19 are formed next.

EXAMPLE III

The present embodiment is the same as the first embodiment, and please refer to the first embodiment for the same parts, such as the gate 12, the gate insulating layer 13, and the fabrication of the amorphous metal oxide semiconductor active layer pattern, which are not described herein again, except that:

fig. 5 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a third embodiment of the present invention, and fig. 6a to 6g are schematic cross-sectional structures of the metal oxide thin film transistor according to the third embodiment of the present invention, and with reference to fig. 5 and fig. 6a to 6c, a second metal layer 15 covering a metal oxide semiconductor thin film 14 is formed, the second metal layer 15 is patterned to form a source/drain layer pattern, the material of the second metal layer is preferably a two-layer or three-layer composite film, the two-layer composite film is a crystallization inducing layer 151 and a top layer 153 from bottom to top, respectively, an upper layer film thereof is preferably a Cu alloy such as Cu-Al, Cu-Mg-Al, Cu-Mn, Cu-Ti, Cu-Ca, and the like, and a self-forming surface passivation protective layer (self-passivation barrier) after annealing, therefore, the related process for additionally manufacturing the annealing oxidation prevention protective layer of the source electrode 15 a/the drain electrode 15b is saved, the bottom layer film (the crystallization inducing layer 151) is preferably titanium Ti, tantalum Ta, titanium nitride TiN, tantalum nitride TaN and the like, and the thickness of the bottom layer film is preferably 5-100 nm, and is further preferably 10-50 nm. The top 153 and bottom (crystallization inducing layer 151) layers of the three-layer composite film are preferably the same two-layer composite film, and the middle 152 layer is preferably pure copper Cu.

The process steps for fabricating the source/drain layer pattern are the same as those of the second embodiment. Because the doping elements of Al, Mg, Mn, Ti and Ca in the copper Cu alloy are lower (generally less than 10 percent) in the alloy, the practice shows that the copper Cu etching solution can be used in the second embodiment.

As shown in fig. 6d, the next step of induced crystallization annealing is performed to convert the amorphous metal oxide semiconductor thin film 14 into a polycrystalline state in the same embodiments one and two, and simultaneously the doped metal elements in the copper alloy are precipitated and enriched on the surface of the copper alloy, and the top layer 153 film of the second metal layer 15 can self-generate a surface passivation protection layer after annealing, that is, a passivation layer 153a (i.e., a self-passivation protection layer Cu-X-O) is generated on the upper surface of the second metal layer 15 to prevent the copper alloy from being continuously oxidized, where X is Al, Mg, Mn, Ti, Ca, and other doped metals.

Referring to FIG. 6e, the substrate 11 is then dried directly without a photolithography processThe etching and dry etching process gas is preferably boron trichloride (BCl)₃) And chlorine (Cl)₂) Optionally oxygen (O)₂) Argon (Ar), carbon tetrachloride (CCl)₄) Silicon tetrachloride (SiCl)₄) Tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) And the like. Boron trichloride BCl₃Chlorine Cl₂The etching selectivity of the dry etching is more than 5, so when the oxide films of Ti, Ta, TiN, TaN, Cu alloy of the second metal layer 15, the metal oxide semiconductor film 14 and the gate insulating layer 13 are completely etched and removed, the film thickness loss of other film regions of the substrate 11 is still within an acceptable range.

As shown in fig. 6f, a first insulating layer 17 covering the gate insulating layer 13, the active layer 140, and the source/drain electrodes 15a and 15b is formed; as shown in fig. 6g, a contact hole (not shown) is formed on the first insulating layer 17, and the drain electrode 15b is exposed through the contact hole; a pixel electrode 16 is formed on the first insulating layer 17, and the pixel electrode 16 is electrically connected to the drain electrode 15b through a contact hole.

Example four

The present embodiment is the same as the first embodiment, and please refer to the first embodiment for the same parts, such as the gate 12, the gate insulating layer 13, and the fabrication of the amorphous metal oxide semiconductor active layer pattern, which are not described herein again, except that:

fig. 7 is a schematic cross-sectional structure diagram of a metal oxide thin film transistor according to a fourth embodiment of the present invention, and fig. 8a to 8i are schematic cross-sectional structures of a metal oxide thin film transistor according to a fourth embodiment of the present invention, and referring to fig. 7 and fig. 8a to 8i, a second metal layer 15 is deposited after the amorphous metal oxide semiconductor film 14 is not subjected to a photolithography process.

Specifically, referring to fig. 8a in combination, an amorphous metal oxide semiconductor thin film 14 is formed over the entire surface of the gate insulating layer 13; forming a second metal layer 15 covering the metal oxide semiconductor film 14, and stacking the second metal layer 15 and the metal oxide semiconductor film 14 up and down, wherein the second metal layer 15 is preferably a two-layer or three-layer composite film, the two-layer composite film is a crystallization inducing layer 151 and a top layer 153 from bottom to top, the upper layer of the two-layer composite film is preferably a copper-aluminum alloy (Cu-Al), a copper-magnesium alloy (Cu-Mg), a copper-magnesium-aluminum alloy (Cu-Mg-Al), a copper-manganese alloy (Cu-Mn), a copper-titanium alloy (Cu-Ti), a copper-calcium alloy (Cu-Ca) and other Cu alloys capable of self-generating a surface passivation protective layer (self-passivation barrier) after annealing, thereby saving the related process for additionally manufacturing the protective layer for preventing the annealing oxidation of the source electrode 15 a/drain electrode 15b, and the bottom layer (crystallization inducing layer 151) is preferably titanium Ti, Ta, titanium nitride, titanium, the film thickness of the underlayer film is preferably 5 to 100nm, more preferably 10 to 50 nm. The top 153 and bottom (crystallization inducing layer 151) layers of the three-layer composite film are preferably the same two-layer composite film, and the middle 152 layer is preferably pure copper Cu.

Referring to fig. 8b, a photoresist 21 is coated on the second metal layer 15, the photoresist 21 is exposed and developed by using a half-tone (half-tone) mask, and a photoresist 21 pattern corresponding to a TFT region and a pixel electrode region is manufactured by development, wherein a TFT channel region and the pixel electrode region are the half-tone regions of the photoresist 21, so that in the photoresist 21 left after development, the thickness of the photoresist 21 on the channel region and the photoresist 21 on the pixel electrode region is less than the thickness of the photoresist 21 on the source/drain region;

referring to fig. 8c, a first wet etching is performed by using a composite film etching solution capable of simultaneously etching Cu, Ti (or Ta) and the amorphous metal oxide semiconductor thin film 14, and the second metal layer 15 and the metal oxide semiconductor thin film 14 outside the TFT region and the pixel electrode region are removed by etching to form a source/drain layer pattern, an active layer pattern, and a pixel electrode pattern, where the source electrode 15a and the drain electrode 15b are not separated above the TFT back channel.

In conjunction with ashing (ashing) of the photoresist 21 on the channel region and the pixel electrode region as shown in fig. 8d, the ashing is performed using O₂Process gas, optionally with addition of SF₆、CF₄、NF₃Exposing the second metal layer 15 above the TFT back channel and the pixel electrode area by fluorine-containing process gas;

then, performing a second wet etching using an etching solution that etches Cu only without damaging Ti (or Ta), and removing the upper film layer in the second metal layer 15 above the TFT channel region and above the pixel electrode region, so that the crystallization-inducing layer 151 is exposed from the channel region;

referring to fig. 8e, an induced crystallization annealing is performed next, and in the same examples as in the first, second, and third, the amorphous metal oxide semiconductor thin film 14 is converted into a polycrystalline state, and the doped metal elements in the Cu alloy are precipitated and enriched on the surface of the Cu alloy, and after annealing, the top layer 153 film of the second metal layer 15 can self-generate a surface passivation protection layer, that is, a passivation layer 153a (i.e., a self-passivation protection layer Cu-X-O) is generated on the upper surface of the second metal layer 15 to prevent the Cu alloy from being continuously oxidized, where X is Al, Mg, Mn, Ti, Ca, and other doped metals.

Referring to FIG. 8f, the substrate 11 is then dry etched directly without a photolithography process, preferably with boron trichloride (BCl) as the dry etch process gas₃) And chlorine (Cl)₂) Optionally oxygen (O)₂) Argon (Ar), carbon tetrachloride (CCl)₄) Silicon tetrachloride (SiCl)₄) Tetrafluoromethane (CF)₄) Sulfur hexafluoride (SF)₆) Nitrogen trifluoride (NF)₃) And the like. Boron trichloride BCl₃Chlorine Cl₂The etching selectivity of the dry etching is such that the etching rate selectivity of the titanium Ti, tantalum Ta, titanium nitride TiN, tantalum nitride TaN oxide film to the copper alloy of the second metal layer 15, to the metal oxide semiconductor thin film 14, and to the gate insulating layer 13 can be up to 5 or more, so that when the titanium Ti, tantalum Ta, titanium nitride TiN, or tantalum nitride TaN oxide film of the source/drain layer in the TFT back channel is completely etched and removed, the film thickness loss of other film regions of the substrate 11 is still within the acceptable range. Thus, the source/drain electrodes 15a and 15b, the active layer 140 and the pixel electrode 16 are manufactured by only one yellow light process, and the active layer 140 and the pixel electrode 16 are formed without using two separate photomasks, so that the process is saved, and the Back Channel Etched (BCE) structure metal oxide TFT with high carrier mobility is realized.

With reference to fig. 8g, a first insulating layer 17 is deposited, wherein the first insulating layer 17 is preferably silicon oxide SiOx, aluminum oxide AlOx, silicon nitride SiNx, silicon oxynitride SiOxNy or a composite film thereof, wherein the direct contact layer of the metal oxide semiconductor thin film 14 thereunder is preferably SiOx or AlOx, and the film thickness thereof is preferably 10 to 1000 nm.

Referring to fig. 8h, the first insulating layer 17 is removed from the pixel electrode 16 by a photolithography process;

as shown in FIG. 8i, a second insulating layer 18 is formed, and the second insulating layer 18 is preferably made of a thin film material with high hydrogen content, such as SiH₄And ammonia NH₃The hydrogen content of the PECVD (plasma enhanced chemical vapor deposition) SiNx, which is a process gas, is usually 20% or more, and the thickness of the second insulating layer 18 is preferably 10 to 1000 nm. Experiments have shown that direct contact of the metal oxide semiconductor film 14 with PECVD SiNx will convert the metal oxide semiconductor into a conductor, i.e. naturally into a low-impedance transparent conductive oxide film required for the pixel electrode 16. That is, the metal oxide semiconductor thin film 14 in the pixel electrode region is changed into the pixel electrode 16, and the metal oxide semiconductor thin film 14 outside the pixel electrode region is the active layer 140.

In the present embodiment, the active layer 140 and the source/drain electrodes 15a and 15b are formed by etching in the same mask process, and the pixel electrode 16 and the active layer 140 are located at the same layer. The area of the orthographic projection of the active layer 140 on the substrate 11 is larger than the area of the orthographic projection of the source/drain electrodes 15a and 15b on the substrate 11.

The common electrode 19 is next formed on the second insulating layer 18.

The present invention further provides a metal oxide thin film transistor, which is formed by the manufacturing method of the metal oxide thin film transistor, and the detailed structure is described with reference to the above embodiments, which is not repeated herein.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, including not only those elements listed, but also other elements not expressly listed.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.