阅读说明：本技术 预测内部操作是否可执行的存储器系统和数据处理系统 (Memory system and data processing system for predicting whether internal operation is executable ) 是由 李硕晙 于 2020-07-01 设计创作，主要内容包括：本公开涉及一种存储器系统,包括：存储器装置,包括多个存储块；以及控制器,适用于：基于从主机周期性输入的系统信息,周期性地生成执行信息,执行信息指示在没有从主机输入的命令的情况下,待对多个存储块执行的内部操作是否可执行；累积地存储所生成的执行信息；基于所累积的执行信息,确定内部操作在当前周期随后的周期内是否可执行；并且根据确定的结果,在随后的周期期间对多个存储块执行内部操作。(The present disclosure relates to a memory system comprising: a memory device comprising a plurality of memory blocks; and a controller adapted to: periodically generating execution information indicating whether an internal operation to be performed on the plurality of memory blocks is executable without a command input from the host, based on system information periodically input from the host; cumulatively storing the generated execution information; determining whether the internal operation is executable in a period subsequent to the current period based on the accumulated execution information; and performing an internal operation on the plurality of memory blocks during a subsequent cycle according to a result of the determination.)

1. A memory system comprises

A memory device comprising a plurality of memory blocks; and

a controller:

periodically generating execution information indicating whether an internal operation to be performed on the plurality of memory blocks is executable without a command input from a host, based on system information periodically input from the host;

cumulatively storing the generated execution information;

determining whether the internal operation is executable in a period subsequent to a current period based on the accumulated execution information; and is

Performing the internal operation on the plurality of memory blocks during a subsequent cycle according to a result of the determination.

2. The memory system of claim 1, wherein the system information comprises:

power supply information indicating stability and sustainability of the power supply in each cycle;

reservation operation information indicating whether there is a command to be transmitted from the host in each cycle; and

operating environment information regarding an operating environment of the host for each cycle.

3. The memory system according to claim 2, wherein when the controller determines that the power supply is stable and sustainable in each cycle, there is no command to be transmitted from the host in each cycle, and the operating environment is an environment in which the internal operation is executable in each cycle, the controller generates the execution information indicating that the internal operation is executable in each cycle.

4. The memory system according to claim 3, wherein the controller determines whether the internal operation is executable in a subsequent cycle based on a latest one or more pieces within the accumulated execution information.

5. The memory system according to claim 4, wherein the controller determines whether the internal operation is executable in a subsequent cycle based on a pattern of a latest bar.

6. The memory system according to claim 5, wherein the memory unit is a single memory unit,

wherein when the controller does not detect that the pattern has any tendency or detects that the pattern indicates that the internal operation is not executable in a subsequent period, the controller determines that the internal operation is not executable in the subsequent period, and

wherein when the controller determines that the internal operation is not executable in a subsequent cycle, the controller skips the internal operation in the subsequent cycle.

7. The memory system of claim 3, wherein the operating environment information includes at least one of information about a temperature of the memory system and information about mobility of the memory system.

8. The memory system according to claim 1, wherein the controller further interrupts the internal operation and performs an operation in response to a command input from the host while the internal operation is being performed.

9. The memory system according to claim 1, wherein the memory unit is a single memory unit,

wherein when the internal operation is an erase operation, the controller further manages an erase block list of blocks that need to be erased among the plurality of memory blocks,

wherein the controller further manages a source block list of blocks satisfying a reference condition for the background operation among the plurality of storage blocks when the internal operation is a background operation,

wherein the controller performs the erase operation with reference to the erase block list, an

Wherein the controller performs the background operation with reference to the source block list.

10. A data processing system comprising:

a host periodically generating and outputting system information; and

a memory system comprising a memory device having a plurality of memory blocks, and:

periodically generating execution information indicating whether an internal operation to be performed on the plurality of memory blocks is executable without a command input from the host, based on the system information;

cumulatively storing the generated execution information;

determining whether the internal operation is executable in a period subsequent to a current period based on the accumulated execution information; and is

Performing the internal operation on the plurality of memory blocks during a subsequent cycle according to a result of the determination.

11. The data processing system of claim 10, wherein the system information comprises:

power supply information indicating stability and sustainability of the power supply in each cycle;

reservation operation information indicating whether there is a command to be transmitted from the host in each cycle; and

operating environment information regarding an operating environment of the host for each cycle.

12. The data processing system of claim 11, wherein when the memory system determines that the power supply is stable and sustainable in each cycle, there is no command to be transmitted from the host in each cycle, and the operating environment is an environment in which the internal operation is executable in each cycle, the memory system generates the execution information indicating that the internal operation is executable in each cycle.

13. The data processing system of claim 12, wherein the memory system determines whether the internal operation is executable in a subsequent cycle based on a most recent one or more of the accumulated execution information.

14. The data processing system of claim 13, wherein the memory system determines whether the internal operation is executable in a subsequent cycle based on a pattern of a latest stripe.

15. The data processing system of claim 14,

wherein when the memory system does not detect the pattern or detects that the pattern indicates that the internal operation is not executable in a subsequent cycle, the memory system determines that the internal operation is not executable in a subsequent cycle, and

wherein when the memory system determines that the internal operation is not executable in a subsequent cycle, the memory system skips the internal operation in the subsequent cycle.

16. The data processing system of claim 12, wherein the operating environment information includes at least one of information about a temperature of the memory system and information about mobility of the memory system.

17. The data processing system of claim 10, wherein the memory system further interrupts the internal operation and performs an operation in response to a command input from the host while the internal operation is being performed.

18. The data processing system of claim 10,

wherein when the internal operation is an erase operation, the memory system further manages an erase block list of blocks that need to be erased among the plurality of memory blocks,

wherein, when the internal operation is a background operation, the memory system further manages a source block list of blocks that satisfy a reference condition for the background operation among the plurality of storage blocks,

wherein the memory system performs the erase operation with reference to the erase block list, an

Wherein the memory system performs the background operation with reference to the source block list.

19. The data processing system of claim 11, wherein the host further changes the sleep mode to an awake mode when the memory system is in a sleep mode and then outputs the system information to the memory system.

20. A method of operation of a controller for controlling a memory device, the method of operation comprising:

periodically collecting first information on performability of internal operations of the memory device during each period for a predetermined duration; and

controlling the memory device to perform the internal operation based on a value pattern of the collected first information;

wherein the first information is collected at each cycle based on second information indicating one or more of:

stability and sustainability of the power supply in each cycle;

a command to be provided in each cycle, the command requesting a slave operation of the memory device; and

an operating environment of the memory device for each cycle.

Technical Field

Various exemplary embodiments relate to a memory system, and more particularly, to a memory system capable of predicting whether an internal operation is executable or not and a data processing system including the same.

Background

Recently, computer environment paradigms have turned into pervasive computing with near anytime and anywhere access to computer systems. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like is increasing. Such portable electronic devices typically use or include a memory system, i.e., a data storage device, that uses or embeds at least one memory device. The data storage device may be used as a primary storage device or a secondary storage device for the portable electronic device.

In a computing device, unlike a hard disk, a data storage device used as a nonvolatile semiconductor memory device has advantages of excellent stability and durability due to the absence of a mechanical driving part (e.g., a robot arm), and high data access speed and low power consumption. Examples of such data storage devices include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and Solid State Drives (SSDs).

Disclosure of Invention

Various embodiments of the present disclosure are directed to a memory system, a data processing system, and an operating method of the memory system, which may minimize complexity and performance degradation of the memory system, maximize the use efficiency of a memory device, and rapidly and stably process data within the memory device.

Various embodiments of the present disclosure are directed to a memory system and a data processing system including the same, which may determine whether to perform an internal operation by predicting whether the internal operation is executable based on system information periodically input from a host.

These and other features and advantages of the present disclosure are not limited to the embodiments described above, and will be understood by those skilled in the art from the following detailed description, taken in conjunction with the accompanying drawings.

According to an embodiment of the present invention, a memory system may include: a memory device comprising a plurality of memory blocks; and a controller adapted to: periodically generating execution information indicating whether an internal operation to be performed on the plurality of memory blocks is executable without a command input from the host, based on system information periodically input from the host; cumulatively storing the generated execution information; determining whether the internal operation is executable in a period subsequent to the current period based on the accumulated execution information; and performing an internal operation on the plurality of memory blocks during a subsequent cycle according to a result of the determination.

The system information may include: power supply information indicating stability and sustainability of the power supply in each cycle; reservation operation information indicating whether there is a command to be transmitted from the host in each cycle; and operating environment information regarding the operating environment of the host computer in each cycle.

When the controller determines that the power supply is stable and sustainable in each cycle, that there is no command to be transmitted from the host in each cycle, and that the operating environment is an environment in which the internal operation is executable in each cycle, the controller may generate execution information indicating that the internal operation is executable in each cycle.

The controller may determine whether the internal operation is executable in a subsequent cycle based on the latest one or more pieces of the accumulated execution information.

The controller may determine whether the internal operation is executable in a subsequent cycle based on the pattern of the latest bar.

When the controller does not detect that the pattern has any tendency or detects that the pattern indicates that the internal operation is not executable in the subsequent period, the controller may determine that the internal operation is not executable in the subsequent period, and when the controller determines that the internal operation is not executable in the subsequent period, the controller may skip the internal operation in the subsequent period.

The operating environment information may include at least one of information on a temperature of the memory system and information on mobility of the memory system.

The controller may be further adapted to interrupt the internal operation and perform the operation in response to a command input from the host while the internal operation is being performed.

When the internal operation is an erase operation, the controller may be further adapted to manage an erase block list of blocks to be erased among the plurality of memory blocks; when the internal operation is a background operation, the controller may be further adapted to manage a source block list of blocks that satisfy a reference condition of the background operation among the plurality of storage blocks; the controller may perform an erase operation with reference to the erase block list, and the controller may perform a background operation with reference to the source block list.

According to an embodiment of the present invention, a data processing system may include: a host adapted to periodically generate and output system information; and a memory system comprising a memory device, the memory device comprising a plurality of memory blocks, and the memory system being adapted to: periodically generating execution information indicating whether an internal operation to be performed on the plurality of memory blocks is executable without a command input from the host, based on the system information; cumulatively storing the generated execution information; determining whether the internal operation is executable in a period subsequent to the current period based on the accumulated execution information; and performing an internal operation on the plurality of memory blocks during a subsequent cycle according to a result of the determination.

The system information may include: power supply information indicating stability and sustainability of the power supply in each cycle; reservation operation information indicating whether there is a command to be transmitted from the host in each cycle; and operating environment information regarding the operating environment of the host computer in each cycle.

When the memory system determines that the power supply is stable and sustainable in each cycle, there is no command to be transmitted from the host in each cycle, and the operating environment is an environment in which the internal operation is executable in each cycle, the memory system may generate execution information indicating that the internal operation is executable in each cycle.

The memory system may determine whether the internal operation is executable in a subsequent cycle based on the latest one or more pieces of the accumulated execution information.

The memory system may determine whether the internal operation is executable in a subsequent cycle based on the pattern of the latest stripe.

When the memory system does not detect the pattern or detects that the pattern indicates that the internal operation is not executable in a subsequent cycle, the memory system may determine that the internal operation is not executable in the subsequent cycle, and when the memory system determines that the internal operation is not executable in the subsequent cycle, the memory system may skip the internal operation in the subsequent cycle.

The operating environment information may include at least one of information on a temperature of the memory system and information on mobility of the memory system.

The memory system may further be adapted to interrupt internal operations and perform operations in response to commands input from the host while internal operations are being performed.

When the internal operation is an erase operation, the memory system may be further adapted to manage an erase block list of blocks that need to be erased among the plurality of memory blocks; when the internal operation is a background operation, the memory system may be further adapted to manage a source block list of blocks satisfying a reference condition for the background operation among the plurality of memory blocks; the memory system may perform an erase operation with reference to the erase block list and the memory system may perform a background operation with reference to the source block list.

The host may be further adapted to change the sleep mode to the awake mode and then output the system information to the memory system when the memory system is in the sleep mode.

According to an embodiment of the present invention, an operating method of a controller for controlling a memory device may include: periodically collecting first information regarding performability of internal operations of the memory device during each period for a predetermined duration; and controlling the memory device to perform an internal operation based on the value pattern of the collected first information, the first information may be collected at each cycle based on second information indicating one or more of: stability and sustainability of the power supply in each cycle; a command to be provided in each cycle, the command requesting a slave operation of the memory device; and the operating environment of the memory device per cycle.

Drawings

FIG. 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Fig. 3 is a block diagram illustrating a controller included in a memory system according to an embodiment of the present invention.

Fig. 4 is a table showing an example of an operation method of the memory system according to an embodiment of the present invention.

Detailed Description

Various examples of the disclosure are described in more detail below with reference to the accompanying drawings. However, the aspects and features of the present invention can be implemented differently to form other embodiments including variations of any of the disclosed embodiments. Accordingly, the present invention should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and examples of the disclosure. It is noted that references to "an embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment.

It will be understood that, although the terms first, second, third, etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element, or to distinguish one element from another element by the same or similar name. Thus, a first element in one example may be termed a second or third element in another example without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and in some instances the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it will be understood that the former may be directly connected or coupled to the latter, or electrically connected or coupled to the latter via one or more intervening elements therebetween. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms and vice versa unless the context clearly indicates otherwise. Similarly, the indefinite articles "a" and "an" mean one or more, unless clearly indicated by the language or context only one.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in view of this disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention.

It is also noted that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, as will be apparent to those of ordinary skill in the relevant art, unless specifically noted otherwise.

Embodiments of the present disclosure are described in detail below with reference to the drawings, wherein like reference numerals refer to like elements.

FIG. 1 is a block diagram illustrating a data processing system 100 including a memory system 110 according to an embodiment of the invention.

For example, the memory system 110 may be installed on a computing or mobile device and then connected with the host 102 to transmit and receive data.

Referring to FIG. 1, data processing system 100 includes a host 102 and a memory system 110. Memory system 110 includes a controller 130 and a memory device 150. The controller 130 includes an execution information generation block 1301, an execution information analysis block 1302, and an internal operation execution block 1303. The internal operation execution block 1303 includes a list management unit 1304 and an internal operation execution control unit 1305. Memory device 150 includes a plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4, >. The host 102 includes a system information generation block 1021.

The controller 130 may perform a read operation, a program operation, an erase operation, and a background operation. The controller 130 may perform a read operation to output data requested by the host 102 or data required in the memory system 110 from the memory device 150. The controller 130 may perform a programming operation to store data transmitted from the host 102 or data generated in the memory system 110 in the memory device 150. The controller 130 may perform an erase operation to erase data stored in the memory device 150. The controller 130 may perform background operations to manage data stored in the memory device 150.

The internal configuration of the memory device 150 may vary according to the characteristics of the memory device 150, the purpose of using the memory system 110, or the specification of the memory system 110 requested by the host 102.

For example, the memory device 150 may be implemented as a non-volatile memory device, such as a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a spin transfer torque random access memory (STT-RAM), and so on.

Memory device 150 may be implemented as a three-dimensional array structure. Embodiments of the present disclosure may be applied to a charge extraction flash (CTF) memory device in which a charge storage layer is formed of a dielectric layer and a flash memory device in which a charge storage layer is formed of a conductive floating gate.

The memory device 150 is configured to receive a command and an address, etc. from the controller 130 and access a region of the memory cell array selected by the address. In other words, the memory device 150 may perform an operation corresponding to the command on the area selected by the address.

For example, the memory device 150 may perform a program operation, a read operation, and an erase operation. In this regard, the memory device 150 may program data into the region selected by the address during a program operation. During a read operation, the memory device 150 may read data from the area selected by the address. During an erase operation, the memory device 150 may erase data stored in the area selected by the address.

The controller 130 may control the operation of the memory device 150 according to the request of the host 102 or regardless of the request of the host 102.

For example, memory controller 130 may control write (i.e., program) operations, read operations, erase operations, and background operations of memory device 150. Background operations may be, for example, Garbage Collection (GC) operations, Wear Leveling (WL) operations, Bad Block Management (BBM) operations, and the like.

The controller 130 may control the operation of the memory system 110 by executing firmware. To control the overall operation of the memory device 150 and perform logical operations, the controller 130 may load and run firmware into the memory 144 during boot time, or drive the firmware. For example, the firmware may be stored in memory device 150 and then loaded into memory 144.

The firmware, which is a program running in the memory system 110, may include, for example, a Flash Translation Layer (FTL), a Host Interface Layer (HIL), and a Flash Interface Layer (FIL). The FTL may perform translation functions between logical addresses of the memory system 110 requested by the host 102 and physical addresses of the memory devices 150. The HIL may be used to interpret commands requested by the host 102 from the memory system 110 as a storage device and transmit the commands to the FTL. The FIL may transmit the command indicated by the FTL to the memory device 150.

The host 102 according to the embodiment of the present disclosure may periodically generate and output system information VSENS, OPREV, and evenns to the memory system 110. For example, when the period is one hour, the host 102 may generate and output system information VSENS, OPREV, and evenns to the memory system 110 every hour.

The host 102 may check whether the memory system 110 is in the awake state every cycle in which the system information VSENS, OPREV, and evens are generated and output to the memory system 110. When the memory system 110 is in the sleep state at the beginning of the period, the host 102 may change the state of the memory system 110 to the awake state and then output the system information VSENS, OPREV, and evensens to the memory system 110.

The system information VSENS, OPREV, and evens may include at least one of power supply information VSENS, reserved operation information OPREV, and operation environment information evens.

The power supply information VSENS may be generated by the power supply detection unit 1022 included in the system information generation block 1021. In other words, the power supply detecting unit 1022 may check the power supply state detected at each cycle and output the power supply state as the power supply information VSENS to the memory system 110. For example, when the data processing system 100 including the host 102 is a mobile device, the power supply detection unit 1022 may generate information corresponding to whether the mobile device is being charged and information of the current remaining battery power as the power supply information VSENS.

The reservation operation information OPREV may be generated by the reservation operation management unit 1023 included in the system information generation block 1021. In other words, the reservation operation management unit 1023 may check whether there is a reservation command to be transmitted to the host 102 of the memory system 110 in each cycle. For example, when the data processing system 100 including the host 102 is a mobile device, the reservation operation management unit 1023 may generate information corresponding to whether the mobile device has an operation reserved in advance and information on whether a reservation operation is to be performed in each cycle as the reservation operation information OPREV.

The operational environment information EVSENS may be generated by the operational environment detection unit 1024 included in the system information generation block 1021. In other words, the operating environment detecting unit 1024 may check the operating environment of the host 102 detected at each cycle and output the operating environment to the memory system 110 as the operating environment information EVSENS. For example, when the data processing system 100 including the host 102 is a mobile device, the operating environment detecting unit 1024 may generate information on the internal temperature or the external temperature of the mobile device and information on the mobility of the mobile device as the operating environment information EVSENS.

The memory system 110 may periodically generate execution information OPINFO indicating whether an internal operation can be performed on a plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4, > during each cycle in response to system information VSENS, OPREV, and evenns input from the host 102, and store the execution information OPINFO as accumulated execution information OPINFO <1: N >. In addition, the memory system 110 may estimate the executability of the internal operation during the current cycle based on the accumulated execution information OPINFO <1: N > accumulated during the predetermined duration of the plurality of cycles, and perform the internal operation on the plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4,. according to the result of the estimation. Internal operations may be performed within the memory system 110 without any commands or data being provided from the host 102. For example, the internal operation of the memory system 110 may be an erase operation performed on some BLOCKs of the plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4. Additionally, the internal operations of the memory system 110 may be background operations, i.e., garbage collection operations, wear leveling operations, read reclamation operations, and bad BLOCK management operations, performed on some of the plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4.

Specifically, the execution information generation BLOCK 1301 included in the controller 130 of the memory system 110 may generate the execution information OPINFO indicating whether an internal operation can be performed on a plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4. The execution information generation block 1301 may periodically generate a piece of execution information OPINFO.

In this case, the system information VSENS, OPREV, and evens may include at least one of the power supply information VSENS, the reserved operation information OPREV, and the operation environment information evens.

Accordingly, when it is determined by the power supply information VSENS that the power supply per cycle is stable and sustainable, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is executable during each cycle and generate the execution information OPINFO indicating that the internal operation is executable. In other words, the execution information generation block 1301 may check the power supply state of the host 102 at each cycle through the power supply information VSENS, and determine whether the power supply is stable and sustainable during each cycle through the result of the check.

For example, when data processing system 100 including host 102 and memory system 110 is a mobile device, power supply information VSENS input from host 102 may include information indicating that the mobile device is charging and that the current remaining battery power is 80%. When such power supply information VSENS is input at each cycle, the execution information generation block 1301 may determine that the power supply will be stable and sustainable during each cycle. Accordingly, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is executable at each cycle, and generate the execution information OPINFO indicating that the internal operation is executable. Alternatively, the power supply information VSENS input from the host 102 may include information indicating that the mobile device is not being charged and the current remaining battery power is 5%. When such power supply information VSENS is input at each cycle, the execution information generation block 1301 may determine that the power supply is not stable and sustainable during each cycle. Accordingly, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is not executable at each cycle, and generate the execution information OPINFO indicating that the internal operation is not executable.

When it is determined by the reservation operation information OPREV that there is no command to be transferred from the host 102 to the memory system 110 during each cycle, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is executable in each cycle, and generate the execution information OPINFO indicating that the internal operation is executable. That is, the execution information generation block 1301 may check whether there is a reservation command to be transferred to the memory system 110 in the host 102 per cycle through the reservation operation information OPREV, and check a point in time when the command is to be executed. When there is no command or it is checked that the command is not executed in every cycle even if there is a command, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is executable during every cycle and generate the execution information OPINFO indicating that the internal operation is executable.

When it is determined by the operating environment information EVSENS that the operating environment is an environment in which the internal operation of the memory system 110 is executable at each cycle, the execution information generation block 1301 may generate execution information OPINFO indicating that the internal operation is executable. In other words, the execution information generation block 1301 may check the operating environment of the host 102 at each cycle by the operating environment information EVSENS, and determine whether the operating environment of the host 102 is an environment in which the internal operation of the memory system 110 can be executed during each cycle by the result of the check.

For example, when the data processing system 100 including the host 102 and the memory system 110 is a mobile device, information indicating that the internal temperature or the external temperature of the mobile device is 25 degrees and the mobile device is not moving may be included in the operating environment information EVSENS input from the host 102. When such operating environment information EVSENS is input at each cycle, the execution information generation block 1301 may determine that the operating environment is an environment in which the internal operations of the memory system 110 are executable during each cycle. Accordingly, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is executable during each cycle, and generate the execution information OPINFO indicating that the internal operation is executable. Alternatively, information indicating that the internal temperature or the external temperature of the mobile device is 55 degrees and that the mobile device is moving may be included in the operating environment information EVSENS input from the host 102. When such operating environment information EVSENS is input at each cycle, the execution information generation block 1301 may determine that the operating environment is an environment in which the internal operations of the memory system 110 are not executable during each cycle. Accordingly, the execution information generation block 1301 may determine that the internal operation of the memory system 110 is not executable during each cycle, and generate the execution information OPINFO indicating that the internal operation is not executable.

The above description exemplifies that the execution information generation block 1301 generates the execution information OPINFO in response to any one of the power supply information VSENS, the contracted operation information OPREV, and the operation environment information evenns. This is merely an embodiment of the present disclosure provided for convenience of description, and as another example, the execution information generation block 1301 may also perform an operation of generating the execution information OPINFO in response to at least two of the power supply information VSENS, the reservation operation information OPREV, and the operation environment information evenns. The execution information generation block 1301 may also perform an operation of generating the execution information OPINFO in response to all of the power supply information VSENS, the reservation operation information OPREV, and the operation environment information evenns. In other words, when it is determined through the power supply information VSENS that the power supply is stable and sustainable during each cycle, it is determined through the reservation operation information that there is no command to be transmitted from the host 102 during each cycle, and it is determined through the operation environment information EVSENS that the operation environment is an environment in which the internal operation can be performed, the controller 130 of the memory system 110 may determine that the internal operation is executable in the memory system 110, and generate the execution information OPINFO indicating that the internal operation is executable.

The execution information analysis block 1302 included in the controller 130 of the memory system 110 may accumulate the execution information OPINFO generated by the execution information generation block 1301 and convert the accumulated execution information OPINFO <1: n > is stored in memory device 150. Subsequently, the execution information analysis BLOCK 1302 may analyze the accumulated execution information OPINFO <1: N > and selectively perform an internal operation on the plurality of memory BLOCKs BLOCK <0, 1, 2, 3, 4,. depending on the result of the analysis. In this case, the fact that the execution information analysis block 1302 analyzes the execution information OPINFO <1: N > corresponding to the respective cycles means that the memory system 110 estimates the performability of the internal operation in the current cycle based on the execution information OPINFO <1: N > accumulated for a predetermined duration of a plurality of previous cycles, and selects whether to perform the internal operation on the memory system 110 in the current cycle according to the result of the estimation.

Specifically, the execution information analysis block 1302 may not analyze the accumulated execution information OPINFO <1: N >, but store the values of the execution information OPINFO <1: N > in the memory device 150 until the number of accumulated execution information OPINFO periodically generated by the execution information generation block 1301 becomes a predetermined number. For example, when the cycle is 1 hour, the execution information analysis block 1302 does not analyze the accumulated execution information OPINFO <1: N > until the number of the accumulated execution information OPINFO <1: N > becomes 24, and the execution information OPINFO periodically generated by the execution information generation block 1301 may be accumulated and stored in the memory device 150 for 24 hours.

When the accumulated execution information OPINFO <1: N > is accumulated in a predetermined number, the execution information analysis BLOCK 1302 may check a value pattern of the accumulated execution information OPINFO <1: N >, predict the execution information OPINFO < N +1> to be accumulated later according to the checked result, and determine whether to execute an internal operation on the memory BLOCK <0, 1, 2, 3, 4,. that. In addition, when the accumulated execution information OPINFO <1: N > exceeds a predetermined number, the execution information analysis block 1302 may check the accumulated execution information OPINFO <1: at least some of the most recently accumulated execution information OPINFO < N-K: n > predicts execution information OPINFO < N +1> to be accumulated later according to the result of the check, and determines whether to execute an internal operation on the memory BLOCK <0, 1, 2, 3, 4. Herein, "K" may be a natural number less than or equal to "N". In this case, when the execution information OPINFO <1: N > is accumulated by a predefined limited number because the execution information OPINFO <1: N > cannot be accumulated indefinitely, the execution information analysis block 1302 may sequentially remove the execution information OPINFO <1: N > from the earliest accumulated execution information.

Specifically, when the execution information OPINFO < N +1> to be accumulated later passes through the accumulated execution information OPINFO <1: at least some of N > perform the information OPINFO < N-K: the value pattern of N > predicts that an internal operation is executable, the execution information analysis BLOCK 1302 may enable the operation start signal OPST during a subsequent cycle, so that the internal operation execution BLOCK 1303 may execute the internal operation on the memory BLOCK <0, 1, 2, 3, 4. In addition, when the execution information OPINFO <1: at least some of N > perform the information OPINFO < N-K: n >, when the amount of execution information indicating that the internal operation can be executed is greater than the amount of execution information indicating that the internal operation cannot be executed, the execution information analysis BLOCK 1302 may enable the operation start signal OPST during a subsequent cycle, so that the internal operation execution BLOCK 1303 may execute the internal operation on the memory BLOCK <0, 1, 2, 3, 4. Further, when the execution information OPINFO < N +1> to be accumulated later is determined by comparing the accumulated execution information OPINFO <1: n > at least some of the execution information OPINFO < N-K: n > the checked value pattern predicts that the internal operation is executable, and in the accumulated execution information OPINFO <1: at least some of N > perform the information OPINFO < N-K: n >, when the number of execution information indicating that the internal operation can be executed is greater than the number of execution information indicating that the internal operation cannot be executed, the execution information analysis BLOCK 1302 may enable the operation start signal OPST during a subsequent cycle, so that the internal operation execution BLOCK 1303 may execute the internal operation on the memory BLOCK <0, 1, 2, 3, 4.

Alternatively, when the accumulated execution information OPINFO <1: at least some of the N > perform the information OPINFO < N-K: when the value pattern of N > cannot be determined, the execution information analysis BLOCK 1302 may disable the operation start signal OPST during a subsequent cycle, thereby making the internal operation execution BLOCK 1303 unable to execute an internal operation on the memory BLOCK <0, 1, 2, 3, 4. In addition, when the execution information OPINFO < N +1> to be accumulated later is determined by comparing the accumulated execution information OPINFO <1: at least some of N > perform the information OPINFO < N-K: n > the checked value pattern indicates that the internal operation is not executable, the execution information analysis BLOCK 1302 may disable the operation start signal OPST during a subsequent cycle, thereby disabling the internal operation execution BLOCK 1303 from executing the internal operation on the memory BLOCK <0, 1, 2, 3, 4, ·> during the subsequent cycle. Further, when the execution information OPINFO <1: at least some of N > perform the information OPINFO < N-K: among N >, when the number of execution information indicating that the internal operation is not executable is larger than the number of execution information indicating that the internal operation is executable, the execution information analysis BLOCK 1302 may disable the operation start signal OPST, so that the internal operation execution BLOCK 1303 cannot execute the internal operation on the memory BLOCK <0, 1, 2, 3, 4.

The internal operation execution BLOCK 1303 may execute an internal operation on the memory BLOCK <0, 1, 2, 3, 4, ·> included in the memory device 150 in response to the state of the operation start signal OPST input from the execution information analysis BLOCK 1302. In other words, the internal operation execution BLOCK 1303 may perform an internal operation on the memory BLOCK <0, 1, 2, 3, 4, ·> during a period in which the operation start signal OPST input from the execution information analysis BLOCK 1302 is enabled. In contrast, the internal operation execution BLOCK 1303 may not execute the internal operation on the memory BLOCK <0, 1, 2, 3, 4, ·> during a period in which the operation start signal OPST input from the execution information analysis BLOCK 1302 is disabled.

In addition, when a command is input from the host 102 while an internal operation is being performed in response to the operation start signal OPST being enabled, the internal operation performing block 1303 may interrupt the internal operation being performed. In other words, the host 102 may transmit the command to the memory system 110 at an unexpected point in time, and the point in time at which the command is transmitted may be the time at which the internal operation execution block 1303 of the controller 130 is executing the internal operation. In this case, the internal operation execution block 1303 may interrupt the internal operation being executed. At this time, the controller 130 may perform an operation corresponding to a command input from the host 102, in addition to the interruption of the internal operation by the internal operation performing block 1303.

The list management unit 1304 included in the internal operation execution BLOCK 1303 may manage, in the form of a list, BLOCKs on which an internal operation needs to be executed among the memory BLOCKs BLOCK <0, 1, 2, 3, 4. For example, when the internal operation is an erase operation, the list management unit 1304 may manage an erase BLOCK list of BLOCKs of the memory BLOCK <0, 1, 2, 3, 4. For another example, when the internal operation is a background operation, the list management unit 1304 may manage a source BLOCK list of BLOCKs among the memory BLOCKs BLOCK <0, 1, 2, 3, 4.

During a period in which the operation start signal OPST is enabled, the internal operation execution control unit 1305 included in the internal operation execution BLOCK 1303 may execute an internal operation, such as an erase operation or a background operation, on the memory BLOCK <0, 1, 2, 3, 4,. > included in the memory device 150 with reference to the BLOCK list BKLIST, such as an erase BLOCK list or a source BLOCK list, input from the list management unit 1304. In addition, the internal operation execution BLOCK 1303 may interrupt an internal operation being executed when a command is input from the host 102 while the internal operation is being executed on the memory BLOCK <0, 1, 2, 3, 4,. > during a period in which the operation start signal OPST is disabled.

FIG. 2 is a block diagram illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 2, data processing system 100 may include a host 102 engaged with or operatively coupled to a memory system 110.

For example, the host 102 may include any of a variety of portable electronic devices, such as a mobile phone, an MP3 player, and a laptop computer, or a non-portable electronic device, such as a desktop computer, a game machine, a Television (TV), a projector, and so forth.

The host 102 also includes at least one Operating System (OS) and functions that may generally manage and control the execution in the host 102. The OS may provide interoperability between the host 102 interfacing with the memory system 110 and a user of the memory system 110. The OS may support functions and operations corresponding to a request of a user. By way of example and not limitation, depending on the mobility of host 102, the OS may include a general purpose operating system and a mobile operating system. General-purpose operating systems can be divided into personal operating systems and enterprise operating systems, depending on system requirements or the user's environment. Personal operating systems, including Windows and Chrome, may be subject to support services for general purposes. Enterprise operating systems may be dedicated to ensuring and supporting high performance, including Windows servers, Linux, and Unix. In addition, Mobile operating systems may include Android, iOS, and Windows Mobile. The mobile operating system may be subject to support services or functions for mobility (e.g., power saving functions). The host 102 may include multiple operating systems. Host 102 may cooperate with memory system 110 to run multiple operating systems in response to a user's request. The host 102 may transfer a plurality of commands corresponding to the user's request into the memory system 110, thereby performing operations corresponding to the commands within the memory system 110. Processing multiple commands in the memory system 110 is described below with reference to FIG. 4.

The memory system 110 may perform particular functions or operations in response to requests from the host 102, and, in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a primary memory system or a secondary memory system for the host 102. The memory system 110 may be implemented using any of various types of memory devices that may be electrically coupled with the host 102 according to the protocol of the host interface. Non-limiting examples of suitable storage devices include Solid State Drives (SSDs), multimedia cards (MMCs), embedded MMCs (emmcs), small-size MMCs (RS-MMCs), micro MMCs, Secure Digital (SD) cards, mini SDs, micro SDs, Universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, Compact Flash (CF) cards, Smart Media (SM) cards, and memory sticks.

The storage devices used as the memory system 110 may be implemented using volatile memory devices, such as Dynamic Random Access Memory (DRAM) or static RAM (sram), and/or non-volatile memory devices, such as Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), ferroelectric RAM (fram), phase change RAM (pram), magnetoresistive RAM (mram), resistive RAM (RRAM or ReRAM), or flash memory.

Memory system 110 may include a controller 130 and a memory device 150. Memory device 150 may store data to be accessed by host 102. Controller 130 may control the storage of data in memory device 150.

The controller 130 and the memory device 150 may be integrated into a single semiconductor device, which may be included in any of various types of memory systems as exemplified above.

By way of example and not limitation, controller 130 and memory device 150 may be integrated into a single semiconductor device. The controller 130 and the memory device 150 may be thus integrated to form an SSD for improving an operation speed. When the memory system 110 is used as an SSD, the operation speed of the host 102 connected to the memory system 110 can be increased more than the operation speed of the host 102 connected to the hard disk. In another embodiment, the controller 130 and the memory device 150 may be integrated into one semiconductor device to form a memory card, such as a PC card (PCMCIA), a compact flash Card (CF), a smart media card (e.g., SM, SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, micro MMC), a Secure Digital (SD) card (e.g., SD, mini SD, micro SD, SDHC), or a general flash memory.

The memory system 110 may be configured as, for example, a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, a computer, a, Configuring one of various electronic devices of a telematics network, a Radio Frequency Identification (RFID) device, or configuring a portion of one of various components of a computing system.

The memory device 150 may be a non-volatile memory device and may retain data stored therein even if power is not supplied. The memory device 150 may store data provided from the host 102 through a write operation while providing data stored therein to the host 102 through a read operation. Memory device 150 may include a plurality of memory blocks 152, 154, 156, each of which may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells electrically coupled with a plurality of Word Lines (WLs). Memory device 150 also includes a plurality of memory dies, each memory die including a plurality of planes, each plane including a memory block among a plurality of memory blocks 152, 154, 156. In addition, the memory device 150 may be a non-volatile memory device, such as a flash memory, wherein the flash memory may be a three-dimensional stacked structure.

The controller 130 may control overall operations of the memory device 150, such as a read operation, a write operation, a program operation, and an erase operation. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. Controller 130 may provide data read from memory device 150 to host 102. The controller 130 may store data provided by the host 102 into the memory device 150.

Controller 130 may include a host interface (I/F)132, a processor 134, Error Correction Code (ECC) circuitry 138, a Power Management Unit (PMU)140, a memory interface (I/F)142, and a memory 144, all operatively coupled via an internal bus.

The host interface 132 may process commands and data provided from the host 102 and may communicate with the host 102 through at least one of various interface protocols such as: universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), serial SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). According to an embodiment, the host interface 132 is a component for exchanging data with the host 102, which may be implemented by firmware called a Host Interface Layer (HIL).

The ECC circuitry 138 may correct erroneous bits of data to be processed in the memory device 150 (e.g., output from the memory device 150), which may include an ECC encoder and an ECC decoder. Here, the ECC encoder may perform error correction encoding on data to be programmed in the memory device 150 to generate encoded data to which parity bits are added and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder may detect and correct errors included in the data read from the memory device 150. In other words, after performing error correction decoding on data read from the memory device 150, the ECC circuit 138 may determine whether the error correction decoding has succeeded and output an instruction signal (e.g., a correction success signal or a correction failure signal). The ECC circuitry 138 may use the parity bits generated during the ECC encoding process to correct the erroneous bits of the read data. When the number of erroneous bits is greater than or equal to the threshold number of correctable erroneous bits, the ECC circuit 138 may not correct the erroneous bits, but may output an error correction failure signal indicating that the correction of the erroneous bits failed.

The ECC circuit 138 may perform error correction operations based on code modulation such as low density parity-even check (LDPC) codes, bose-charderurri-hodgkin (BCH) codes, turbo codes, reed-solomon (RS) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), or Block Coded Modulation (BCM). ECC circuitry 138 may include any and all circuits, modules, systems, or devices for performing error correction operations based on at least one of the above-described codes.

PMU140 may manage the power provided in controller 130. For example, PMU140 may detect power on and power off. In addition, PMU140 may include a power detector.

Memory interface 142 may serve as an interface for processing commands and data transmitted between controller 130 and memory devices 150 to allow controller 130 to control memory devices 150 in response to requests communicated from host 102. Memory interface 142 may generate control signals for memory device 150 and, where memory device 150 is a flash memory, and particularly where memory device 150 is a NAND flash memory, may process data input into memory device 150 or output from memory device 150 under the control of processor 134. Memory interface 142 may provide an interface for processing commands and data between controller 130 and memory device 150, such as the operation of a NAND flash interface, and particularly between controller 130 and memory device 150. According to an embodiment, memory interface 142 may be implemented as a component for exchanging data with memory device 150 by firmware called a Flash Interface Layer (FIL).

The memory 144 may support operations performed by the memory system 110 and the controller 130. The memory 144 may store temporary or transactional data generated or communicated for operation in the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may transfer data read from the memory device 150 into the host 102. The controller 130 may store data input through the host 102 in the memory device 150. Memory 144 may be used to store data needed by controller 130 and memory device 150 to perform operations such as read operations or program/write operations.

The execution information OPINFO generated by the execution information generation block 1301 described above with reference to fig. 1 may be temporarily stored in the memory 144 before being stored in the memory device 150 by the execution information analysis block 1302. In addition, the execution information analysis block 1302 described above with reference to fig. 1 may compare the accumulated execution information OPINFO <1: n > is temporarily stored in the memory 144, and then the execution information OPINFO <1: n > value.

The memory 144 may be implemented with volatile memory. The memory 144 may be implemented with Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), or both. Although fig. 2 illustrates the memory 144 disposed within the controller 130, the present invention is not limited to this arrangement. That is, the memory 144 may be internal or external to the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and/or signals between the memory 144 and the controller 130.

The memory 144 may store data for performing operations such as data writes and data reads requested by the host 102 and/or data transferred between the memory device 150 and the controller 130 for background operations such as garbage collection and wear leveling as described above. In accordance with an embodiment, to support operations in memory system 110, memory 144 may include program memory, data memory, write buffers/caches, read buffers/caches, data buffers/caches, and map buffers/caches.

Processor 134 may be implemented with a microprocessor or Central Processing Unit (CPU). The memory system 110 may include one or more processors 134. Processor 134 may control the overall operation of memory system 110. By way of example and not limitation, processor 134 may control a programming operation or a read operation of memory device 150 in response to a write request or a read request input from host 102. According to an embodiment, the processor 134 may use or run firmware to control the overall operation of the memory system 110. Herein, the firmware may be a Flash Translation Layer (FTL). The FTL may serve as an interface between the host 102 and the memory device 150. The host 102 may communicate requests for write operations and read operations to the memory device 150 through the FTL.

In some embodiments, processor 134 and memory interface unit 142 may be used to perform the operations of execution information generation block 1301, execution information analysis block 1302, and internal operation execution block 1303 described above with reference to fig. 1.

The FTL may manage address mapping, garbage collection, wear leveling, etc. In particular, the FTL may load, generate, update, or store mapping data. Accordingly, the controller 130 may map the logical address input from the host 102 with the physical address of the memory device 150 by the mapping data. Due to the address mapping operation, the memory device 150 may additionally be used as a general purpose storage device to perform a read operation or a write operation. Also, through the address mapping operation based on the mapping data, when the controller 130 attempts to update data stored in a specific page, the controller 130 may program the updated data on another blank page, and may invalidate old data of the specific page (e.g., update a physical address corresponding to a logical address of the updated data from the specific page to a newly programmed page) due to characteristics of the flash memory device. In addition, the controller 130 may store the mapping data of the new data in the FTL.

For example, the controller 130 uses the processor 134 when performing operations requested from the host 102 in the memory device 150. The processor 134, in conjunction with the memory device 150, may process instructions or commands corresponding to input commands from the host 102. The controller 130 may perform foreground operations as command operations, such as a program operation corresponding to a write command, a read operation corresponding to a read command, an erase/discard operation corresponding to an erase/discard command, and a parameter setting operation corresponding to a set parameter command or a set characteristic command with a set command, corresponding to a command from the host 102.

As another example, controller 130 may perform background operations on memory device 150 via processor 134. By way of example and not limitation, background operations of the memory device 150 include copying data of a memory block among the memory blocks 152, 154, 156 and storing the data in another memory block (e.g., a Garbage Collection (GC) operation). The background operation may include an operation (e.g., a Wear Leveling (WL) operation) to move data stored in at least one of the memory blocks 152, 154, 156 in the memory device 150 to at least another one of the memory blocks 152, 154, 156. During background operations, controller 130 may use processor 134 to store mapping data stored in controller 130 to at least one of memory blocks 152, 154, 156, e.g., a mapping cleanup operation. Another example of a background operation performed by processor 134 is a bad block management operation that checks for bad blocks among the plurality of memory blocks 152, 154, 156.

In the memory system 110, the controller 130 performs a plurality of command operations corresponding to a plurality of commands received from the host 102. For example, when performing a plurality of program operations corresponding to a plurality of program commands, a plurality of read operations corresponding to a plurality of read commands, and a plurality of erase operations corresponding to a plurality of erase commands sequentially, randomly, or alternately, the controller 130 may determine which channel(s) or via(s) for connecting the controller 130 to which memory die(s) in the memory 150 is or are appropriate to perform each operation. The controller 130 may send or communicate data or instructions via the determined channel or pathway for performing each operation. After each operation is completed, multiple memory dies may each transfer the results of the operation via the same channel or lane. The controller 130 may then transmit a response or acknowledgement signal to the host 102. In an embodiment, the controller 130 may check the status of each channel or each lane. In response to a command received from the host 102, the controller 130 may select at least one channel or lane based on the state of each channel or each lane so that instructions and/or operation results and data may be transferred via the selected channel or lane.

Controller 130 may check the status of a plurality of channels (or vias) coupled to a plurality of memory dies included in memory device 150.

By way of example and not limitation, controller 130 may identify a status with respect to a channel (or pathway) associated with a memory die in memory device 150. The controller 130 may determine that each channel or each lane is in a busy state, a ready state, an active state, an idle state, a normal state, or an abnormal state. The controller may determine through which channel or lane to transfer instructions (and/or data) based on the physical block address, e.g., the die to which the instructions (and/or data) are transferred. The controller 130 may refer to the descriptor transferred from the memory device 150. The descriptor may include a block or page that describes a parameter of an item of information about the memory device 150, which is data having a set format or structure. For example, the descriptors may include device descriptors, configuration descriptors, unit descriptors, and the like. The controller 130 may reference or use the descriptor to determine a channel or path to exchange instructions or data.

A management unit (not shown) may be included in processor 134. The management unit may perform bad block management of the memory device 150. The management unit can find bad memory blocks which are not ideal and can not be used continuously, and perform bad block management on the bad memory blocks. When the memory device 150 is a flash memory, such as a NAND flash memory, a program failure may occur during a write operation, such as during a program operation, due to the characteristics of the NAND logic function. During bad block management, data of a memory block that failed programming or a bad memory block may be programmed into a new memory block. The bad block may seriously deteriorate the utilization efficiency of the memory device 150 having the 3D stack structure and the reliability of the memory system 110. Thus, reliable bad block management may enhance or improve the performance of the memory system 110.

Fig. 3 is a block diagram illustrating a controller in a memory system according to another embodiment of the present invention.

Referring to FIG. 3, a controller 130 cooperates with the host 102 and the memory device 150. The controller 130 may include a host interface (I/F)132, a Flash Translation Layer (FTL) circuit 40, a memory interface (I/F)142, and a memory 144.

Although not shown in fig. 3, the ECC circuitry 138 in fig. 2 may be included in the Flash Translation Layer (FTL) circuitry 40, according to an embodiment. In another embodiment, the ECC circuitry 138 may be implemented as a separate module, circuit, or firmware included in the controller 130 or associated with the controller 130.

In some embodiments, the Flash Translation Layer (FTL) unit 40 and the memory interface unit 142 may function as the execution information generation block 1301, the execution information analysis block 1302, and the internal operation execution block 1303 described above with reference to fig. 1.

The host interface 132 is used to process commands and data from the host 102. By way of example and not limitation, host interface 132 may include command queue 56, buffer manager 52, and event queue 54. The command queue 56 may sequentially store commands and data from the host 102 and output the commands and data to the buffer manager 52 in the order of storage. The buffer manager 52 may sort, manage, or otherwise condition commands and data communicated from the command queue 56. The event queue 54 may sequentially transfer events for processing commands and data from the buffer manager 52.

Multiple commands or data of the same characteristics may be received continuously from the host 102, or commands and data of different characteristics may be transmitted to the memory system 110 after they are mixed or intermixed. For example, multiple commands for reading data (i.e., read commands) may be passed, or read commands and program/write commands may be alternately transmitted to memory system 110. The host interface 132 may store commands and data received from the host 102 sequentially to the command queue 56. Thereafter, the host interface 132 may estimate or predict what type of internal operation the controller 130 will perform based on the characteristics of the commands and data received from the host 102. The host interface 132 may determine the order and priority of processing of commands and data based at least on their characteristics. Depending on the characteristics of the commands and data received from the host 102, the buffer manager 52 in the host interface 132 is configured to determine whether the buffer manager 52 should store the commands and data in the memory 144 or whether the buffer manager 52 should pass the commands and data to the Flash Translation Layer (FTL) circuitry 40. The event queue 54 receives events input from the buffer manager 52, which are to be executed and processed internally by the memory system 110 or the controller 130 in response to commands and data from the host 102, to pass the events into the Flash Translation Layer (FTL) circuitry 40 in the order received.

According to an embodiment, the host interface 132 in fig. 3 may perform the functions of the controller 130 in fig. 2.

According to an embodiment, the Flash Translation Layer (FTL) circuitry 40 may include a state manager (GC/WL)42, a Mapping Manager (MM)44, a Host Request Manager (HRM)46, and a block manager (BM/BM) 48. The host request manager 46 may manage incoming events from the event queue 54. The mapping manager 44 may process or control the mapping data. The state manager 42 may perform Garbage Collection (GC) or Wear Leveling (WL). Block manager 48 may execute commands or instructions on blocks in memory device 150.

By way of example and not limitation, host request manager 46 may use mapping manager 44 and block manager 48 to process or process requests based on read and program commands and events passed from host interface 132. The host request manager 46 may send a query request to the mapping data manager 44 to determine the physical address corresponding to the logical address entered with the event. The host request manager 46 may send a read request with a physical address to the memory interface 142 to process the read request (process event). In another aspect, host request manager 46 may send a program request (or write request) to block manager 48 to program incoming data to a blank page (i.e., a page without data) in memory device 150, and may then transmit a mapping update request corresponding to the program request to mapping manager 44 to update an entry related to the programmed data in information mapping logical-physical addresses to each other.

Here, block manager 48 may convert programming requests passed from host request manager 46, mapping data manager 44, and/or status manager 42 into flash programming requests for memory device 150 to manage flash blocks in memory device 150. To maximize or enhance the programming or writing performance of memory system 110 (see FIG. 2), block manager 48 may collect programming requests and send flash programming requests for multi-plane and one-shot programming operations to memory interface 142. The block manager 48 may send several flash programming requests to the memory interface 142 to enhance or maximize the parallel processing of multi-channel and multi-directional flash controllers.

The block manager 48 may be configured to manage the blocks in the memory device 150 according to the number of valid pages, select and erase blocks without valid pages when free blocks are needed, and select blocks including the least number of valid pages when garbage collection is determined to be necessary. The state manager 42 may perform garbage collection to move valid data to a blank block and erase the remaining data in the block from which valid data was moved so that the block manager 48 may have enough free blocks (i.e., blank blocks with no data). If block manager 48 provides information about the block to be erased to status manager 42, status manager 42 can check all flash pages of the block to be erased to determine if each page is valid. For example, to determine the validity of each page, state manager 42 may identify a logical address stored in an out-of-band (OOB) area of each page. To determine whether each page is valid, state manager 42 may compare the physical address of the page to the physical address mapped to the logical address obtained from the request. The state manager 42 sends a program request to the block manager 48 for each valid page. When the programming operation is complete, the mapping table may be updated by an update of mapping manager 44.

Mapping manager 44 may manage a logical-to-physical mapping table. The mapping manager 44 may process requests, such as queries and updates, generated by the host request manager 46 or the state manager 42. Mapping manager 44 may store the entire mapping table in memory device 150 (e.g., flash/non-volatile memory) and cache mapping entries according to the storage capacity of memory 144. When a mapping cache miss occurs while processing a query or update request, mapping manager 44 may send a read request to memory interface 142 to load the associated mapping table stored in memory device 150. When the number of dirty cache blocks in mapping manager 44 exceeds a certain threshold, a programming request may be sent to block manager 48, forming a clean cache block, and a dirty mapping table may be stored in memory device 150.

When performing garbage collection, the state manager 42 copies the valid pages into free blocks, and the host request manager 46 can program the latest version of the data for the same logical address of the page and issue an update request at the current time. When the state manager 42 requests a mapping update in a state in which the copying of the valid page has not been completed, the mapping manager 44 may not perform the mapping table update. This is because if the state manager 42 requests a mapping update and does not complete a valid page copy until later, a mapping request is issued along with the old physical information. Mapping manager 44 may perform a mapping update operation to ensure accuracy only if the latest mapping table still points to the old physical address.

Memory device 150 may include a plurality of memory blocks. Each of the plurality of memory blocks may be a Single Level Cell (SLC) memory block or a multi-level cell (MLC) memory block depending on the number of bits that may be stored or represented in one memory cell of such a block. Here, an SLC memory block includes multiple pages implemented by memory cells, each memory cell storing one bit of data. SLC memory blocks may have high data I/O operating performance and high endurance performance. An MLC memory block includes multiple pages implemented by memory cells, each memory cell storing multiple bits of data (e.g., two or more bits). MLC memory blocks may have a larger storage capacity in the same space than SLC memory blocks. MLC memory blocks can be highly integrated in terms of storage capacity. In an embodiment, the memory device 150 may be implemented with MLC memory blocks such as double-layer cell memory blocks, triple-layer cell (TLC) memory blocks, quad-layer cell (QLC) memory blocks, and combinations thereof. A dual level cell memory block may include multiple pages implemented by memory cells each capable of storing 2 bits of data. A triple-level cell (TLC) memory block may include multiple pages implemented by memory cells that are each capable of storing 3-bit data. A four-layer cell (QLC) memory block may include multiple pages implemented by memory cells each capable of storing 4 bits of data. In another embodiment, memory device 150 may be implemented with a block comprising multiple pages implemented by memory cells, each memory cell capable of storing 5 or more bits of data.

In an embodiment of the present disclosure, memory device 150 is implemented as a non-volatile memory such as a flash memory, such as a NAND flash memory, a NOR flash memory, or the like. In another embodiment, the memory device 150 may be implemented by at least one of a Phase Change Random Access Memory (PCRAM), a Ferroelectric Random Access Memory (FRAM), and a spin injection magnetic memory, such as a spin transfer torque magnetic random access memory (STT-MRAM).

Fig. 4 is a table showing a first example of an operation method of the memory system 110 according to an embodiment of the present invention.

Referring to fig. 4, various CASEs CASE <1:5> for analyzing a value pattern thereof when pieces of execution information OPINFO <1: N > are accumulated during a predetermined duration of a plurality of cycles will be described. At this time, CASE <1:5>, the value of the execution information OPINFO < N +1> to be accumulated in the subsequent cycle may be determined differently.

In fig. 4, a total of 11 pieces of execution information OPINFO <1:11> are accumulated during a predetermined duration of 11 cycles. In addition, the execution information analysis block 1302 analyzes ten pieces of execution information OPINFO <2:11> among the 11 pieces of execution information OPINFO <1:11>, and then predicts the value of the 12 th piece of execution information OPINFO <12> to be accumulated in the 12 th cycle.

In the first CASE <1>, ten pieces of execution information OPINFO <2:11> are targeted for analysis by the execution information analysis block 1302, and as can be seen from the result of analyzing the value patterns thereof, the ten pieces of execution information OPINFO <2:11> have a value pattern indicating that an internal operation is executable in two cycles and then an internal operation is not executable in two cycles. In other words, since the second execution information OPINFO <2> has a value indicating that the internal operation is not executable, and the third and fourth execution information OPINFO <3> and OPINFO <4> have values indicating that the internal operation is executable, the fifth and sixth execution information OPINFO <5> and OPINFO <6> have values indicating that the internal operation is not executable, the seventh and eighth execution information OPINFO <7> and OPINFO <8> have values indicating that the internal operation is executable, and the ninth and tenth execution information OPINFO <9> and OPINFO <10> have values indicating that the internal operation is not executable, it can be seen that the plurality of pieces of execution information OPINFO <3:10> have a value pattern indicating that the internal operation is executable in two cycles and then the internal operation is not executable in two cycles. At this time, since the 11 th execution information OPINFO <11> has a value indicating that the internal operation can be executed, it can be predicted that the 12 th execution information OPINFO <12> has a value indicating that the internal operation can be executed.

In the second CASE <2>, ten pieces of execution information OPINFO <2:11> are targeted for analysis by the execution information analysis block 1302, and as can be seen from the result of analyzing the value patterns thereof, the ten pieces of execution information OPINFO <2:11> have a value pattern indicating that an internal operation is executable in three cycles and then an internal operation is not executable in three cycles. In other words, since the second execution information OPINFO <2>, the third execution information OPINFO <3> and the fourth execution information OPINFO <4> have values indicating that the internal operation is executable, the fifth execution information OPINFO <5>, the sixth execution information OPINFO <6> and the seventh execution information OPINFO <7> have values indicating that the internal operation is not executable, and the eighth execution information OPINFO <8>, the ninth execution information OPINFO <9> and the tenth execution information OPINFO <10> have values indicating that the internal operation is executable, it can be seen that the plurality of pieces of execution information OPINFO <2:10> have a value pattern indicating that the internal operation is executable in three cycles and then indicates that the internal operation is not executable in three cycles. At this time, since the 11 th execution information OPINFO <11> has a value indicating that the internal operation is not executable, it can be predicted that the 12 th execution information OPINFO <12> has a value indicating that the internal operation is not executable.

In the third CASE <3>, ten pieces of execution information OPINFO <2:11> are targeted for analysis by the execution information analysis block 1302, and as can be seen from the result of analyzing the value patterns thereof, the ten pieces of execution information OPINFO <2:11> have a value pattern indicating that an internal operation is executable in several cycles and then the internal operation is not executable in the remaining cycles. In other words, since the second execution information OPINFO <2>, the third execution information OPINFO <3>, the fourth execution information OPINFO <4>, the fifth execution information OPINFO <5>, the sixth execution information OPINFO <6>, the seventh execution information OPINFO <7> and the eighth execution information OPINFO <8> have values indicating that the internal operation is executable, and the ninth execution information OPINFO <9>, the tenth execution information OPINFO <10> and the 11 th execution information OPINFO <11> have values indicating that the internal operation is not executable, it can be seen that ten pieces of execution information OPINFO <2:11> have a value pattern indicating that the internal operation is executable in several previous cycles and then indicates that the internal operation is not executable in the remaining cycles. At this time, since the ninth execution information OPINFO <9>, the tenth execution information OPINFO <10>, and the 11 th execution information OPINFO <11> have values indicating that the internal operation is not executable, it is possible to predict that the 12 th execution information OPINFO <12> has a value indicating that the internal operation is not executable.

In the fourth CASE <4>, ten pieces of execution information OPINFO <2:11> are targeted for analysis by the execution information analysis block 1302, and as can be seen from the result of analyzing the value patterns thereof, the ten pieces of execution information OPINFO <2:11> have a value pattern indicating that an internal operation is not executable in several cycles and then an internal operation is executable in the remaining cycles. In other words, since the second execution information OPINFO <2>, the third execution information OPINFO <3>, the fourth execution information OPINFO <4> and the fifth execution information OPINFO <5> have values indicating that the internal operation is not executable, and the sixth execution information OPINFO <6>, the seventh execution information OPINFO <7>, the eighth execution information OPINFO <6>, the ninth execution information OPINFO <9>, the tenth execution information OPINFO <10> and the 11 th execution information OPINFO <11> have values indicating that the internal operation is executable, it can be seen that ten pieces of execution information OPINFO <2:11> have value patterns indicating that the internal operation is not executable in several previous cycles and then the internal operation is executable in the remaining cycles. At this time, since the sixth execution information OPINFO <6>, the seventh execution information OPINFO <7>, the eighth execution information OPINFO <8>, the ninth execution information OPINFO <9>, the tenth execution information OPINFO <10>, and the 11 th execution information OPINFO <11> have values indicating that the internal operation is executable, it is possible to predict that the 12 th execution information OPINFO <12> has a value indicating that the internal operation is executable.

In the fifth CASE <5>, ten pieces of execution information OPINFO <2:11> are targeted for analysis by the execution information analysis block 1302, and as can be seen from the result of analyzing the value patterns thereof, the value patterns of the ten pieces of execution information OPINFO <2:11> do not have a specific tendency. In other words, since the second execution information OPINFO <2> has a value indicating that the internal operation is not executable, the third execution information OPINFO <3> has a value indicating that the internal operation is executable, the fourth execution information OPINFO <4> has a value indicating that the internal operation is not executable, the fifth execution information OPINFO <5> has a value indicating that the internal operation is executable, the sixth execution information OPINFO <6> and the seventh execution information OPINFO <7> have values indicating that the internal operation is not executable, the eighth execution information OPINFO <8>, the ninth execution information OPINFO <9> and the tenth execution information OPINFO <10> have values indicating that the internal operation is executable, and the 11 th execution information OPINFO <11> has a value indicating that the internal operation is not executable, it can be seen that the value pattern of the ten pieces of execution information OPINFO <2:11> does not have a specific tendency. In this case, the 12 th execution information OPINFO <12> may be estimated to have a value indicating that the internal operation is not executable, so that the internal operation cannot be executed at every cycle.

For reference, unlike the above-described embodiment shown in fig. 4, the execution information analysis block 1302 may analyze all 11 pieces of execution information OPINFO <1:11> accumulated during a predetermined duration of 11 cycles and predict the value of the 12 th execution information OPINFO <12> to be accumulated at the 12 th cycle.

The effect on the device according to the present disclosure is described below.

The memory system and the data processing system according to the embodiments of the present disclosure may predict whether an internal operation of the memory system is executable without a command from the host for a predetermined time after a set time point based on system information input from the host for each cycle repeated for each predetermined time, and then may execute the internal operation for a predetermined time from the set time point according to a result of the prediction. Accordingly, by predicting a point in time that does not affect the input/output performance between the host and the memory system, the internal operation of the memory system can be stably performed.

While the present disclosure has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims.