阅读说明：本技术 太阳能电池结构及其制作方法 (Solar cell structure and manufacturing method thereof ) 是由 田伟辰 洪政源 叶昌鑫 吴以德 于 2019-09-02 设计创作，主要内容包括：本发明公开了一种太阳能电池结构及其制作方法,太阳能电池结构包含半导体基板、钝化层、穿隧层和掺杂结晶硅层。半导体基板具有相对的第一侧和第二侧。钝化层位于半导体基板的第一侧。穿隧层位于半导体基板的第二侧。掺杂结晶硅层位于穿隧层的远离该半导体基板的侧边,其包含多晶硅晶体,且其结晶度约为50％～90％。本发明的太阳能电池结构具有较高的暗喻开路电压和载子生命周期,使得整体效能因而提升。(The invention discloses a solar cell structure and a manufacturing method thereof. The semiconductor substrate has opposing first and second sides. The passivation layer is located on the first side of the semiconductor substrate. The tunneling layer is located on the second side of the semiconductor substrate. The doped crystalline silicon layer is located on the side of the tunneling layer far away from the semiconductor substrate, comprises polysilicon crystals and has crystallinity of about 50% to 90%. The solar cell structure of the invention has higher metaphorical open-circuit voltage and carrier life cycle, so that the overall efficiency is improved.)

1. A solar cell structure, comprising:

a semiconductor substrate having opposing first and second sides;

a passivation layer on a first side of the semiconductor substrate;

a tunneling layer located on a second side of the semiconductor substrate; and

and the doped crystalline silicon layer is positioned on one side edge of the tunneling layer far away from the semiconductor substrate, comprises polycrystalline silicon crystals and has the crystallinity of 50-90%.

2. The solar cell structure of claim 1, wherein the doped crystalline silicon layer comprises a first doped crystalline silicon layer and a second doped crystalline silicon layer stacked on each other, the first doped crystalline silicon layer is located between the tunneling layer and the second doped crystalline silicon layer, and the doping concentration of the second doped crystalline silicon layer is greater than that of the first doped crystalline silicon layer.

3. The solar cell structure of claim 2, wherein the first doped crystalline silicon layer has a doping concentration of 10¹³Per cubic centimeter to 10¹⁷Per cubic centimeter, and the doping concentration of the second doped crystalline silicon layer is 10¹⁷Per cubic centimeter to 10²¹One per cubic centimeter.

4. The solar cell structure of claim 2, wherein the first and second sub-doped crystalline silicon layers each have a thickness of 10 to 50 nanometers.

5. The solar cell structure of claim 1, wherein the passivation layer is made of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, or a combination thereof.

6. The solar cell structure of claim 1, wherein the tunneling layer has a thickness of 0.1 to 3 nanometers.

7. The solar cell structure of claim 1, wherein the doped crystalline silicon layer has a thickness of 20 nm to 100 nm.

8. A method of fabricating a solar cell structure, comprising:

providing a semiconductor substrate;

forming a tunneling layer on the first side of the semiconductor substrate by high-temperature oxidation or chemical vapor deposition;

forming a doped crystalline silicon layer on the side of the tunneling layer far away from the semiconductor substrate through a first deposition process, wherein the doped crystalline silicon layer comprises polycrystalline silicon crystals, and the crystallinity of the doped crystalline silicon layer is 50% -90%; and

a passivation layer is formed on a second side of the semiconductor substrate opposite the first side by a second deposition process.

9. The method of claim 8, wherein forming the doped crystalline silicon layer on a side of the tunneling layer remote from the semiconductor substrate comprises:

forming a first-time doped crystalline silicon layer on one side of the tunneling layer far away from the semiconductor substrate, wherein the doping concentration of the first-time doped crystalline silicon layer is 10¹³Per cubic centimeter to 10¹⁷Per cubic centimeter; and

forming a second-time doped crystalline silicon layer on the side of the first-time doped crystalline silicon layer far away from the tunneling layer, wherein the doping concentration of the second-time doped crystalline silicon layer is 10¹⁷Per cubic centimeter to 10²¹One per cubic centimeter.

10. The method of claim 8, wherein the first deposition process comprises forming a first doped crystalline silicon layer and a second doped crystalline silicon layer, wherein the process gas of the second doped crystalline silicon layer is enriched with a dopant reactant gas relative to the process gas of the first doped crystalline silicon layer.

Technical Field

The present invention relates to a solar cell structure and a method for fabricating the same, and more particularly, to a solar cell structure having a polycrystalline silicon crystal and a method for fabricating the same.

Background

Passivation structures and processes are important structures and processes that are essential in the semiconductor industry. Taking the solar cell industry as an example, conventional Back Surface Field (BSF) solar cells, such as a Passivated emitter and back electrode Passivated (PERC) solar cell, a heterojunction with intrinsic thin layer (HIT) solar cell, or a tunnel oxide Passivated (top) solar cell, have passivation layers. For example, the doped crystalline silicon layer used in the high efficiency silicon-based solar cell structure is fabricated by a high temperature process, which affects the quality of the tunneling layer and reduces the product performance and yield.

Disclosure of Invention

An objective of the present invention is to provide a solar cell structure, which has a higher metaphorical open-circuit voltage (i.e., open-circuit voltage) and carrier lifetime than the conventional solar cell structure, so as to improve the overall performance. Another objective of the present invention is to provide a method for fabricating the solar cell structure.

In accordance with the above objects, the present invention provides a solar cell structure comprising a semiconductor substrate, a passivation layer, a tunneling layer and a doped crystalline silicon layer. The semiconductor substrate has opposing first and second sides. The passivation layer is located on the first side of the semiconductor substrate. The tunneling layer is located on the second side of the semiconductor substrate. The doped crystalline silicon layer is positioned on the side of the tunneling layer far away from the semiconductor substrate, comprises polycrystalline silicon crystals and has the crystallinity of 50-90%.

According to an embodiment of the present invention, the doped crystalline silicon layer includes a first doped crystalline silicon layer and a second doped crystalline silicon layer stacked on each other, the first doped crystalline silicon layer is located between the tunneling layer and the second doped crystalline silicon layer, and a doping concentration of the second doped crystalline silicon layer is greater than a doping concentration of the first doped crystalline silicon layer.

According to the inventionIn one embodiment, the first time doped crystalline silicon layer has a doping concentration of about 10¹³Per cubic centimeter to 10¹⁷Cubic centimeter, and the doping concentration of the second doped crystalline silicon layer is about 10¹⁷Per cubic centimeter to 10²¹One per cubic centimeter.

According to another embodiment of the present invention, each of the first doped crystalline silicon layer and the second doped crystalline silicon layer has a thickness of about 10 nanometers (nm) to about 50 nm.

According to another embodiment of the present invention, the passivation layer is made of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, or a combination thereof.

According to another embodiment of the present invention, the thickness of the tunneling layer is about 0.1 nm to about 3 nm.

According to another embodiment of the present invention, the thickness of the doped crystalline silicon layer is about 20 nm to about 100 nm.

In accordance with the above objects, the present invention further provides a method for fabricating a solar cell structure, comprising: providing a semiconductor substrate; forming a tunneling layer on the first side of the semiconductor substrate by high-temperature oxidation or chemical vapor deposition; forming a doped crystalline silicon layer on one side of the tunneling layer far away from the semiconductor substrate by a first deposition process, wherein the doped crystalline silicon layer contains polycrystalline silicon crystals, and the crystallinity of the doped crystalline silicon layer is 50% -90%; and forming a passivation layer on a second side of the semiconductor substrate opposite to the first side by a second deposition process.

According to another embodiment of the present invention, the forming the doped crystalline silicon layer on the side of the tunneling layer away from the semiconductor substrate includes: forming a first-time doped crystalline silicon layer with a doping concentration of about 10 on the tunneling layer side away from the semiconductor substrate¹³Per cubic centimeter to 10¹⁷Per cubic centimeter; and forming a second doped crystalline silicon layer with a doping concentration of about 10 on the first doped crystalline silicon layer at a side thereof remote from the tunneling layer¹⁷Per cubic centimeter to 10²¹One per cubic centimeter.

According to another embodiment of the present invention, the first deposition process includes forming a first doped crystalline silicon layer and a second doped crystalline silicon layer, wherein the process gas for the second doped crystalline silicon layer is increased by a dopant reactive gas relative to the process gas for the first doped crystalline silicon layer.

The invention has the advantages that the quality of the tunneling layer can be prevented from being influenced in a high-temperature process by controlling the doping concentration in the doped crystalline silicon layer, and the efficiency and the qualification rate of products are further ensured.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 is a cross-sectional view of a solar cell structure according to an embodiment of the present invention;

FIG. 2 is a partial cross-sectional view of the solar cell structure of FIG. 1; and

fig. 3 is a flowchart of a method for fabricating a solar cell structure according to an embodiment of the invention.

Description of the main reference numerals:

100-solar cell structure, 102-semiconductor substrate, 102A-first side, 102B-second side, 104-tunneling layer, 106-doped crystalline silicon layer, 106A-first time doped crystalline silicon layer, 106B-second time doped crystalline silicon layer, 108, 110-passivation layer, 112-anti-reflection layer, 114, 116-electrode layer, 300-method, 302, 304, 306, 308-step, T106A, T106B-thickness.

Detailed Description

Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the invention.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, components, regions and/or sections, these elements, components, regions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the spatially relative terms are used to describe various orientations of the elements in use or operation and are not intended to be limited to the orientations shown in the figures. Elements may also be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in a similar manner.

Referring to fig. 1, fig. 1 is a cross-sectional view of a solar cell structure 100 according to an embodiment of the invention. As shown in fig. 1, the solar cell structure 100 is a tunnel oxide passivated contact (topocon) solar cell structure and includes a semiconductor substrate 102, a tunneling layer 104, a doped crystalline silicon layer 106, passivation layers 108, 110, an anti-reflection layer 112, and electrode layers 114, 116.

The semiconductor substrate 102 may be an N-type doped crystalline silicon substrate or a P-type doped crystalline silicon substrate depending on the application of the solar cell structure 100. The tunneling layer 104 is formed by performing a surface treatment on the first side 102A of the semiconductor substrate 102 by using an rf plasma device to form the tunneling layer 104 on the first side 102A of the semiconductor substrate 102. The tunneling layer 104 may be a silicon oxide film having a thickness of about 0.1 nanometer (nm) to about 3 nm and a defect density of substantially less than 10¹¹Per square centimeter. The doped crystalline silicon layer 106 is located on a side of the tunneling layer 104 away from the semiconductor substrate 102. The doped crystalline silicon layer 106 may comprise monocrystalline silicon crystals and/or polycrystalline silicon crystals having a thickness T₁₀₆May be about 20 nm to about 100 nm, and may have a crystallinity of about 50% to about 90% to reduce the interface resistance with the electrode layer 114 and avoid damage to the tunneling layer 104. In addition, the doped crystalline silicon layer 106 may be an N-type doped crystalline silicon layer or a P-type doped crystalline silicon layer corresponding to the type of the semiconductor substrate 102. For example, if the semiconductor substrate 102 is an N-type doped crystalline silicon substrate, the doped crystalline silicon layer 106 may be an N + -type doped crystalline silicon layer.

The passivation layers 108, 110 and the anti-reflective layer 112 are sequentially stacked on the second side 102B of the semiconductor substrate 102. The material of each passivation layer 108, 110 may be aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, combinations thereof, or other suitable materials. For example, the passivation layers 108, 110 may be an aluminum oxide layer and a silicon oxide layer, respectively. The material of the anti-reflective layer 112 may be silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, combinations thereof, or other suitable materials.

The electrode layers 114 and 116 are respectively located on a side of the doped crystalline silicon layer 106 away from the tunneling layer 104 and the second side 102A of the semiconductor substrate 102, wherein the electrode layer 116 extends upward and penetrates the passivation layers 108 and 110 and the anti-reflection layer 112. The material of the electrode layers 114, 116 may be silver, copper, aluminum, combinations thereof, or other suitable metals or conductive materials. In some embodiments, the electrode layer 114 is a transparent conductive oxide layer, which may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or other suitable transparent conductive material.

Fig. 2 is a partial cross-sectional view of the solar cell structure 100 of fig. 1. As shown in fig. 2, the doped crystalline silicon layer 106 includes a first sub-doped crystalline silicon layer 106A and a second sub-doped crystalline silicon layer 106B stacked one on another, wherein the first sub-doped crystalline silicon layer 106A is located on a side of the tunnel layer 104 away from the semiconductor substrate 102, and the second sub-doped crystalline silicon layer 106B is located on a side of the first sub-doped crystalline silicon layer 106A away from the tunnel layer 104. For example, the semiconductor substrate 102 is implemented as an N-doped crystalline silicon substrate, the first and second sub-doped crystalline silicon layers 106A and 106B may be formed of polysilicon and have N-type dopants, such as phosphorus, arsenic, antimony, and/or other similar dopants. The second doped crystalline silicon layer 106B has a doping concentration greater than the doping concentration of the first doped crystalline silicon layer 106A. Since the first-time doped crystalline silicon layer 106A is adjacent to the tunneling layer 104, the first-time doped crystalline silicon layer 106A with a lower doping concentration can prevent the dopants from diffusing into the tunneling layer 104, thereby improving the reliability of the tunneling layer 104. In addition, the second doped crystalline silicon layer 106B is adjacent to the electrode layer 114, so that the second doped crystalline silicon layer 106B with higher doping concentration can be added to the electrode layer 114 (ohmic contact). In some embodiments, the first doped crystalline silicon layer 106A has a doping concentration of about 10¹³Per cubic centimeter to 10¹⁷One per cubic centimeter. And the second doped crystalline silicon layer 106B has a doping concentration of about 10¹⁷Per cubic centimeter to 10²¹One per cubic centimeter. In addition, in some embodiments, the thickness T of the first and second doped crystalline silicon layers 106A and 106B_106A、T_106BEach of about 10 nm to about 50 nm. Thickness T_106AAnd thickness T_106BMay be the same or different. The definition of the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B can be determined by the doping concentration. In one embodiment, the doped crystalline silicon layer 106 is plotted against the doping concentration, wherein the doped crystalline silicon layer 106 is adjacent to the tunneling layer 104 on the left and the electrode layer 114 on the right on the x-axis, and the doping concentration is plotted on the y-axis. The interface between the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B is located at the position corresponding to the middle doping concentration in the interval with the largest doping concentration variation.

In some embodiments, the doped crystalline silicon layer 106 may have three or more sub-doped crystalline silicon layers, and the doping concentration relationship of the sub-doped crystalline silicon layers may be stepped to decrease in a direction away from the tunneling layer 104. The thicknesses of these sub-doped crystalline silicon layers may be the same as or different from each other. In other embodiments, the doped crystalline silicon layer 106 may have a continuous doping concentration variation, and the doping concentration may decrease gradually in a direction away from the tunneling layer 104; the doping concentration near the junction with the tunneling layer 104 is about 10¹³Per cubic centimeter to 10¹⁷Cubic centimeter and a doping concentration of about 10 near the junction with the conductive layer 114¹⁷Per cubic centimeter to 10²¹One per cubic centimeter.

Compared with the conventional solar cell structure, the implied open-circuit voltage (i.e., voltage) of the solar cell structure of the present invention can reach 700 millivolts (mV) or more, and the carrier lifetime (i.e., lifetime) can be increased to 1600 microseconds or more, so the overall performance can be increased by at least 5%. In addition, the solar cell structure can also improve the photoelectric conversion efficiency of the tunneling oxide passivation contact type solar cell structure to more than 24%.

Fig. 3 is a flow chart of a method 300 of fabricating a solar cell structure according to an embodiment of the invention. For convenience, the following description of the steps of the method 300 is provided to form the solar cell structure 100 of fig. 1 and 2, but the invention is not limited thereto, and can be applied to form other solar cell structures or similar semiconductor structures.

In the method 300, a semiconductor substrate 102 is provided, beginning with step 302. The semiconductor substrate 102 may be a P-type doped crystalline silicon substrate or an N-type doped crystalline silicon substrate according to various design requirements.

Next, in step 304, a tunneling layer 104 is formed on the first side 102A of the semiconductor substrate 102. The tunneling layer 104 may be formed by high temperature oxidation or chemical vapor deposition. In one embodiment, the tunneling layer 104 is formed by chemical vapor deposition using a radio frequency plasma apparatus. If the semiconductor substrate 102 is provided as a silicon substrate and the process gas introduced by the rf plasma apparatus is oxygen, ozone or other gas composed of oxygen atoms, the oxygen ions in the plasma state combine with the silicon atoms of the broken bonds on the surface of the semiconductor substrate 102 to form silicon oxide, thereby forming a silicon oxide film (i.e., the tunneling layer 104). The silicon oxide film formed by the RF plasma equipment may have a thickness of about 0.1 nm to about 3 nm and a defect density of substantially less than 10¹¹Per square centimeter.

Then, in step 306, a doped crystalline silicon layer 106 is formed on the side of the tunneling layer 104 away from the semiconductor substrate 102. The doped crystalline silicon layer 106 may be formed on the tunneling layer 104 by performing a Chemical Vapor Deposition (CVD) process, such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and may have a thickness of about 20 nm to about 100 nm. In a chemical vapor deposition process for forming the doped crystalline silicon layer 106, the process pressure may be about 400 torr (torr) and the rf power may be about 30 milliwatts per square centimeter (mW/cm)²) And a semiconductor substrate 102 may be approximately 300 degrees celsius. The doped crystalline silicon layer 106 may comprise a single crystal silicon crystal or a polycrystalline silicon crystal. After the chemical vapor deposition process is completed, an annealing process may be performed to form polysilicon crystals in the doped crystalline silicon layer 106, such that the crystallinity of the doped crystalline silicon layer 106 is about 50% to 90%. In addition, the doped crystalline silicon layer 106 may be an N-type doped crystalline silicon layer or a P-type doped crystalline silicon layer corresponding to the type of the semiconductor substrate 102. For example, if the semiconductor substrate 102 is an N-type doped crystalline silicon substrate, the doped crystalline silicon layer 106 may be an N + -type doped crystalline silicon layer.

Further, the formed doped crystalline silicon layer 106 includes a first sub-doped crystalline silicon layer 106A and a second sub-doped crystalline silicon layer 106B stacked one on another, wherein the first sub-doped crystalline silicon layer 106A is located on a side of the tunnel layer 104 away from the semiconductor substrate 102, and the second sub-doped crystalline silicon layer 106B is located on a side of the first sub-doped crystalline silicon layer 106A away from the tunnel layer 104. For example, the semiconductor substrate 102 is implemented as an N-doped crystalline silicon substrate, the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B may both have polysilicon crystals and both have N-type dopants, such as phosphorus, arsenic, antimony and/or other similar dopants. The process gases for the chemical vapor deposition process may be silane and hydrogen during the formation of the first doped crystalline silicon layer 106A, while the process gases for the chemical vapor deposition process may be reactive gases that add dopants in addition to silane and hydrogen during the formation of the second doped crystalline silicon layer 106B, such as: and (3) phosphine. So that the doping concentration of the first doped crystalline silicon layer 106A is greater than the doping concentration of the second doped crystalline silicon layer 106B. In some embodiments, the first doped crystalline silicon layer 106A has a doping concentration of about 10¹⁷Per cubic centimeter to 10²¹Cubic centimeter and the second doped crystalline silicon layer 106B has a doping concentration of about 10¹³Per cubic centimeter to 10¹⁷One per cubic centimeter. By controlling the time of the cvd process, the thickness of each of the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B may be about 10 nm to about 50 nm.

In some embodiments, the doped crystalline silicon layer 106 may be formed with three or more sub-doped crystalline silicon layers, and the doping concentration relationship of the sub-doped crystalline silicon layers may be decreased in a direction gradually away from the tunneling layer 104 by adjusting the process gas of the cvd process performed to form the sub-doped crystalline silicon layers. In other embodiments, the doped crystalline silicon layer 106 may be formed by appropriately controlling the cvd process to have a continuous doping concentration variation, and the doping concentration may gradually decrease in a direction away from the tunneling layer 104.

After the doped crystalline silicon layer 106 is formed, a passivation layer 108 is formed on the second side 102B of the semiconductor substrate 102 (i.e., the side of the semiconductor substrate 102 away from the tunneling layer 104) in step 308. The passivation layer 108 may be formed on the semiconductor substrate 102 by performing a chemical vapor deposition (cvd) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD) process. The material of the passivation layer 108 may be aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, combinations thereof, or other suitable materials.

After step 308, the corresponding steps may be performed according to the type of semiconductor structure. Taking the solar cell structure 100 as an example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be performed to form a passivation layer 110 on the passivation layer 108. Likewise, the passivation layer 110 may be formed of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, combinations thereof, or other suitable materials. Thereafter, a deposition process or a coating process is performed to form an anti-reflection layer 112 on the passivation layer 110. The anti-reflective layer 112 may be formed of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, combinations thereof, or other suitable materials. Then, evaporation, sputtering or electroplating processes are performed to form electrode layers 114, 116 on the doped crystalline silicon layer 106 and the second side 102B of the semiconductor substrate 102, respectively. Before forming the electrode layer 116, an etching process may be performed to form a gap on the passivation layers 108, 110 and the anti-reflection layer 112, and then the electrode layer 116 is formed in the gap. The electrode layers 114, 116 may be formed of silver, copper, aluminum, combinations thereof, or other metals or conductive materials. In other embodiments, the electrode layers 114, 116 may be formed by screen printing.

In some embodiments, if the electrode layer 114 is formed of a metal material, the doped crystalline silicon layer 106 and the metal layer 114 may be formed simultaneously by sequentially forming a doped silicon film and a metal material film on the side of the tunneling layer 104 away from the semiconductor substrate and then performing an annealing process.

The method for manufacturing the solar cell structure has the advantages that the quality of the tunneling layer can be prevented from being influenced in a high-temperature process by controlling the doping concentration in the doped crystalline silicon layer, and the efficiency and the qualified rate of products are further ensured.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.