阅读说明：本技术 一种用于低电压下的50%占空比整形电路 (50% duty cycle shaping circuit used under low voltage ) 是由 王子轩 邵陆钦 蔡志匡 刘璐 谢祖帅 郭静静 于 2021-02-01 设计创作，主要内容包括：本发明涉及一种用于低电压下的50%占空比整形电路,利用脉宽调节电路和占空比检测电路,将正弦信号转化为占空比稳定为50%的方波。占空比检测电路和脉宽调节电路形成的负反馈环路将输出占空比锁定为50％。在保证信号正常转化的前提下,增强了电路的噪声性能,降低了电路的静态功耗。(The invention relates to a 50% duty cycle shaping circuit used under low voltage, which converts a sinusoidal signal into a square wave with the duty cycle stabilized to 50% by utilizing a pulse width regulating circuit and a duty cycle detecting circuit. The output duty cycle is locked to 50% by a negative feedback loop formed by the duty cycle detection circuit and the pulse width adjusting circuit. On the premise of ensuring normal conversion of signals, the noise performance of the circuit is enhanced, and the static power consumption of the circuit is reduced.)

1. The 50% duty cycle shaping circuit used under low voltage is characterized by comprising a pulse width regulating circuit and a duty cycle detection circuit, wherein the input end of the pulse width regulating circuit is connected with a voltage signal V_in(ii) a The output Vs square wave of the pulse width regulating circuit is used as one input end of a duty ratio detection circuit, the other input end of the duty ratio detection circuit is connected with a current source Iref, and the output V of the duty ratio detection circuit is fed back to the pulse width regulating circuit;

the pulse width regulating circuit comprises a first capacitor C₁A second capacitor C_2、A first resistor R₁A second resistor R₂A first PMOS transistor M_p1A first NMOS transistor M_N1And a first inverter inv₁，

Wherein the voltage signal V_inAre respectively connected with a first capacitor C₁And a second capacitor C₂The upper stage plate of (1), the first capacitor C₁Respectively with the first resistor R₁Left end of the first PMOS transistor M_p1The grid electrodes are connected; second capacitor C₂Respectively with a second resistor R₂Left end of (1), first NMOS transistor M_N1Is connected with the grid electrode of the first resistor R₁The right end is connected with a power supply Vdd; a second resistor R₂The right end is grounded; first PMOS transistor M_p1The source of (2) is connected with a power supply Vdd; first PMOS transistor M_p1And the first inverter inv₁Are connected with the input end of the power supply; first NMOS transistor M_N1The source of (2) is grounded; first NMOS transistor M_N1Is connected to the input of the first inverter inv; first inverter inv₁As the output signal Vs of the pulse width adjusting circuit.

2. The 50% duty cycle shaping circuit for use at low voltages of claim 1 wherein the duty cycle detection circuit comprises a second PMOS transistor M_P2A second NMOS transistor M_N2A third capacitor C₃，

Wherein the second PMOS transistor M_P2And the first inverter inv₁The output ends of the two are connected; second PMOS transistor M_P2Is connected with a current source Iref; the current source Iref is connected with a power supply Vdd; second PMOS transistor M_P2Drain and third capacitor C₃The upper-level plates are connected;

second NMOS transistor M_N2And the first inverter inv₁The output ends of the two are connected; second NMOS transistor M_N2Is connected with a current source Iref; current source Iref is grounded; second NMOS transistor M_N2Drain and third capacitor C₃The upper-level plates are connected;

first PMOS transistor M_p1And the first NMOS transistor M_N1Are respectively connected with third capacitors C₃Upper stage board of (2), third capacitor C₃The lower plate of (2) is grounded.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a 50% duty cycle shaping circuit used under low voltage.

Background

In recent years, the development and application of portable wireless communication equipment are promoted by the rapid popularization of communication modes such as Bluetooth, WI-FI and GPS, and a 32.768kHz crystal oscillator gradually enters the visual angle of people. The 32.768kHz crystal oscillator is widely used in integrated circuits, as a signal generation module of a real-time clock, provides a real-time clock signal for systems on chip such as measuring equipment and sensors, and is used as a timing reference which is always on in general electronic equipment. Therefore, the 32.768kHz crystal oscillator is a key module for time calibration. The shaping circuit is one of important modules for converting a sinusoidal signal into a square wave signal in a 32.768kHz crystal oscillator. In summary, it is of great significance to implement a shaping circuit with high frequency precision and low power consumption.

Reducing the power supply voltage is a direct and effective way to achieve low power consumption, and the adoption of a near-threshold power supply voltage to achieve a pulse width modulation circuit becomes a new research hotspot. The large reduction in supply voltage can significantly reduce the power consumption of the time shaping circuit, but also reduces the accuracy of the waveform frequency. Most of the documents at present adopt a buffer to convert a sinusoidal signal into a square wave, and although the buffer can complete the conversion of the waveform, the noise performance, the frequency precision and the total power consumption are not satisfactory, and a 50% duty cycle loop locking is necessary to achieve the high-precision square wave required by a 32.768kHz crystal oscillator. Therefore, a 50% duty cycle shaping circuit is adopted to realize high precision and low power consumption.

Another implementation is to shape with schmitt triggers. By using the positive feedback function in the state conversion process of the Schmitt trigger, the periodic signal with slowly changing edge can be converted into a rectangular pulse signal with steep edge. However, the schmitt trigger causes a delay in the output voltage variation and a backlash effect, and thus cannot achieve a high-precision effect.

Disclosure of Invention

The invention aims to solve the technical problem of providing a 50% duty ratio locking mode, which can improve the performance of high phase noise while generating stable square waves and meet the work of high-precision requirement under the condition of a near-threshold power supply voltage.

The invention adopts the following technical scheme for solving the technical problems: a50% duty cycle shaping circuit used under low voltage comprises a pulse width adjusting circuit and a duty cycle detection circuit, wherein the input end of the pulse width adjusting circuit is connected with a voltage signal V_in(ii) a Output Vs square wave of pulse width regulating circuit as dutyAnd one input end of the duty ratio detection circuit and the other input end of the duty ratio detection circuit are connected with the current source Iref, and the output V of the duty ratio detection circuit is fed back to the pulse width regulation circuit.

Further, the pulse width adjusting circuit comprises a first capacitor C₁A second capacitor C_2、A first resistor R₁A second resistor R₂A first PMOS transistor M_p1A first NMOS transistor M_N1And a first inverter inv₁，

Wherein the voltage signal V_inAre respectively connected with a first capacitor C₁And a second capacitor C₂The upper stage plate of (1), the first capacitor C₁Respectively with the first resistor R₁Left end of the first PMOS transistor M_p1The grid electrodes are connected; second capacitor C₂Respectively with a second resistor R₂Left end of (1), first NMOS transistor M_N1Is connected with the grid electrode of the first resistor R₁The right end is connected with a power supply Vdd; a second resistor R₂The right end is grounded; first PMOS transistor M_p1The source of (2) is connected with a power supply Vdd; first PMOS transistor M_p1And the first inverter inv₁Are connected with the input end of the power supply; first NMOS transistor M_N1The source of (2) is grounded; first NMOS transistor M_N1Is connected to the input of the first inverter inv; first inverter inv₁As the output signal Vs of the pulse width adjusting circuit.

Further, the duty ratio detection circuit comprises a second PMOS transistor M_P2A second NMOS transistor M_N2A third capacitor C₃Wherein the second PMOS transistor M_P2And the first inverter inv₁The output ends of the two are connected; second PMOS transistor M_P2Is connected with a current source Iref; the current source Iref is connected with a power supply Vdd; second PMOS transistor M_P2Drain and third capacitor C₃The upper-level plates are connected; second NMOS transistor M_N2And the first inverter inv₁The output ends of the two are connected; second NMOS transistor M_N2Is connected with a current source Iref; current source Iref is grounded; second oneNMOS transistor M_N2Drain and third capacitor C₃The upper-level plates are connected; first PMOS transistor M_p1And the first NMOS transistor M_N1Are respectively connected with third capacitors C₃Upper stage board of (2), third capacitor C₃The lower plate of (2) is grounded.

The invention has the beneficial effects that: the invention utilizes a pulse width adjusting circuit and a duty ratio detection circuit to convert a sinusoidal signal into a square wave with the duty ratio stabilized to 50%; the output duty cycle is locked to 50% by a negative feedback loop formed by the duty cycle detection circuit and the pulse width adjusting circuit. On the premise of ensuring normal conversion of signals, if the duty ratio of the pulse regulation circuit to output the square waves is less than 50%, the duty ratio detection circuit can automatically improve the output voltage, so that the duty ratio of the output square waves is increased, the duty ratio of the output square waves is ensured to be locked to 50%, the accuracy of the whole circuit is improved, and the power consumption of a follow-up circuit is reduced.

Drawings

FIG. 1 is a block diagram of the subject circuit of the present invention;

fig. 2 is a schematic circuit structure diagram of the pulse width adjusting circuit and the duty ratio detecting circuit according to the present invention:

wherein, 1 is a pulse width adjusting circuit, and 2 is a duty ratio detecting circuit.

Detailed Description

The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.

As shown in FIG. 1, the 50% duty cycle shaping circuit for low voltage comprises a pulse width modulation circuit 1 and a duty cycle detection circuit 2, wherein an input end of the pulse width modulation circuit 1 is connected with a voltage signal V_in(ii) a The output Vs square wave of the pulse width adjusting circuit 1 is used as one input end of the duty ratio detecting circuit 2, the other input end of the duty ratio detecting circuit 2 is connected with the current source Iref, and the output V of the duty ratio detecting circuit 2 is fed back to the pulse width adjusting circuit 1.

In practical application, the present invention designs a specific circuit structure for the pulse width modulation circuit, as shown in fig. 2.

The pulse width adjusting circuit 1 comprises a first capacitor C₁A second capacitor C_2、A first resistor R₁A second resistor R₂A first PMOS transistor M_p1A first NMOS transistor M_N1And a first inverter inv₁Wherein the voltage signal V_inAre respectively connected with a first capacitor C₁And a second capacitor C₂The upper stage plate of (1), the first capacitor C₁Respectively with the first resistor R₁Left end of the first PMOS transistor M_p1The grid electrodes are connected; second capacitor C₂Respectively with a second resistor R₂Left end of (1), first NMOS transistor M_N1Is connected with the grid electrode of the first resistor R₁The right end is connected with a power supply Vdd; a second resistor R₂The right end is grounded; first PMOS transistor M_p1The source of (2) is connected with a power supply Vdd; first PMOS transistor M_p1And the first inverter inv₁Are connected with the input end of the power supply; first NMOS transistor M_N1The source of (2) is grounded; first NMOS transistor M_N1Is connected to the input of the first inverter inv; first inverter inv₁As the output signal Vs of the pulse width adjustment circuit to the duty ratio detection circuit.

The duty ratio detection circuit 2 includes a second PMOS transistor M_P2A second NMOS transistor M_N2A third capacitor C₃Wherein the second PMOS transistor M_P2And the first inverter inv₁The output ends of the two are connected; second PMOS transistor M_P2Is connected with a current source Iref; the current source Iref is connected with a power supply Vdd; second PMOS transistor M_P2Drain and third capacitor C₃The upper-level plates are connected; second NMOS transistor M_N2And the first inverter inv₁The output ends of the two are connected; second NMOS transistor M_N2Is connected with a current source Iref; current source Iref is grounded; second NMOS transistor M_N2Drain and third capacitor C₃The upper-level plates are connected; first PMOS transistor M_p1And the first NMOS transistor M_N1Are respectively connected with third capacitors C₃Upper stage board of (2), third capacitor C₃The lower plate of (2) is grounded.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.