阅读说明：本技术 执行微指令的存储控制器 (Memory controller for executing microinstructions ) 是由 王祎磊 于 2015-05-18 设计创作，主要内容包括：本申请公开了执行微指令的存储控制器。该存储控制器包括微指令存储器、微指令处理器与接口控制器；所述微指令存储器存储微指令序列；所述微指令处理器从微指令存储器读取微指令序列,所述微指令处理器调度或执行微指令序列,以使所述接口控制器向存储器件发出访问存储器件的命令；处理第一命令时,所述微指令处理器执行与所述第一命令对应的微指令序列；其中,所述第一命令为来自用户或上层系统的命令。(A memory controller to execute micro-instructions is disclosed. The storage controller comprises a micro-instruction memory, a micro-instruction processor and an interface controller; the micro instruction memory stores a micro instruction sequence; the micro instruction processor reads a micro instruction sequence from a micro instruction memory, and schedules or executes the micro instruction sequence to enable the interface controller to send a command for accessing the memory device to the memory device; when a first command is processed, the microinstruction processor executes a microinstruction sequence corresponding to the first command; wherein the first command is a command from a user or an upper system.)

1. A memory controller is characterized by comprising a micro-instruction memory, a micro-instruction processor and an interface controller;

the micro instruction memory stores a micro instruction sequence;

the micro instruction processor reads a micro instruction sequence from a micro instruction memory, and schedules or executes the micro instruction sequence to enable the interface controller to send a command for accessing the memory device to the memory device;

when a first command is processed, the microinstruction processor executes a microinstruction sequence corresponding to the first command;

wherein the first command is a command from a user or an upper system.

2. The memory controller of claim 1, wherein after the microinstruction processor fetches a first command, the microinstruction processor converts the first command into a first microinstruction sequence corresponding to the first command; or, the memory controller further includes a conversion circuit, and after the microinstruction processor obtains the first command, the conversion circuit converts the first command into a first microinstruction sequence corresponding to the first command.

3. The memory controller of claim 2, wherein said converting the first command into a first sequence of microinstructions corresponding to the first command comprises:

selecting the first micro-instruction sequence from at least one micro-instruction sequence stored in the micro-instruction memory according to the content of the first command; or, according to the content of the first command, filling a template of a micro instruction sequence to obtain the first micro instruction sequence.

4. The storage controller of any of claims 1-3, wherein the storage controller further comprises a scheduler; the scheduler is coupled with the microinstruction processor;

the scheduler instructs the microinstruction processor to pause or resume execution of the microinstruction sequence.

5. The memory controller of claim 4, wherein in response to receiving a second command, the scheduler checks an execution status of the first micro instruction sequence and/or determines whether to suspend the first micro instruction sequence based on a priority of the first command and a second command, the second command being a command from a user or an upper system;

wherein if the first micro instruction sequence is being executed, the scheduler controls the micro instruction processor to suspend executing the first micro instruction sequence; alternatively, the first and second electrodes may be,

if the first microinstruction sequence is executing and the second command has a higher priority than the first command, the scheduler controls the microinstruction processor to suspend executing the first microinstruction sequence.

6. The memory controller of any of claims 1-5, wherein the memory controller further comprises a status register and a pool of registers; the state register is used for saving and providing the execution state of the micro-instruction sequence to the micro-instruction processor; the register pool is used for storing the execution states of a plurality of micro instruction sequences.

7. The memory controller of claim 6, wherein after the micro instruction processor pauses the first micro instruction sequence, an execution state of the first micro instruction sequence before pausing is saved to the status register;

and the scheduler resumes the execution of the first micro-instruction sequence by acquiring the execution state of the first micro-instruction sequence before suspension from the state register.

8. The memory controller of any of claims 5-7, wherein the scheduler controls the microinstruction processor to execute a second microinstruction sequence corresponding to the second command after the first microinstruction sequence is suspended; alternatively, the scheduler controls the microinstruction processor to execute other microinstruction sequences.

9. The memory controller of any of claims 1-3, wherein the first micro instruction sequence comprises a yield micro instruction, the first micro instruction sequence yielding in response to the micro instruction processor executing the yield micro instruction;

in response to the first micro instruction sequence yielding, the scheduler causes the micro instruction processor to execute one of the micro instruction sequences stored in the micro instruction memory.

10. A storage device comprising a storage controller according to any of claims 1-9.

Technical Field

The present invention relates to Solid State Storage Devices (SSDs), and more particularly, to a memory controller that executes microinstructions.

Background

Like mechanical hard disks, solid State Storage Devices (SSDs) are also large capacity, non-volatile storage devices for computer systems. Solid state memory devices typically use Flash memory (Flash) as a storage medium. Fig. 1 is a block diagram of a prior art memory system. Which mainly includes a host system 110 and a solid-state storage device 120. The solid-state storage device 120 includes an interface module 130, a storage controller 140, and a Flash array 160 composed of a plurality of Flash memory granules 150. The Interface module 130 is mainly used to implement an Interface protocol for communicating with a host System, such as SATA (Serial advanced technology Attachment), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), nvme (nvmexpress), SCSI (Small Computer System Interface), IDE (Integrated Drive Electronics), and the like. Through the interface module 130, the solid-state storage device presents to the host system a standard storage device that possesses a certain logical address space or physical address space. The memory controller 140 is a control core of the entire memory device, and is mainly responsible for transmission of control signals and data between the interface module 130 and the flash memory array 160, flash memory management, conversion or mapping of host logical addresses to flash memory physical addresses, wear leveling, and/or bad block management. The storage controller 140 may be implemented in a variety of ways, including software, hardware, firmware, or a combination thereof.

Memory controller 140 accesses flash granule 150 by sending commands to flash granule 150 in flash array 160. Commands to access the flash granule 150 include, for example, read, program, and/or erase, etc. The commands that access the flash granule 150 also include a suspend command for temporarily suspending execution of commands that have been sent to the flash granule 150.

The execution time for the program, erase, etc. commands is relatively long compared to the read commands. If the read command is issued to the flash granule 150 after the program or erase command, the read command needs to wait for the program or erase command to complete before it can be executed, which in turn results in a longer response time for the read operation and an increased read latency of the memory device 120. Similarly, if a program command is issued to the flash granule 150 after an erase command, the program command needs to wait for the erase command to complete before it can be executed, which in turn results in a longer response time for the program command.

Execution of a program or erase command on the flash granule 150 may be temporarily suspended by issuing a suspend command to the flash granule 150, and then the flash granule 150 may respond to the read command and resume execution of the suspended program or erase command by issuing a resume command to the flash granule 150 after the read command execution is complete. During the execution of a program or erase command by flash granule 150, a suspend command and a resume command may be received multiple times, and the same program or erase command may be suspended and resumed multiple times.

In U.S. patent application publication No. US2013/0198451a1, conditional execution of pause commands is provided. Upon receiving a read/write command, a suspend threshold is calculated based on a suspend policy, and it is determined whether a previous erase operation satisfies the suspend threshold. If the suspend threshold is satisfied, the previous erase operation is suspended, and if the suspend threshold is not satisfied, the previous erase operation is completed.

In chinese patent application publication No. CN1414468A, a scheme is provided for Processing a CPU (Central Processing Unit) instruction by executing a micro instruction sequence. When the CPU is to process a specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In converting a particular instruction into a micro instruction sequence, the micro instruction sequence template may be populated to correspond to the particular instruction.

Disclosure of Invention

Although the prior art provides a scheme for determining whether to issue a pause command by checking a pause threshold, it is still desirable to provide more flexibility for controlling the timing of issuing the pause command. And it is desirable that users of the storage device be able to engage in flexible control over the timing of issuance of flash suspend commands, rather than relying on the storage controller to implement scheduling of multiple commands to access the flash granules.

To achieve the above objects, the present invention responds to commands from a host or user through the execution of a sequence of micro instructions. Execution of the micro instruction sequence by the micro instruction processor issues operation commands to the flash memory granule and/or receives data or other information read from the flash memory granule. A user of the storage device can participate in the flexible control of the timing of issuance of the flash suspend command by programming, updating, and/or modifying the micro instruction sequence.

According to a first aspect of the present invention, there is provided a first method of scheduling a sequence of microinstructions, comprising: when a first command is received, executing a first microinstruction sequence corresponding to the first command; pausing (suspend) the first micro instruction sequence if the first micro instruction sequence is executing while a second command is received; executing a second micro instruction sequence corresponding to the second command.

According to the first aspect of the present invention, there is also provided a second method of scheduling a micro instruction sequence, comprising: when a first command is received, executing a first microinstruction sequence corresponding to the first command; the first micro instruction sequence causes the controller to: the first micro instruction sequence yields; when a second command is received, executing a second microinstruction sequence corresponding to the second command; the second micro instruction sequence causes the controller to: the second micro instruction sequence yields; checking the execution state of the micro instruction sequence; restoring the second micro instruction sequence.

According to the first method or the second method of the first aspect of the present invention, there is provided the third method of the first aspect of the present invention, wherein: the executing the first sequence of microinstructions corresponding to the first command further comprises: a timer is started.

According to a third method of the first aspect of the present invention, there is provided the fourth method of the first aspect of the present invention, wherein if the first microinstruction sequence is executing and if the timer records a time less than a threshold value, suspending (suspend) the first microinstruction sequence; executing the second micro instruction sequence.

According to a fifth method of the first aspect of the present invention, there is provided the method of the first aspect of the present invention, wherein: pausing (suspend) the first micro instruction sequence if the first micro instruction sequence is executing and if the second command has a higher priority than the first command; executing the second micro instruction sequence.

According to one of the above methods of the first aspect of the invention, there is provided a sixth method of the first aspect of the invention, wherein: the first command indicates a memory erase operation and/or a memory program operation; and the second command indicates a memory read operation.

According to one of the above methods of the first aspect of the present invention, there is provided the seventh method of the first aspect of the present invention, wherein the suspending (suspend) the first microinstruction sequence comprises: a command to suspend a memory erase operation and/or a memory program operation is sent to the memory.

According to a seventh method of the first aspect of the present invention, there is provided the eighth method of the first aspect of the present invention, the eighth method further comprising: restoring the first micro instruction sequence in response to completion of execution of the second micro instruction sequence.

According to an eighth method of the first aspect of the present invention, there is provided the ninth method of the first aspect of the present invention, wherein restoring the first microinstruction sequence comprises: sending a command to a memory to resume the memory erase operation and/or memory program operation.

According to a fifth method of the first aspect of the invention there is provided the tenth method of the first aspect of the invention, the tenth method further comprising: adjusting a priority of the first command and/or the second command.

According to a second aspect of the invention, there is provided a first method of scheduling memory operations, comprising: when a first command is received, if the first command indicates an erasing operation, executing an erasing operation micro-instruction sequence;

the erase operation micro instruction sequence causes the memory controller to:

issuing an erase command to the memory device; and

the erase operation micro instruction sequence yields (yield);

when a second command is received, if the second command indicates a read operation, executing a read operation micro-instruction sequence; the read operation micro instruction sequence causes the memory controller to:

reading the operation micro-instruction sequence yield; and

issuing a read command to a memory device;

the first method further includes checking an execution status of the micro instruction sequence; and recovering the read operation micro-instruction sequence.

According to a second aspect of the present invention there is provided a method as defined in the second aspect of the present invention, wherein the erase operation microinstruction sequence causes the memory controller to:

issuing an erase command to the memory device;

starting a timer; and

the erase operation micro instruction sequence yields (yield);

and in the second method of the second aspect of the invention: and checking the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, sending a command for suspending the erasing operation of the memory to the memory, and recovering the micro-instruction sequence of the reading operation.

According to a third method of the second aspect of the invention there is provided the method of the second aspect of the invention, wherein the sequence of erase operation microinstructions causes the memory controller to:

starting a timer;

issuing an erase command to the memory device; and

the erase operation micro instruction sequence yields (yield);

and in a third method of the second aspect of the invention: and checking the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, sending a command for suspending the erasing operation of the memory to the memory, and recovering the micro-instruction sequence of the reading operation.

According to a second or third method of the second aspect of the invention there is provided a fourth method of the second aspect of the invention wherein the execution status of the micro instruction sequence is checked and the timer is also halted if the time recorded by the timer is less than a threshold value.

According to a fourth method of the second aspect of the present invention, there is provided the fifth method of the second aspect of the present invention, wherein the read operation micro instruction sequence causes the memory controller to:

reading the operation micro-instruction sequence yield;

issuing a read command to a memory device; and

acquiring data returned by a memory;

and a fifth method of the second aspect of the invention: and recovering the erasing operation micro-instruction sequence in response to the completion of the execution of the reading operation micro-instruction sequence.

According to a fifth method of the second aspect of the present invention, there is provided the sixth method of the second aspect of the present invention, wherein the restoring the erase operation microinstruction sequence includes restoring the timer.

According to a seventh method of the second aspect of the present invention, there is provided the seventh method of the second aspect of the present invention, wherein the execution status of the micro instruction sequence is checked, and if the priority of the second command is higher than that of the first command, a command to suspend the memory erase operation is sent to the memory, and the read operation micro instruction sequence is resumed.

According to one of the above methods of the second aspect of the present invention, there is provided the eighth method of the second aspect of the present invention, wherein the resuming the read operation microinstruction sequence comprises: sending a command to a memory to resume the memory erase operation and/or memory program operation.

According to a seventh method of the second aspect of the present invention, there is provided the ninth method of the second aspect of the present invention, further comprising: adjusting a priority of the first command and/or the second command.

According to a third aspect of the present invention, there is provided a method of first executing a micro instruction sequence, comprising: processing a first command, and if the first command indicates an erase operation, issuing an erase command to the memory device; during the execution of the erase operation, if a second command indicating a read operation is received, a command to suspend (suspend) the erase operation is issued to the memory device, and a read command is issued to the memory device.

According to a first method of the third aspect of the present invention, there is provided the second method of the third aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is not completed, the micro instruction sequence yields (yield).

According to the third aspect of the present invention, there is provided the third method according to the third aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, data returned from the memory device is acquired; and issuing a command to resume the erase operation.

According to a third aspect of the present invention, there is provided the fourth method according to the third aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, after a command to resume the erase operation is issued, the micro instruction sequence yields (yield).

According to one of the above methods of the third aspect of the present invention, there is provided the fifth method of the third aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, wherein if the first command indicates an erase operation, a timer is further started; and if a second command indicating a read operation is received and the time recorded by the timer is less than the threshold, issuing a command to suspend (suspend) the erase operation to the memory device and issuing a read command to the memory device.

According to a fifth method of the third aspect of the present invention, there is provided the sixth method of the third aspect of the present invention, wherein after a read command is issued to the memory device, the execution status is checked, and if the execution of the read command is completed, wherein after the data returned from the memory device is acquired after the execution of the read command is completed, the timer is resumed.

According to one of the above-described methods of the third aspect of the present invention, there is provided the seventh method of the third aspect of the present invention, wherein if a second command indicating a read operation is received and the second command has a higher priority than the first command, a command to suspend (suspend) the erase operation is issued to the memory device, and a read command is issued to the memory device.

According to a seventh method of the third aspect of the present invention, there is provided the eighth method of the third aspect of the present invention, further comprising: adjusting a priority of the first command and/or the second command.

According to a fourth aspect of the present invention, there is still provided a method for executing a micro instruction sequence, comprising: processing a first command, and if the first command indicates an erase operation, issuing an erase command to the memory device; a second command is checked, and if the second command indicates a read operation, a command to suspend (suspend) the erase operation is issued to the memory device, and a read command is issued to the memory device.

According to a first method of the fourth aspect of the present invention, there is provided the second method of the fourth aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is not completed, the micro instruction sequence yields (yield).

According to the third method of the fourth aspect of the present invention, there is provided the first method or the second method of the fourth aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, data returned from the memory device is acquired; and issuing a command to resume the erase operation.

According to a fourth aspect of the present invention, there is provided the fourth method of the fourth aspect of the present invention, wherein the micro instruction sequence yields (yield) after issuing the command to resume the erase operation.

According to one of the above methods of the fourth aspect of the present invention, there is provided the fifth method of the fourth aspect of the present invention, wherein if the first command indicates an erase operation, a timer is further started; and if the second command indicates a read operation and the time recorded by the timer is less than the threshold, issuing a command to suspend (suspend) the erase operation to the memory device and issuing a read command to the memory device.

According to a fifth method of the fourth aspect of the present invention, there is provided the sixth method of the fourth aspect of the present invention, wherein the timer is recovered after data returned from the memory is acquired after the execution of the read command is completed.

According to one of the above-mentioned methods of the fourth aspect of the present invention, there is provided the seventh method of the fourth aspect of the present invention, wherein if the second command indicates a read operation and the second command has a higher priority than the first command, a command to suspend (suspend) the erase operation is issued to the memory device and a read command is issued to the memory device.

According to a seventh method of the fourth aspect of the present invention, there is provided the eighth method of the fourth aspect of the present invention, further comprising: adjusting a priority of the first command and/or the second command.

According to a fifth aspect of the present invention, there is provided a first memory controller comprising a micro instruction memory, a micro instruction processor and a scheduler; the micro instruction memory stores a first micro instruction sequence and a second micro instruction sequence; in response to receiving a first command, the microinstruction processor executes a first sequence of microinstructions; in response to receiving a second command, a scheduler checks an execution status of the first micro instruction sequence and suspends (suspend) the first micro instruction sequence if the first micro instruction sequence is executing; and causes the microinstruction processor to execute the second microinstruction sequence.

According to a fifth aspect of the present invention, there is provided a second memory controller comprising a micro instruction memory, a micro instruction processor and a scheduler; the micro instruction memory stores a first micro instruction sequence and a second micro instruction sequence; in response to receiving a first command, the microinstruction processor executes a first sequence of microinstructions; the first micro instruction sequence causes the controller to: the first micro instruction sequence yields; in response to receiving a second command, the microinstruction processor executes executing a second sequence of microinstructions; the second micro instruction sequence causes the controller to: the second micro instruction sequence yields; the scheduler checks the micro instruction sequence execution state and resumes execution of the second micro instruction sequence on the micro instruction processor.

According to the first storage controller or the second storage controller of the fifth aspect of the present invention, there is provided the third storage controller of the fifth aspect of the present invention, wherein: the memory controller further comprises a timer; the executing the first micro instruction sequence further comprises: a timer is started.

According to a third memory controller of the fifth aspect of the present invention, there is provided the fourth memory controller of the fifth aspect of the present invention, wherein the scheduler suspends (suspend) the first micro instruction sequence and causes the micro instruction processor to execute the second micro instruction sequence if the first micro instruction sequence is found to be executing and if the time recorded by the timer is less than a threshold value.

According to a fifth aspect of the present invention, there is provided the fifth storage controller according to the fifth aspect of the present invention, wherein: if the scheduler finds that the first micro instruction sequence is executing and if the second command has a higher priority than the first command, the scheduler suspends (suspend) the first micro instruction sequence and causes the micro instruction processor to execute the second micro instruction sequence.

According to one of the above-described storage controllers of the fifth aspect of the present invention, there is provided a sixth storage controller according to the fifth aspect of the present invention, wherein: the first command indicates a memory erase operation and/or a memory program operation; and the second command indicates a memory read operation.

According to one of the above-described memory controllers of the fifth aspect of the present invention, there is provided the seventh memory controller of the fifth aspect of the present invention, wherein the suspending (suspend) the first micro instruction sequence includes: a command to suspend a memory erase operation and/or a memory program operation is sent to the memory through the interface controller.

According to a seventh storage controller of the fifth aspect of the present invention, there is provided the eighth storage controller of the fifth aspect of the present invention, further comprising: the scheduler causes the microinstruction processor to resume the first microinstruction sequence in response to completion of execution of the second microinstruction sequence.

According to an eighth memory controller of the fifth aspect of the present invention, there is provided the ninth memory controller of the fifth aspect of the present invention, wherein the restoring the first microinstruction sequence includes: sending a command to the memory through the interface controller to resume the memory erase operation and/or the memory program operation.

According to a fifth storage controller of the fifth aspect of the present invention, there is provided the tenth storage controller of the fifth aspect of the present invention, further comprising: the scheduler adjusts a priority of the first command and/or the second command.

According to a sixth aspect of the present invention, there is provided a first memory controller comprising a micro instruction memory, a micro instruction processor and a scheduler; the micro instruction memory stores an erasing operation micro instruction sequence and a reading operation micro instruction sequence; in response to receiving a first command, a scheduler causes the microinstruction processor to execute an erase operation microinstruction sequence if it is determined that the first command indicates an erase operation; the erase operation micro instruction sequence causes the micro instruction processor to: issuing an erase command to the memory device; and an erase operation micro instruction sequence yield (yield); in response to receiving a second command, the scheduler causes the microinstruction processor to execute a read operation microinstruction sequence if it is determined that the second command indicates a read operation; the read operation microinstruction sequence causes the microinstruction processor to: reading the operation micro-instruction sequence yield; and issuing a read command to the memory device; the scheduler checks the execution status of the micro instruction sequence and causes the micro instruction controller to resume execution of the read operation micro instruction sequence.

According to a sixth aspect of the present invention there is provided a second memory controller according to the sixth aspect of the present invention, the second memory controller further comprising a timer, wherein the erase operation microinstruction sequence causes the microinstruction processor to: issuing an erase command to the memory device; starting a timer; and an erase operation micro instruction sequence yield (yield); and wherein: and the scheduler checks the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, the interface controller sends a command for suspending the erasing operation of the memory to the memory, and the micro-instruction processor resumes the execution of the micro-instruction sequence of the read operation.

According to a sixth aspect of the present invention there is provided a third memory controller according to the sixth aspect of the present invention, the third memory controller further comprising a timer, wherein the sequence of erase operations microinstructions causes the microinstruction processor to: starting a timer; issuing an erase command to the memory device; and an erase operation micro instruction sequence yield (yield); and wherein: and the scheduler checks the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, the interface controller sends a command for suspending the erasing operation of the memory to the memory, and the micro-instruction processor resumes the execution of the micro-instruction sequence of the read operation.

According to a second memory controller or a third memory controller of the sixth aspect of the present invention, there is provided the fourth memory controller according to the sixth aspect of the present invention, wherein the scheduler checks an execution status of the micro instruction sequence, and also suspends the timer if a time recorded by the timer is less than a threshold value.

According to a fourth memory controller of a sixth aspect of the present invention, there is provided the fifth memory controller of the sixth aspect of the present invention, wherein the read operation microinstruction sequence causes the microinstruction processor to: reading the operation micro-instruction sequence yield; issuing a read command to a memory device; and acquiring data returned by the memory; and wherein: in response to completion of execution of the read operation microinstruction sequence, the scheduler causes the microinstruction processor to resume execution of the erase operation microinstruction sequence.

According to a fifth memory controller of a sixth aspect of the present invention, there is provided the sixth memory controller of the sixth aspect of the present invention, wherein the resuming the erase operation microinstruction sequence includes resuming the timer.

According to a sixth aspect of the present invention, there is provided the seventh memory controller according to the sixth aspect of the present invention, wherein the scheduler checks an execution state of the micro instruction sequence, and if the priority of the second command is higher than that of the first command, causes the interface controller to send a command to suspend the memory erase operation to the memory, and causes the micro instruction processor to resume execution of the read operation micro instruction sequence.

According to a sixth aspect of the present invention, there is provided the fifth memory controller according to the eighth aspect of the present invention, wherein the scheduler causes the micro-instruction controller to resume execution of the read operation micro-instruction sequence: causing the interface controller to send a command to the memory to resume the memory erase operation and/or memory program operation.

According to a seventh storage controller of the sixth aspect of the present invention, there is provided the ninth storage controller of the sixth aspect of the present invention, wherein the scheduler adjusts the priority of the first command and/or the second command.

According to a seventh aspect of the present invention there is provided a memory device comprising one of the memory controllers according to the fifth or sixth aspects of the present invention.

According to an eighth aspect of the present invention, there is provided an electronic system comprising a computer and a storage device coupled to the computer, the storage device being responsive to an access request from the computer; the memory device is a memory device according to the seventh aspect of the present invention.

According to a ninth aspect of the present invention, there is provided a non-transitory computing device readable medium having stored thereon a program, the program comprising a sequence of micro instructions; the program, when executed by a computing device, causes the computing device to be configured to perform one of the methods according to the third or fourth aspect of the invention.

According to a tenth aspect of the present invention there is provided a program comprising a sequence of micro instructions which, when executed by a computing device, causes the computing device to be configured to perform one of the methods according to the third or fourth aspects of the present invention.

According to an eleventh aspect of the present invention, there is provided a first execution device of a micro instruction sequence, comprising: a first means for processing a first command, and issuing an erase command to the memory device if the first command indicates an erase operation; and a second means for issuing a command to suspend (suspend) the erase operation to the memory device and issuing a read command to the memory device if a second command indicating a read operation is received during the execution of the erase operation.

According to a first device of an eleventh aspect of the present invention, there is provided the device of the eleventh aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is not completed, the micro instruction sequence yields (yield).

According to the first device or the second device of the eleventh aspect of the present invention, there is provided the third device of the eleventh aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if execution of the read command is completed, data returned from the memory is acquired; and issuing a command to resume the erase operation.

According to a third device of an eleventh aspect of the present invention, there is provided the fourth device of the eleventh aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if execution of the read command is completed, wherein after a command to resume the erase operation is issued, the micro instruction sequence yields (yield).

According to one of the above-mentioned devices of the eleventh aspect of the present invention, there is provided the fifth device of the eleventh aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, wherein if the first command indicates an erase operation, a timer is further started; and if a second command indicating a read operation is received and the time recorded by the timer is less than the threshold, issuing a command to suspend (suspend) the erase operation to the memory device and issuing a read command to the memory device.

According to a fifth apparatus of the eleventh aspect of the present invention, there is provided the sixth apparatus of the eleventh aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is completed, wherein the timer is recovered after data returned from the memory is acquired after the execution of the read command is completed.

According to one of the above-described devices of the eleventh aspect of the present invention, there is provided the seventh device of the eleventh aspect of the present invention, wherein if a second command indicating a read operation is received and the second command has a higher priority than the first command, a command to suspend (suspend) the erase operation is issued to the memory device, and a read command is issued to the memory device.

According to a seventh apparatus of the eleventh aspect of the present invention, there is provided the eighth apparatus of the eleventh aspect of the present invention, further comprising: third means for adjusting a priority of the first command and/or the second command.

According to a twelfth aspect of the present invention, there is still provided a first execution device of a micro instruction sequence, comprising: a first means for processing a first command, and issuing an erase command to the memory device if the first command indicates an erase operation; and a second means for checking a second command, issuing a command to suspend (suspend) the erase operation to the memory device if the second command indicates a read operation, and issuing a read command to the memory device.

According to a twelfth aspect of the present invention, there is provided the second apparatus of the twelfth aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if the execution of the read command is not completed, the micro instruction sequence yields (yield).

According to the first device or the second device of the twelfth aspect of the present invention, there is provided the third device of the twelfth aspect of the present invention, wherein after a read command is issued to the memory device, an execution status is checked, and if execution of the read command is completed, data returned from the memory is acquired; and issuing a command to resume the erase operation.

According to a third device of the twelfth aspect of the present invention, there is provided the fourth device of the twelfth aspect of the present invention, wherein the micro instruction sequence yields (yield) after issuing a command to resume the erase operation.

According to one of the above devices of the twelfth aspect of the present invention, there is provided the fifth device of the twelfth aspect of the present invention, wherein if the first command indicates an erase operation, a timer is further started; and if the second command indicates a read operation and the time recorded by the timer is less than the threshold, issuing a command to suspend (suspend) the erase operation to the memory device and issuing a read command to the memory device.

According to a fifth apparatus of the twelfth aspect of the present invention, there is provided the apparatus of the twelfth aspect of the present invention, wherein the timer is recovered after data returned from the memory is acquired after the execution of the read command is completed.

According to one of the above devices of the twelfth aspect of the present invention, there is provided the seventh device of the twelfth aspect of the present invention, wherein if the second command indicates a read operation and the second command has a higher priority than the first command, a command to suspend (suspend) the erase operation is issued to the memory device and a read command is issued to the memory device.

According to a seventh apparatus of the twelfth aspect of the present invention, there is provided the eighth apparatus of the twelfth aspect of the present invention, further comprising: third means for adjusting a priority of the first command and/or the second command.

According to a thirteenth aspect of the present application, there is provided a first memory controller according to the thirteenth aspect of the present application, comprising a micro instruction memory, a micro instruction processor and an interface controller; the micro instruction memory stores a micro instruction sequence; the micro instruction processor reads a micro instruction sequence from a micro instruction memory, and schedules or executes the micro instruction sequence to enable the interface controller to send a command for accessing the memory device to the memory device; when a first command is processed, the microinstruction processor executes a microinstruction sequence corresponding to the first command; wherein the first command is a command from a user or an upper system.

According to a first memory controller of a thirteenth aspect of the present application, there is provided the second memory controller of the thirteenth aspect of the present application, wherein after the microinstruction processor fetches a first command, the microinstruction processor converts the first command into a first microinstruction sequence corresponding to the first command; or, the memory controller further includes a conversion circuit, and after the microinstruction processor obtains the first command, the conversion circuit converts the first command into a first microinstruction sequence corresponding to the first command.

According to a second memory controller of the thirteenth aspect of the present application, there is provided the third memory controller of the thirteenth aspect of the present application, wherein the converting the first command into a first microinstruction sequence corresponding to the first command includes: selecting the first micro-instruction sequence from at least one micro-instruction sequence stored in the micro-instruction memory according to the content of the first command; or, according to the content of the first command, filling a template of a micro instruction sequence to obtain the first micro instruction sequence.

According to one of the first to third storage controllers of the thirteenth aspect of the present application, there is provided the fourth storage controller according to the thirteenth aspect of the present application, further comprising a scheduler; the scheduler is coupled with the microinstruction processor; the scheduler instructs the microinstruction processor to pause or resume execution of the microinstruction sequence.

According to a fourth memory controller of the thirteenth aspect of the present application, there is provided the fifth memory controller of the thirteenth aspect of the present application, wherein in response to receiving a second command, the scheduler checks an execution status of the first micro instruction sequence, and/or determines whether to suspend the first micro instruction sequence according to priorities of the first command and a second command, the second command being a command from a user or an upper system; wherein if the first micro instruction sequence is being executed, the scheduler controls the micro instruction processor to suspend executing the first micro instruction sequence; or, if the first microinstruction sequence is executing and the second command has a higher priority than the first command, the scheduler controls the microinstruction processor to suspend executing the first microinstruction sequence.

According to one of the first to fifth memory controllers of the thirteenth aspect of the present application, there is provided the sixth memory controller according to the thirteenth aspect of the present application, further comprising a status register and a register pool; the state register is used for saving and providing the execution state of the micro-instruction sequence to the micro-instruction processor; the register pool is used for storing the execution states of a plurality of micro instruction sequences.

According to a sixth memory controller of the thirteenth aspect of the present application, there is provided the seventh memory controller of the thirteenth aspect of the present application, wherein after the micro instruction processor suspends the first micro instruction sequence, an execution state before the suspension of the first micro instruction sequence is saved to the status register; and the scheduler resumes the execution of the first micro-instruction sequence by acquiring the execution state of the first micro-instruction sequence before suspension from the state register.

According to one of the fifth to seventh memory controllers of the thirteenth aspect of the present application, there is provided the eighth memory controller of the thirteenth aspect of the present application, wherein the scheduler controls the microinstruction processor to execute the second microinstruction sequence corresponding to the second command after the first microinstruction sequence is suspended; alternatively, the scheduler controls the microinstruction processor to execute other microinstruction sequences.

According to one of the first to third memory controllers of the thirteenth aspect of the present application, there is provided the ninth memory controller of the thirteenth aspect of the present application, wherein the first micro instruction sequence comprises a yield micro instruction, the first micro instruction sequence yielding in response to the micro instruction processor executing the yield micro instruction; in response to the first micro instruction sequence yielding, the scheduler causes the micro instruction processor to execute one of the micro instruction sequences stored in the micro instruction memory.

According to a ninth memory controller of the thirteenth aspect of the present application, there is provided the tenth memory controller of the thirteenth aspect of the present application, wherein the scheduler checks an execution status of the microinstruction sequences stored in the microinstruction memory and/or determines the microinstruction sequences to be scheduled for execution according to the priorities of the first and second commands.

According to a fourth or fifth memory controller of the thirteenth aspect of the present application, there is provided the eleventh memory controller of the thirteenth aspect of the present application, wherein the micro instruction memory stores therein a first micro instruction sequence and a second micro instruction sequence, the first micro instruction sequence and the second micro instruction sequence each including a yield micro instruction; in response to receiving a first command, the microinstruction processor executes a first sequence of microinstructions; in response to executing the first microinstruction sequence, the first microinstruction sequence yields; if the microinstruction processor receives a second command after the first microinstruction sequence yields, the microinstruction processor executes the second microinstruction sequence; in response to executing the second micro instruction sequence, the second micro instruction sequence yields; the scheduler checks the micro instruction sequence execution state and resumes execution of the second micro instruction sequence on the micro instruction processor.

According to a fourth, fifth or eleventh storage controller of the thirteenth aspect of the present application, there is provided the twelfth storage controller according to the thirteenth aspect of the present application, further comprising a timer; the timer is started in response to executing the first micro instruction sequence.

According to a twelfth storage controller of the thirteenth aspect of the present application, there is provided the thirteenth storage controller of the thirteenth aspect of the present application, wherein the scheduler suspends the first microinstruction sequence and causes the microinstruction processor to execute the second microinstruction sequence if the first microinstruction sequence is found to be executing or the time recorded by the timer is less than a threshold value.

According to one of the fifth to thirteenth memory controllers of the thirteenth aspect of the present application, there is provided the fourteenth memory controller of the thirteenth aspect of the present application, wherein the scheduler controls the microinstruction processor to suspend executing the first microinstruction sequence, comprising: a command to suspend a memory erase operation and/or a memory program operation is sent to the memory device through the interface controller.

According to a thirteenth memory controller of the thirteenth aspect of the present application, there is provided the fifteenth memory controller of the thirteenth aspect of the present application, wherein the scheduler controls the microinstruction processor to resume executing the first microinstruction sequence in response to completion of execution of the second microinstruction sequence.

According to a seventh or fifteenth memory controller of the thirteenth aspect of the present application, there is provided the sixteenth memory controller of the thirteenth aspect of the present application, wherein the micro-instruction processor resumes executing the first micro-instruction sequence, including sending a command to resume the memory erase operation and/or memory program operation to a memory through the interface controller.

According to a fourth storage controller of the thirteenth aspect of the present application, there is provided the seventeenth storage controller of the thirteenth aspect of the present application, wherein the scheduler is further configured to adjust a priority of the first command and/or the second command.

According to one of the fifth to twelfth memory controllers of the thirteenth aspect of the present application, there is provided the eighteenth memory controller of the thirteenth aspect of the present application, wherein the micro instruction memory stores therein an erase operation micro instruction sequence and a read operation micro instruction sequence; in response to receiving a first command, a scheduler causes the microinstruction processor to execute an erase operation microinstruction sequence if it is determined that the first command indicates an erase operation; the erase operation micro instruction sequence causes the micro instruction processor to: issuing an erase command to the memory device and yielding an erase operation micro instruction sequence; in response to receiving a second command, the scheduler controls the microinstruction processor to execute a read operation microinstruction sequence if it is determined that the second command indicates a read operation; the read operation microinstruction sequence causes the microinstruction processor to: the read operation micro instruction sequence yields and sends a read command to the memory device; the scheduler checks the execution state of the micro instruction sequence and controls the micro instruction processor to resume execution of the read operation micro instruction sequence.

According to an eighteenth memory controller of the thirteenth aspect of the present application, there is provided the nineteenth memory controller of the thirteenth aspect of the present application, the erase operation microinstruction sequence causes the microinstruction processor to: issuing an erase command to the memory device; starting a timer; the erase operation micro instruction sequence yields; the scheduler checks the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, the interface controller is controlled to send a command for suspending the memory erasing operation to the memory, and the micro-instruction processor is controlled to resume the execution of the micro-instruction sequence of the read operation.

According to an eighteenth memory controller of the thirteenth aspect of the present application, there is provided the twentieth memory controller of the thirteenth aspect of the present application, wherein the erase operation microinstruction sequence causes the microinstruction processor to: starting a timer; issuing an erase command to the memory device; the erase operation micro instruction sequence yields; the scheduler checks the execution state of the micro-instruction sequence, and if the time recorded by the timer is less than a threshold value, the interface controller is controlled to send a command for suspending the memory erasing operation to the memory, and the micro-instruction processor is controlled to resume the execution of the micro-instruction sequence of the reading operation.

According to a nineteenth or twentieth memory controller of the thirteenth aspect of the present application, there is provided the twenty-first memory controller of the thirteenth aspect of the present application, wherein the scheduler checks an execution state of the microinstruction sequence and suspends the timer if a time recorded by the timer is less than a threshold value.

According to one of the eighteenth to twenty-first memory controllers of the thirteenth aspect of the present application, there is provided the twenty-second memory controller of the thirteenth aspect of the present application, wherein the read operation microinstruction sequence causes the microinstruction processor to: reading the operation micro-instruction sequence yield; issuing a read command to a memory device; acquiring data returned by a memory; wherein the scheduler causes the microinstruction processor to resume execution of the erase operation microinstruction sequence in response to completion of execution of the read operation microinstruction sequence.

According to a twenty-second memory controller of the thirteenth aspect of the present application, there is provided the twenty-third memory controller of the thirteenth aspect of the present application, wherein the restoring the erase operation microinstruction sequence includes restoring the timer.

According to an eighteenth memory controller of the thirteenth aspect of the present application, there is provided the twenty-fourth memory controller of the thirteenth aspect of the present application, wherein the scheduler checks an execution state of the micro instruction sequence, causes the interface controller to send a command to suspend the memory erase operation to the memory if the priority of the second command is higher than the priority of the first command, and controls the micro instruction processor to resume execution of the read operation micro instruction sequence.

According to a fourteenth aspect of the present application, there is provided a first storage apparatus according to the fourteenth aspect of the present application, comprising the storage controller according to any one of the above-described thirteenth aspects.

According to a fifteenth aspect of the present application, there is provided a first electronic system according to the fifteenth aspect of the present application, comprising a computer and a storage device coupled to the computer, the storage device being responsive to access requests from the computer; the storage device is a storage device as described in the above fourteenth aspect.

Drawings

The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a prior art storage system;

FIG. 2 is a block diagram of the structure of the components of the memory controller that process microinstructions according to an embodiment of the invention;

FIG. 3 is a flow diagram of a method of scheduling a micro instruction sequence according to an embodiment of the invention;

FIG. 4 is a block diagram of the components of a memory controller that process microinstructions according to another embodiment of the present invention;

FIG. 5 is a timing diagram illustrating the processing of a scheduler and a microinstruction processor according to another embodiment of the present invention;

FIG. 6 is a block diagram of the components of a memory controller that process microinstructions according to another embodiment of the present invention;

FIG. 7 is a flowchart of a method of executing a micro instruction sequence according to an embodiment of the invention;

FIG. 8 is a flowchart of a method of executing a micro instruction sequence according to yet another embodiment of the invention; and

FIG. 9 is a flowchart illustrating a method for executing a micro instruction sequence according to yet another embodiment of the invention.

Detailed Description

Referring to FIG. 2, FIG. 2 is a block diagram of the structure of the components of the memory controller that process microinstructions according to an embodiment of the invention. To enable processing of the microinstructions, the memory controller of the storage device may include a microinstruction processor 210, a command queue 220, an interface controller 230, and/or a microinstruction memory 240.

The micro instruction memory 240 is used to store micro instructions. The microinstruction processor 210 reads and executes the microinstructions from the microinstruction memory 240. The micro instructions cause the micro instruction processor to issue commands to the flash granule through the interface controller 230 to access the flash granule, including, for example, commands to read, program, erase, pause, read a flash granule feature (feature) and/or read a set granule feature. The micro instructions also cause the micro instruction processor to obtain data read from the flash memory granule through the interface controller 230. The micro instruction or micro instructions may correspond to one of the commands to read, program, erase, and/or suspend, etc., access the flash memory granule. The microinstructions may also include branch, jump microinstructions that cause the microinstruction processor to change the order in which the microinstructions are executed.

One or more micro instruction sequences may be stored in the micro instruction memory 240. By way of example, n micro instruction sequences are stored in the micro instruction memory 240 of FIG. 2, including micro instruction sequence 1, micro instruction sequence 2 … …, and micro instruction sequence n. Each of the micro instruction sequence 1, the micro instruction sequence 2 … …, and the micro instruction sequence n includes a plurality of micro instructions.

Multiple microinstructions in the microinstruction sequence may be executed by the microinstruction processor 210. Each micro instruction sequence has its own execution state so that execution of each micro instruction can be suspended and resumed. The microinstruction processor can suspend the executing microinstruction sequence and select to execute other microinstruction sequences. Yield microinstructions may also be provided in the microinstruction sequence, and when the yield microinstruction is executed, the microinstruction processor may schedule and execute other microinstruction sequences. When the microinstruction processor 210 suspends the executing microinstruction sequence or executes the yield microinstruction, the execution state of the executing microinstruction sequence is saved; when the micro instruction processor resumes execution of the micro instruction sequence, the saved execution state is read out, thereby resuming execution of the resumed micro instruction sequence.

Interface controller 230 is coupled to the flash granule for issuing commands to the flash granule to access the flash granule, including, for example, read, program, erase, suspend and/or resume, etc.; and also for obtaining data read from the flash memory granule.

The command queue 220 is used to buffer commands from a user or an upper system. Commands from a user or upper system may include read, write, delete, mark as invalid, and the like commands, may also include read memory device status, read/set flash granule feature (feature), and the like commands, and may also include user-defined commands. The command queue 220 may be implemented by memory, a first-in-first-out memory register file, or the like.

When a command in the command queue 220 is processed, a micro instruction sequence corresponding to the command is obtained and executed by the micro instruction processor 210 to complete the processing of the command in the command queue 220. The conversion from commands in the process command queue 220 to a sequence of microinstructions may be accomplished by conversion circuitry (not shown). The conversion from commands in the process command queue 220 to micro instruction sequences may also be implemented by the micro instruction processor 210. In retrieving the microinstruction sequence, the microinstruction sequence may be stuffed or adapted based on the commands in the command queue 220 to conform the microinstruction sequence to the commands in the command queue 220.

For example, when the microinstruction processor 210 executes the microinstruction sequence 1, a new command from a user or an upper system is written into the command queue 220. Scheduling logic (not shown) may be provided to assist the microinstruction processor 210 in scheduling the microinstruction sequences. In response to the new command, the scheduling logic may halt execution of microinstruction sequence 1 and schedule a microinstruction sequence (e.g., microinstruction sequence 2) corresponding to the new command to be executed by the microinstruction processor. The execution state of the suspended microinstruction sequence 1 is saved so that when execution of the microinstruction sequence 1 is resumed, the execution state when suspended can be obtained. In one embodiment, the new command is a read command. The read command may have a higher priority and the scheduling logic pauses execution of the microinstruction sequence 1 in response to the new command based on the read command having the higher priority.

In one embodiment, the micro instruction sequence 1 is used to perform an erase operation on a flash granule. When the scheduling logic suspends execution of the microinstruction sequence 1, the scheduling logic also issues a command to the flash granule to suspend the flash granule erase operation. When the execution of the micro instruction sequence 2 is completed, the scheduling logic also issues a command to the flash granule to resume the flash granule erase operation. Then the execution state of the micro instruction sequence 1 when suspended is obtained, and the execution of the micro instruction sequence 1 is resumed.

In another embodiment, the micro instruction sequence 1 is used to perform a program operation on a flash granule. When the scheduling logic pauses execution of the microinstruction sequence 1, the scheduling logic also issues a command to the flash granule to pause a flash granule programming operation. When the execution of the micro instruction sequence 2 is completed, the scheduling logic also issues a command to the flash granule to resume the flash granule programming operation. Then the execution state of the micro instruction sequence 1 when suspended is obtained, and the execution of the micro instruction sequence 1 is resumed.

The scheduling logic may be implemented as software, hardware circuitry, and/or firmware, may be separate from the microinstruction processor 210, or may be integrated into the microinstruction processor 210.

In one embodiment, the microinstruction sequence 1 includes a yield microinstruction. When the micro instruction processor 210 executes the yield micro instruction, the execution state of the micro instruction sequence 1 is saved, and one of the micro instruction sequences is selected to be executed or restored. At this point, if there is a new command from the user or the upper system in the command queue 220, the new command corresponding to microinstruction sequence 2, the scheduling logic may execute microinstruction sequence 2 in response to the new command. The scheduling logic may also resume the micro instruction sequence 3 based on the presence of the micro instruction sequence 3 that has yielded or been stalled. In a further embodiment, after the micro instruction processor 210 executes the yield micro instruction of micro instruction sequence 1, the priorities of micro instruction sequence 1, micro instruction sequence 2, and/or micro instruction sequence 3 are compared, and a determination is made as to which micro instruction to execute next. In still further embodiments, the micro instruction sequence corresponding to the read operation has a higher priority than the micro instruction sequence corresponding to the erase operation. The micro instruction sequence corresponding to the read operation has a higher priority than the micro instruction sequence corresponding to the program operation.

In one embodiment, both the micro instruction sequence 1 and the micro instruction sequence 2 include yield micro instructions. For example, a yield micro instruction is included at the beginning of micro instruction sequence 1 and micro instruction sequence 2. When micro instruction sequence 1 is executed in response to a command in command queue 220, micro instruction sequence 1 yields with the execution of the yield micro instruction. At which point the dispatch logic determines which micro instruction sequence to execute next. If there is a new command in the command queue 220 corresponding to micro instruction sequence 2, the scheduling logic may schedule execution of micro instruction sequence 2. Since the beginning of the micro instruction sequence 2 includes a yield micro instruction, the micro instruction sequence 2 also yields. At this point, both micro instruction sequence 1 and micro instruction sequence 2 have yielded. The scheduling logic may select one of the micro instruction sequence 1 or the micro instruction sequence 2 to resume execution; the scheduling logic may also select to execute the microinstruction sequence n if a new command corresponding to another microinstruction sequence (e.g., microinstruction sequence n) is stored in the command queue 220. In a further embodiment, the scheduling logic determines which microinstruction sequence to execute based on the priority of the microinstruction sequence 1, the microinstruction sequence 2, and/or the microinstruction sequence n.

In yet another embodiment, the micro instruction sequence 1 and the micro instruction sequence 2 both include yield micro instructions. For example, a yield micro instruction is included at the beginning of micro instruction sequence 1 and micro instruction sequence 2. When micro instruction sequence 1 is executed in response to a command in command queue 220, micro instruction sequence 1 yields with the execution of the yield micro instruction. At which point the dispatch logic determines which micro instruction sequence to execute next. If there is a new command in the command queue 220 corresponding to micro instruction sequence 2, the scheduling logic may schedule execution of micro instruction sequence 2. Since the beginning of the micro instruction sequence 2 includes a yield micro instruction, the micro instruction sequence 2 also yields. At which point the dispatch logic determines which micro instruction sequence to execute next. The dispatch logic finds that both micro instruction sequence 1 and micro instruction sequence 2 have yielded. The scheduling logic may resume execution of the micro instruction sequence 1 on a first come first served basis. Next, the execution of the micro instruction sequence 1 causes the interface controller 230 to issue an erase operation to the flash memory granule. Further yield instructions may be included in the micro instruction sequence 1. The micro instruction sequence 1 yields again with the execution of the yield instruction. The dispatch logic again determines which sequence of micro instructions to execute next. Since the micro instruction sequence 1 corresponds to an erase operation and the micro instruction sequence 2 corresponds to a read operation, which is prioritized over the erase operation, the dispatch logic determines to resume execution of the micro instruction sequence 2. At this point, the scheduling logic also causes the interface controller 230 to issue an erase suspend command to the flash granule to suspend the erase command issued due to the micro instruction sequence 1, thereby allowing the flash granule to respond to subsequent read commands. Next in the course of executing the micro instruction sequence 2, the instruction processor 210 causes the interface controller to issue a read command to the flash granule. In a further embodiment, micro instruction sequence 2 execution completes when data returned by the flash granule is received. The dispatch logic again determines which sequence of micro instructions to execute next. Note that the micro instruction sequence 1 has yielded, and the dispatch logic determines to resume execution of the micro instruction sequence 1. To resume the micro instruction sequence 1, the scheduling logic also causes the interface controller 230 to issue a command to resume the erase operation to the flash granule, and then resume execution of the micro instruction sequence 1. In a similar manner as the micro instruction sequence 1 corresponding to the erase operation is executed, the scheduling logic may schedule the micro instruction sequence corresponding to the program operation. In one embodiment, commands from a user or an upper system in the command queue 220 provide priority information for the commands.

In another embodiment, the execution of the micro instruction sequence 1 causes the interface controller 230 to issue an erase operation to the flash granule. Further yield instructions may be included in the micro instruction sequence 1. The micro instruction sequence 1 yields again with the execution of the yield instruction. The scheduling logic starts a timer for the erase operation of the micro instruction sequence 1 to record the elapsed time after the erase operation is issued to the flash memory granule. Next, when micro instruction sequence 2 is desired to be executed in response to a command in command queue 220, the scheduling logic again determines which micro instruction sequence to execute next. In this embodiment, the micro instruction sequence 1 corresponds to an erase operation, and the micro instruction sequence 2 corresponds to a read operation, with the read operation having a higher priority than the erase operation. The scheduling logic further checks the timer. If the value of the timer is greater than the threshold, indicating that a significant amount of time has elapsed since the issuance of the previous flash granule erase command, it may be expected that the erase operation will complete soon. At this time, if an erase suspend command is issued to the flash memory granule to suspend the previous erase operation and a read command is issued, the improvement effect on the read operation delay is not obvious, and the execution delay of the previous erase operation is increased. In this case, the scheduling logic does not schedule execution of micro instruction sequence 2 and does not cause interface controller 230 to issue an erase suspend command to the flash granule. And if the value of the timer is not greater than or less than the threshold value, it indicates that the previous erase command needs to be executed for a longer time. In this case, if the read command is executed after waiting for the erase command to complete, the execution delay of the read operation experienced by the user will be significantly increased. The scheduling logic thus selects to schedule execution of the micro instruction sequence 2. And causes the interface controller 230 to issue an erase pause command to the flash granule, as well as a pause timer. The scheduling logic may also adjust the priority of the micro instruction sequence 1 and/or the micro instruction sequence 2. Then during execution of the micro instruction sequence 2, the micro instruction sequence 2 will cause the interface controller 230 to issue a read command to the flash granule. After the execution of the micro instruction sequence 2 is completed, or after the data specified by the read command is read from the flash memory granule, the scheduling logic causes the interface controller 230 to issue a command to resume the erase operation to the flash memory granule, and to resume the timer, so that the timer continues to count time. In further embodiments, in response to a desire to execute additional micro-instruction sequences, the scheduling logic again causes the interface controller 230 to issue an erase pause command to the flash granule and again stops the timer. In yet another embodiment, the micro instruction sequence 1 corresponds to a program operation and the micro instruction sequence 2 corresponds to a read operation.

Referring to FIG. 3, FIG. 3 shows a flowchart of a method of scheduling a micro instruction sequence according to an embodiment of the invention. The process flow of fig. 3 may be implemented by scheduling logic. The scheduling logic may be implemented as software, hardware circuitry, and/or firmware, either separate from the microinstruction processor 210 (see FIG. 2) or integrated into the microinstruction processor 210.

When a first command is received (310) from a user or an upper system through, for example, the command queue 220, the scheduling logic schedules execution of a first sequence of microinstructions corresponding to the first command (320). In one embodiment, the translation circuitry translates the first command into a first sequence of microinstructions based on the contents of the first command. Referring to FIG. 2, a sequence of micro-instructions may be stored in the micro-instruction memory 240 for selection by the translation circuit according to the contents of the first command. The microinstruction memory stores templates, which may also be sequences of microinstructions, and the translation circuitry populates the microinstruction sequence templates with the contents of the first command to obtain sequences of microinstructions that are executable by the microinstruction processor 210.

During execution of the first micro instruction sequence, a second command is received 330 from a user or an upper system via, for example, the command queue 220. The scheduling logic checks the execution status of the first micro instruction sequence and/or other micro instruction sequences (340). In one embodiment, the first micro instruction sequence is executing and may be halted. In yet another embodiment, the first micro instruction sequence is executing and may be suspended, with the second command corresponding to a higher priority than the first command. In yet another embodiment, the first micro instruction sequence has yielded, for example, by executing a yield micro instruction. The scheduling logic pauses the first micro instruction sequence (350). To suspend and resume the first micro instruction sequence, the scheduling logic also saves the execution state of the first micro instruction sequence. In one embodiment, the first micro instruction sequence issues a flash granule erase command. The scheduling logic also issues an erase pause command to the flash granule. Next, the scheduling logic schedules execution of a second sequence of microinstructions (360).

FIG. 4 is a block diagram of the components of a memory controller that process microinstructions according to another embodiment of the invention. The components provided in FIG. 4 to process microinstructions are similar to the components provided in FIG. 2, including a microinstruction processor 410, a command queue 420, an interface controller 430, and/or a microinstruction memory 440. The microinstruction memory 440 stores the microinstruction sequence 1 and the microinstruction sequence 2 … … microinstruction sequence n. In the embodiment of fig. 4, a status register 450, a register pool 460, and a scheduler 470 are also shown.

The status register 450 is coupled to the microinstruction processor 410 for saving and providing the execution status of the microinstruction sequences. The execution state of the micro instruction sequence includes a Program Counter (PC), general purpose registers (GR), physical address registers and/or timers, etc. The program counter is used to indicate the address of the currently executing microinstruction in the microinstruction sequence. The physical address register is used to indicate the address of the flash granule accessed by the micro instruction sequence.

The register pool 460 is used to store the execution state of the micro instruction sequence. The execution state of the microinstruction sequence held by the register pool 460 may include the contents of the status register 450. Within the register pool 460, the execution state of one or more microinstruction sequences 460 may be saved. The micro instruction sequence 460, with state information stored in the register pool 460, may be resumed for execution by the scheduler 470. The microinstruction processor 410 may resume execution of a sequence of microinstructions by restoring state information corresponding to the sequence of microinstructions stored in the register pool 460 into the state registers 450.

Scheduler 470 is coupled to microinstruction processor 410, command queue 420. The scheduler 470 may instruct the microinstruction processor 410 to suspend the microinstruction sequence being executed. The scheduler 470 may instruct the microinstruction processor 410 to resume execution of the microinstruction sequences. The scheduler 470 may also instruct the microinstruction processor 410 to begin a new execution of the microinstruction sequence. Scheduler 470 implements scheduling of the micro instruction sequences by storing state information (e.g., program counter values, general counter values, physical address register values, and/or timer values, etc.) corresponding to the micro instruction sequences in state registers 450.

Scheduler 470 may also be implemented as a sequence of microinstructions. In one embodiment, the execution of the microinstruction sequence is scheduled on the microinstruction processor 410 by periodically calling the microinstruction sequence corresponding to the scheduler 470 to check the execution status of the microinstruction sequence.

FIG. 5 is a timing diagram illustrating the processing of a scheduler and a microinstruction processor according to another embodiment of the present invention. In fig. 5, the arrow direction of the time axis shows the passage direction of time. The processing performed by the scheduler 570 is listed below the scheduler 570, and the processing performed by the microinstruction processor 510 is listed below the microinstruction processor 510.

In the embodiment of fig. 5, first, the scheduler 570 discovers or responds to the receipt of the first command (520). The scheduler schedules a first micro instruction sequence (522). As a result of scheduling the first micro instruction sequence, the microprocessor 510 begins executing the first micro instruction sequence (532). During execution (532) of the first micro instruction sequence, the scheduler discovers or responds to receipt (524) of the second command. Upon determination of the execution condition and/or the scheduling condition, the scheduler 570 suspends 526 instructing the microinstruction processor 510 to stall the first microinstruction sequence. In response, the microinstruction processor 510 stalls execution of the first microinstruction sequence. State information of the suspended first micro instruction sequence is saved. The scheduler schedules a second micro instruction sequence (528). As a result of scheduling the two micro instruction sequences, the microprocessor 510 begins executing the second micro instruction sequence (534). As processing proceeds, execution of the second micro instruction sequence is complete. Upon further determination of the execution condition and/or scheduling condition, scheduler 570 decides to schedule the first micro instruction sequence (530). The microinstruction processor 510 resumes execution of the first microinstruction sequence by restoring the state information of the previously saved large first microinstruction sequence (536).

FIG. 6 is a block diagram of the components of a memory controller that process microinstructions according to another embodiment of the invention. The components provided in FIG. 6 to process microinstructions are similar to the components provided in FIG. 6, including a microinstruction processor 610, a command queue 620, an interface controller 630, and/or a microinstruction memory 640. The micro instruction sequence is stored in the micro instruction memory 640. In the embodiment of FIG. 6, the micro instruction sequence stored in micro instruction memory 640 includes micro instructions that instruct interface controller 630 to issue one or more commands to the flash granule. For example, the micro instruction sequence stored in the micro instruction memory 640 includes an erase micro instruction, an erase suspend micro instruction, a read micro instruction, and an erase resume micro instruction. The erase micro instruction is used to instruct the interface controller 630 to issue an erase command to the flash memory granule. The erase suspend micro instruction is used to instruct the interface controller 630 to issue an erase suspend command to the flash granule. The read micro instruction is used to instruct the interface controller 630 to issue a read command to the flash granule. The erase recovery micro instruction is used to instruct the interface controller 630 to issue an erase recovery command to the flash granule. In another embodiment, the micro instruction sequences stored in the micro instruction memory 640 further include a program suspend micro instruction, and/or a program resume micro instruction. The program suspend micro-instruction is used to instruct the interface controller 630 to issue a program suspend command to the flash granule, and the program resume micro-instruction is used to instruct the interface controller 630 to issue a program resume command to the flash granule.

FIG. 7 is a flowchart of a method of executing a micro instruction sequence 710 according to an embodiment of the invention. In fig. 7, the direction of the time axis arrow shows the passage direction of time. In one embodiment, the first command indicates a flash granule erase operation. The first command 720 is processed by executing the micro instruction sequence 710. The first command may be retrieved from command queue 620 (see FIG. 6). Those skilled in the art will recognize that there are other ways to obtain the first command. An erase command 730 is issued to the flash granule by executing the micro instructions in the micro instruction sequence 710. The second command 740 is fetched and processed by executing the microinstructions in the microinstruction sequence 710. For example, by executing the microinstructions in the microinstruction sequence 710, the microinstruction sequence 710 checks the command queue 620 (see FIG. 6) for receipt of a second command, which is processed after it is received. Next, the micro instruction sequence 710 determines to suspend a previously issued erase command by executing the micro instructions in the micro instruction sequence 710, whereupon an erase suspend command 750 is issued to the flash granule. For example, by executing the microinstructions in the microinstruction sequence 710, the microinstruction sequence 710 determines whether to suspend a previously issued erase command by comparing the priority of the first command to the priority of the second command. In another example, the determination to suspend an erase command or a write command issued in a forward direction to the flash memory granule is based on a first command corresponding to an erase, program, or write operation and a second command corresponding to a read operation. Next, a read command 760 is issued to the flash granule by executing the micro-instructions in the micro-instruction sequence 710.

FIG. 8 is a flowchart illustrating a method for executing the first micro instruction sequence 810 according to another embodiment of the present invention. In fig. 8, the direction of the time axis arrow shows the direction of the passage of time.

In one embodiment, the first command indicates a flash granule erase operation. The first command 820 is processed by executing the first micro instruction sequence 810. The first command may be retrieved from command queue 620 (see FIG. 6). Those skilled in the art will recognize that there are other ways to obtain the first command. An erase command 830 is issued to the flash granule by executing the micro instructions in the first micro instruction sequence 810. Subsequently, the yield microinstruction in the first microinstruction sequence 810 is executed to yield 835 the first microinstruction sequence 810. After the first micro instruction sequence 810 yields, the micro instruction processor 610 (see FIG. 6) may execute the micro instructions 837 of the other micro instruction sequences 815. In one example, the sequence of microinstructions that the microinstruction processor 610 next executes is selected by a scheduler or scheduling logic. In another example, the scheduler or scheduling logic chooses to resume execution of the first micro instruction sequence 810 because there are no other micro instruction sequences waiting to be executed or the priority of the first micro instruction sequence 810 is higher. Yield microinstructions are also included in the other microinstruction sequence 815. The other micro instruction sequence 815 yields 839 by executing a yield micro instruction in the other micro instruction sequence 815. As the other micro instruction sequence 815 yields, the microprocessor 610 may execute another micro instruction sequence. In one example, the scheduler or scheduling logic selects to resume execution of the first micro instruction sequence 810. The microinstruction processor 610 continues to execute the first microinstruction sequence 810 by restoring the execution state (e.g., program counter value, general counter value, physical address register value, and/or timer value, etc.) at the time the first microinstruction sequence 810 yields.

Next, a second command 840 is fetched and processed by executing the microinstructions in the first sequence of microinstructions 810. For example, by executing the microinstructions in the first microinstruction sequence 810, the microinstruction sequence 810 checks whether the command queue 620 (see FIG. 6) receives a second command, which is processed after it is received. Next, by executing the microinstructions in the sequence of microinstructions 810, the first sequence of microinstructions 810 determines that a previously issued erase command is to be suspended, whereupon an erase suspend command 850 is issued to the flash memory granule. For example, by executing a microinstruction in the first microinstruction sequence 810, the microinstruction sequence 810 determines whether to suspend a previously issued erase command by comparing the priority of the first command to the priority of the second command. In another example, the determination to suspend an erase command or a program command issued in a forward direction to the flash memory granule is based on a first command corresponding to an erase, program, or write operation and a second command corresponding to a read operation. Next, a read command 860 is issued to the flash granule by executing the micro instructions in the first micro instruction sequence 810.

FIG. 9 is a flowchart illustrating a method for executing a micro instruction sequence according to yet another embodiment of the invention. In fig. 8, the direction of the time axis arrow shows the direction of the passage of time.

In one embodiment, the first command indicates a flash granule erase operation. The first command 920 is processed by executing the first micro instruction sequence 910. The first command may be retrieved from command queue 620 (see FIG. 6). Those skilled in the art will recognize that there are other ways to obtain the first command. An erase command 930 is issued to the flash granule by executing a microinstruction of the first sequence of microinstructions 910. Subsequently, the yield microinstruction in the first microinstruction sequence 910 is executed to yield 935 the first microinstruction sequence 910. In a further embodiment, the execution state (e.g., program counter value, general counter value, physical address register value, and/or timer value, etc.) of the first micro instruction sequence 910 is saved upon yield. After the first micro instruction sequence 910 yields, the micro instruction processor 610 (see FIG. 6) may execute the micro instructions 937 in the other micro instruction sequences 915. In one example, the sequence of microinstructions that the microinstruction processor 610 next executes is selected by a scheduler or scheduling logic. In another example, the scheduler or scheduling logic may choose to resume execution of the first micro instruction sequence 910 because there are no other micro instruction sequences waiting to be executed or the priority of the first micro instruction sequence 910 is higher.

Yield microinstructions are also included in the other microinstruction sequence 915. The other microinstruction sequence 915 yields 939 by executing the yielding microinstruction in the other microinstruction sequence 915. As the other micro instruction sequence 915 yields, the microprocessor 610 may execute another micro instruction sequence. In one example, the scheduler or scheduling logic selects to resume execution of the first sequence of microinstructions 910. The microinstruction processor 610 continues to execute the first microinstruction sequence 910 by restoring the execution state (e.g., program counter value, general counter value, physical address register value, and/or timer value, etc.) at the time the first microinstruction sequence 910 yields.

Next, a second command 940 is fetched and processed by executing the microinstructions in the first microinstruction sequence 910. For example, by executing the microinstructions in the first microinstruction sequence 910, the microinstruction sequence 910 checks whether the command queue 620 (see FIG. 6) receives a second command, which is processed after it is received. Next, by executing the microinstructions in the microinstruction sequence 910, the first microinstruction sequence 910 determines that the previously issued erase command is to be paused, whereupon an erase pause command 950 is issued to the flash granule. For example, by executing microinstructions in the first microinstruction sequence 910, the microinstruction sequence 910 determines whether to suspend a previously issued erase command by comparing the priority of the first command to the priority of the second command. In another example, the determination to suspend an erase command or a program command issued in a forward direction to the flash memory granule is based on a first command corresponding to an erase, program, or write operation and a second command corresponding to a read operation. In yet another example, a timer is started by the first micro instruction sequence 910 before or after the step 930 of issuing an erase command is performed. While the value of the timer is also referenced when the first micro instruction sequence 910 determines whether a previously issued erase command is to be paused. If the value of the timer is greater than the threshold, indicating that a significant amount of time has elapsed since the issuance of the previous flash granule erase command, it may be expected that the erase operation will complete soon. At this time, if an erase suspend command is issued to the flash memory granule to suspend the previous erase operation and a read command is issued, the improvement effect on the read operation delay is not obvious, and the execution delay of the previous erase operation is increased. In this case, the micro instruction sequence 910 does not issue an erase pause command to the flash granule. And if the value of the timer is not greater than or less than the threshold value, it indicates that the previous erase command needs to be executed for a longer time. In this case, if the read command is executed after waiting for the erase command to complete, the execution delay of the read operation experienced by the user will be significantly increased. Thus, an erase pause command 950 is issued to the flash granule by a micro instruction in the micro instruction sequence 910. The first microinstruction sequence 910 also then causes the timer to pause.

Next, a read command 960 is issued to the flash granule by executing the microinstructions in the first sequence of microinstructions 910. By executing the microinstructions in the first sequence of microinstructions 910, it is checked 970 whether the read command is complete. For example, in response to obtaining data corresponding to the read command from the flash granule, it is determined that the read command execution is complete. If the read command execution is complete, an erase recovery command 980 is issued to the flash granule. In a further embodiment, the timer is restored to continue counting. If the read command has not been completed, the first micro instruction sequence 910 yields 972. In a further embodiment, the execution state (e.g., program counter value, general counter value, physical address register value, and/or timer value, etc.) of the first micro instruction sequence 910 is saved upon yield. After the first micro instruction sequence 910 yields, the micro instruction processor 610 (see FIG. 6) may execute the micro instructions 974 in the other micro instruction sequence 915. In one example, the sequence of microinstructions (e.g., other microinstruction sequence 915) that is next executed by the microinstruction processor 610 is selected by a scheduler or scheduling logic. In another example, the scheduler or scheduling logic may choose to resume execution of the first micro instruction sequence 910 because there are no other micro instruction sequences waiting to be executed or the priority of the first micro instruction sequence 910 is higher.

In other microinstruction sequences 915, yield microinstructions may also be included. The other microinstruction sequence 915 yields 976 by executing the yield microinstruction in the other microinstruction sequence 915. Upon yield of the other micro instruction sequence 915, its execution state (e.g., program counter value, general counter value, physical address register value, and/or timer value, etc.) is saved. After the other micro instruction sequence 915 yields, the micro instruction processor 610 (see FIG. 6) may select to execute the micro instructions in the first micro instruction sequence 910 or the other micro instruction sequence 915. In one example, the sequence of microinstructions that the microinstruction processor 610 next executes is selected by a scheduler or scheduling logic. In another example, the scheduler or scheduling logic may choose to resume execution of the first micro instruction sequence 910 because the first micro instruction sequence 910 is waiting to be executed and/or the first micro instruction sequence 910 may be prioritized.

Next, by executing the microinstructions in the first microinstruction sequence 910, it is checked 990 whether the erase command is complete. The erase command is the erase command issued to the flash granule in step 930. If the erase command execution is complete, then the execution of the first sequence of micro instructions 910 is complete 998. If the erase command has not been completed, the first micro instruction sequence 910 yields 992. After the first micro instruction sequence 910 yields, the micro instruction processor 610 (see FIG. 6) may execute the micro instructions 994 in the other micro instruction sequence 915. In other micro instruction sequences, yield micro instructions may also be included. The other microinstruction sequence 915 yields 996 by executing the yield microinstruction in the other microinstruction sequence 915. After the other micro instruction sequence 915 yields, the micro instruction processor 610 (see FIG. 6) may select to execute the micro instructions in the first micro instruction sequence 910 or the other micro instruction sequence 915.

Next, when the first sequence of microinstructions 910 is resumed execution again, it is checked whether a new command is received by the command queue 620. Upon receiving a new command, the first microinstruction sequence 910 again determines whether to suspend a previously issued erase command by executing the microinstructions in the microinstruction sequence 910. In a further embodiment, the micro instruction sequence 910 again checks the timer and determines to again suspend the previously issued erase command if the timer is not greater than or less than the threshold and the second command corresponds to a flash granule read operation. In another embodiment, the microinstruction sequence 910 compares the priority of the first command with the priority of the new command. If the new command has a higher priority than the first command, it is determined that the previously issued erase command is to be suspended again. In still another example, the priority of the first command, the second command, and/or the new command is adjusted over time or depending on the value of a timer. In yet another example, the priority of the commands is provided when the user or upper system issues the first command, the second command, and/or the new command. In still another example, a user or an upper system may adjust the priority of the commands.

The new command may be processed using step 940 of processing the second command and subsequent steps. And may also issue erase suspend and/or erase resume commands to the flash granule again.

By providing a micro-instruction sequence execution mechanism and micro-instructions such as yield, erase pause, erase resume and the like, the capability of controlling the sending opportunity of the pause command is provided for the user of the storage device. A user of the storage device is enabled to participate in flexible control of the timing of issuance of the flash suspend command, rather than relying on the storage controller to enforce scheduling of multiple commands to access the flash granule. A user of the storage device can participate in the flexible control of the timing of issuance of the flash suspend command by programming, updating, and/or modifying the micro instruction sequence.

Various embodiments of the present invention are disclosed above with flash memory pellets as an example. Those skilled in the art will recognize that embodiments of the present invention may also be applied to other types of storage media that support erase suspend and/or erase resume commands, such as phase change memory, resistive memory, ferroelectric memory, and the like.

The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art.