Clock tree robustness detection method and device based on library unit
阅读说明：本技术 一种基于库单元的时钟树健壮度检测方法及装置 (Clock tree robustness detection method and device based on library unit ) 是由 王锐 刘一杰 莫军 李建军 王亚波 于 2020-07-03 设计创作，主要内容包括：本发明公开了一种基于库单元的时钟树健壮度检测方法及装置,包括：扫描待检测时钟树的工艺库单元,选取满足第一预设条件的特定时钟树单元；扫描特定时钟树单元,检测所有特定时钟树单元是否满足第二预设条件的特定阈值电压单元；在检测到所有特定时钟树单元中存在不满足第二预设条件的特定阈值电压单元时,判断待检测时钟树的健壮度较低；在检测到所有特定时钟树单元均满足第二预设条件的特定阈值电压单元时,判断待检测时钟树的健壮度较高。本发明实施例准确得到时钟树健壮度的检测结果。(The invention discloses a clock tree robustness detection method and a device based on library units, wherein the method comprises the following steps: scanning a process library unit of a clock tree to be detected, and selecting a specific clock tree unit meeting a first preset condition; scanning the specific clock tree units, and detecting whether all the specific clock tree units meet the specific threshold voltage unit of a second preset condition; when detecting that a specific threshold voltage unit which does not meet a second preset condition exists in all specific clock tree units, judging that the robustness of the clock tree to be detected is low; and when all the specific clock tree units are detected to meet the specific threshold voltage unit of the second preset condition, judging that the robustness of the clock tree to be detected is higher. The embodiment of the invention can accurately obtain the detection result of the clock tree robustness.)
1. A clock tree robustness detection method based on library units is characterized by comprising the following steps:
Scanning a process library unit of a clock tree to be detected, and selecting a specific clock tree unit meeting a first preset condition;
scanning the specific clock tree units, and detecting whether all the specific clock tree units meet specific threshold voltage units of a second preset condition;
when detecting that a specific threshold voltage unit which does not meet the second preset condition exists in all the specific clock tree units, judging that the robustness of the clock tree to be detected is low;
and when all the specific clock tree units are detected to meet the specific threshold voltage unit of the second preset condition, judging that the robustness of the clock tree to be detected is higher.
2. The library-unit-based clock tree robustness testing method of claim 1, wherein after judging that the robustness of the clock tree to be tested is low, the specific threshold voltage unit not satisfying the second preset condition is replaced with a clock tree unit satisfying both the first preset condition and the second preset condition.
3. The library-unit-based clock tree robustness detection method of any one of claims 1-2, wherein the first preset condition is that a specific position in a clock tree unit name is a specific pattern; the second preset condition is that a specific position in the clock tree unit name is a specific style.
4. The library-unit-based clock tree robustness detection method of claim 3, wherein the first preset condition is a prefix name of CLK in a clock tree unit name; the second preset condition is that the suffix name in the clock tree unit name is CLK.
5. A clock tree robustness detection device based on library units is characterized by comprising:
the selecting module is used for scanning the process library unit of the clock tree to be detected and selecting a specific clock tree unit meeting a first preset condition;
the detection module is used for scanning the specific clock tree units and detecting whether all the specific clock tree units meet specific threshold voltage units of a second preset condition;
the first judging module is used for judging that the robustness of the clock tree to be detected is low when detecting that a specific threshold voltage unit which does not meet the second preset condition exists in all the specific clock tree units;
and the second judging module is used for judging that the robustness of the clock tree to be detected is higher when all the specific clock tree units meet the specific threshold voltage unit of the second preset condition.
6. The library-unit-based clock tree robustness detection apparatus of claim 5, further comprising: and the replacing module is used for replacing the specific threshold voltage unit with a clock tree unit which simultaneously meets the first preset condition and the second preset condition after judging that the robustness of the clock tree to be detected is low.
7. The library-unit-based clock tree robustness detection apparatus of claim 6, wherein the first preset condition is that a specific position in a clock tree unit name is a specific pattern; the second preset condition is that a specific position in the clock tree unit name is a specific style.
8. The library-unit-based clock tree robustness detection apparatus of claim 6, wherein the first predetermined condition is a prefix name of CLK in a clock tree unit name; the second preset condition is that the suffix name in the clock tree unit name is CLK.
Technical Field
The invention relates to the technical field of chip design, in particular to a clock tree robustness detection method and device based on library units.
Background
At present, the integrated circuit is developed vigorously, and along with the higher and higher integration level of the chip, the chip area is larger and larger, and the time sequence convergence of the chip is more and more difficult. The establishment of a heavily stressed clock tree for timing convergence is also the subject of intensive research and development in the industry. Major electronic design automation tool vendors have developed many algorithms for clock trees to improve and upgrade the quality of the clock trees. But the clock tree setup requirements and implementations are still diverse in different process and chip application directions and are of great relevance to the thoughts and experiences of the engineers using the tools. Therefore, the detection of the clock tree quality is very important. The inventor of the present invention finds, in research, that the robustness of the clock tree is ensured by using the related implementation in the clock tree establishment process in the prior art as a basis, but the robustness of the clock tree cannot be ensured due to the absence of any detection mechanism after the clock tree is established in the prior art, and the timing convergence efficiency of the chip is poor.
Disclosure of Invention
The invention provides a clock tree robustness detection method and device based on a library unit, and aims to solve the technical problem that the prior art cannot guarantee the robustness of a clock tree to be detected, so that the timing sequence convergence efficiency of a chip is poor.
The first embodiment of the present invention provides a clock tree robustness detection method based on library units, which includes:
scanning a process library unit of a clock tree to be detected, and selecting a specific clock tree unit meeting a first preset condition;
scanning the specific clock tree units, and detecting whether all the specific clock tree units meet specific threshold voltage units of a second preset condition;
when detecting that a specific threshold voltage unit which does not meet the second preset condition exists in all the specific clock tree units, judging that the robustness of the clock tree to be detected is low;
and when all the specific clock tree units are detected to meet the specific threshold voltage unit of the second preset condition, judging that the robustness of the clock tree to be detected is higher.
Further, after the robustness of the clock tree to be detected is judged to be low, the specific threshold voltage unit which does not meet the second preset condition is replaced by a clock tree unit which meets the first preset condition and the second preset condition at the same time.
Further, the first preset condition is that a specific position in the clock tree unit name is a specific style; the second preset condition is that a specific position in the clock tree unit name is a specific style.
Further, the first preset condition is that a prefix name in the clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK.
Another embodiment of the present invention provides a clock tree robustness detection apparatus based on library units, including:
the selecting module is used for scanning the process library unit of the clock tree to be detected and selecting a specific clock tree unit meeting a first preset condition;
the detection module is used for scanning the specific clock tree units and detecting whether all the specific clock tree units meet specific threshold voltage units of a second preset condition;
the first judging module is used for judging that the robustness of the clock tree to be detected is low when detecting that a specific threshold voltage unit which does not meet the second preset condition exists in all the specific clock tree units;
and the second judging module is used for judging that the robustness of the clock tree to be detected is higher when all the specific clock tree units meet the specific threshold voltage unit of the second preset condition.
Further, the detection device further comprises: and the replacing module is used for replacing the specific threshold voltage unit with a clock tree unit which simultaneously meets the first preset condition and the second preset condition after judging that the robustness of the clock tree to be detected is low.
Further, the first preset condition is that a specific position in the clock tree unit name is a specific style; the second preset condition is that a specific position in the clock tree unit name is a specific style.
Further, the first preset condition is that a prefix name in the clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK.
According to the embodiment of the invention, the specific clock tree units meeting the first preset condition are scanned, whether the specific threshold voltage units which do not meet the second preset condition exist in all the clock tree units is detected according to the characteristics of the clock tree, and when the specific threshold voltage units which do not meet the second preset condition exist, the robustness of the clock tree to be detected is judged to be low, so that the robustness of the clock tree can be accurately detected, and the efficiency of chip time sequence convergence is favorably improved.
Drawings
FIG. 1 is a flowchart illustrating a clock tree robustness detection method based on library units according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a clock tree robustness detecting apparatus based on library units according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, a first embodiment of the present invention is shown in fig. 1, which illustrates a clock tree robustness detection method based on library units, including:
s1, scanning the process library unit of the clock tree to be detected, and selecting a specific clock tree unit meeting a first preset condition;
it should be noted that the robustness of the clock tree is understood as: the clock period and the degree of recovery of the waveform are maintained as the clock propagates through the clock tree. In an ideal case, the clock waveform is a square wave, and the duty ratio of the high level and the low level in the waveform is 50%: 50 percent. In order to improve the balance of clock propagation on rising and falling edges, a specific clock tree unit satisfying a first preset condition is set according to the characteristics of the clock tree. According to the embodiment of the invention, the specific clock tree unit meeting the first preset condition can be accurately selected by scanning the process library unit document and the model file of the clock tree to be detected, so that the replacement of the clock tree threshold voltage unit is realized, and the robustness of the clock tree is improved.
S2, scanning the specific clock tree units, and detecting whether all the specific clock tree units meet the specific threshold voltage unit of a second preset condition;
S3, when detecting that the specific clock tree units have specific threshold voltage units which do not meet the second preset condition, judging that the robustness of the clock tree to be detected is low;
and S4, when all the specific clock tree units are detected to meet the specific threshold voltage unit of the second preset condition, judging that the robustness of the clock tree to be detected is higher.
According to the embodiment of the invention, the specific clock tree units meeting the first preset condition are scanned, whether the specific threshold voltage units which do not meet the second preset condition exist in all the clock tree units is detected according to the characteristics of the clock tree, and when the specific threshold voltage units which do not meet the second preset condition exist, the robustness of the clock tree to be detected is judged to be low, so that the robustness of the clock tree can be accurately detected, and the efficiency of chip time sequence convergence is favorably improved.
As a specific implementation manner of the embodiment of the present invention, after the robustness of the clock tree to be detected is determined to be low, the specific threshold voltage unit that does not satisfy the second preset condition is replaced with a clock tree unit that satisfies both the first preset condition and the second preset condition.
In the embodiment of the invention, all the specific clock units are scanned, the specific threshold voltage unit which does not meet the second preset condition is selected, and the specific threshold voltage unit is replaced by the clock tree unit which simultaneously meets the first preset condition and the second preset condition, so that the clock tree uses the uniform threshold voltage unit, the propagation speeds of the rising edge and the falling edge of the clock are basically consistent when the clock propagates on the clock tree, and the robustness of the clock tree is improved.
As a specific implementation manner of the embodiment of the present invention, the first preset condition is that a specific position in the clock tree unit name is a specific style; the second preset condition is that the specific position in the clock tree unit name is a specific pattern.
As a specific implementation manner of the embodiment of the present invention, the specific threshold voltage unit satisfying the first preset condition and the second preset condition is a low voltage threshold voltage unit. According to the embodiment of the invention, the threshold voltage units are uniformly replaced by the low-voltage threshold voltage units, the OCV change of the clock is small when the clock is transmitted by the low-voltage threshold voltage units of the clock tree, and the delay difference of the whole clock tree is favorably reduced, so that the area and power consumption expenditure in the time sequence convergence process are favorably reduced, and the robustness of the clock tree is improved.
As a specific implementation manner of the embodiment of the present invention, the first preset condition is that a prefix name in a clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK.
The first preset condition includes: one or more of prefix name CLK, prefix name CK and prefix name S; the second preset condition includes: one or more of a suffix name CLK, a suffix name RVT, and a suffix name STN. Optionally, the first preset condition in the embodiment of the present invention is that a prefix name in a clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK, and the specific threshold voltage unit satisfying the first preset condition and the second preset condition in the embodiment of the present invention is a low-voltage threshold voltage unit.
As a specific implementation manner of the embodiment of the present invention, after capturing threshold voltage cells with suffix name not × _ LVT, BUFX8_ RVT replaces these threshold voltage cells with program scripts:
Error：CTS cell clkgen/U1 using BUF8X_RVT,not CLK*&*_LVT cell；
size_cell clkgen/U1 CLKBUFX8_LVT；
Error：CTS cell clkdiv/U2 using MUX2X2_HVT,not CLK*&*_LVT cell；
size_cell clkdiv/U2 CLKMUX2X2_LVT。
the embodiment of the invention has the following beneficial effects:
according to the embodiment of the invention, the specific clock tree units meeting the first preset condition are scanned, whether the specific threshold voltage units which do not meet the second preset condition exist in all the clock tree units is detected according to the characteristics of the clock tree, and when the specific threshold voltage units which do not meet the second preset condition exist, the robustness of the clock tree to be detected is judged to be low, so that the robustness of the clock tree can be accurately detected, and the efficiency of chip time sequence convergence is favorably improved.
Further, in the embodiment of the present invention, the threshold units used in the clock tree are replaced with the low-voltage threshold voltage units according to the preset replacement rule, so that the threshold voltage units used in the clock tree are unified into the same threshold voltage power supply, when the characteristics of the clock tree propagate among the same type of threshold voltage units, the characteristics of the clock can be well described by the units, the propagation speeds of the rising edge and the falling edge of the library unit are substantially the same, and the duty ratio of the high level and the low level tends to 50%: 50%, the balance of the propagation of the rising edge and the falling edge is kept, and the robustness of the clock waveform is ensured; and the low-voltage threshold voltage unit has small variation in OCV, so that the delay difference of the whole clock tree is favorably reduced, and the area and the power consumption expenditure in the time sequence convergence process are favorably reduced.
Referring to fig. 2, a second embodiment of the present invention, fig. 2 shows a clock tree robustness detecting apparatus based on library units, including:
the
it should be noted that the robustness of the clock tree is understood as: the clock period and the degree of recovery of the waveform are maintained as the clock propagates through the clock tree. In an ideal case, the clock waveform is a square wave, and the duty ratio of the high level and the low level in the waveform is 50%: 50 percent. In order to improve the balance of clock propagation on rising and falling edges, a specific clock tree unit satisfying a first preset condition is set according to the characteristics of the clock tree. According to the embodiment of the invention, the specific clock tree unit meeting the first preset condition can be accurately selected by scanning the process library unit document and the model file of the clock tree to be detected, so that the replacement of the clock tree threshold voltage unit is realized, and the robustness of the clock tree is improved.
A detecting
The first judging
the second determining
In the embodiment of the present invention, the
As a specific implementation manner of the embodiment of the present invention, the replacing module is configured to replace the specific threshold voltage unit with a clock tree unit that satisfies the first preset condition and the second preset condition at the same time after the robustness of the clock tree to be detected is determined to be low.
In the embodiment of the invention, the detection is that all the specific clock units are scanned, the specific threshold voltage unit which does not meet the second preset condition is selected, the module is replaced and replaced by the clock tree unit which simultaneously meets the first preset condition and the second preset condition, so that the clock tree uses the uniform threshold voltage unit, the propagation speeds of the rising edge and the falling edge of the clock are kept basically consistent when the clock propagates on the clock tree, and the robustness of the clock tree is improved.
As a specific implementation manner of the embodiment of the present invention, the first preset condition is that a specific position in the clock tree unit name is a specific style; the second preset condition is that the specific position in the clock tree unit name is a specific pattern.
As a specific implementation manner of the embodiment of the present invention, the specific threshold voltage unit satisfying the first preset condition and the second preset condition is a low voltage threshold voltage unit. According to the embodiment of the invention, the threshold voltage units are uniformly replaced by the low-voltage threshold voltage units, the OCV change of the clock is small when the clock is transmitted by the low-voltage threshold voltage units of the clock tree, and the delay difference of the whole clock tree is favorably reduced, so that the area and power consumption expenditure in the time sequence convergence process are favorably reduced, and the robustness of the clock tree is improved.
As a specific implementation manner of the embodiment of the present invention, the first preset condition is that a prefix name in a clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK.
The first preset condition includes: one or more of prefix name CLK, prefix name CK and prefix name S; the second preset condition includes: one or more of a suffix name CLK, a suffix name RVT, and a suffix name STN. Optionally, the first preset condition in the embodiment of the present invention is that a prefix name in a clock tree unit name is CLK; the second preset condition is that the suffix name in the clock tree unit name is CLK, and the specific threshold voltage unit satisfying the first preset condition and the second preset condition in the embodiment of the present invention is a low-voltage threshold voltage unit.
As a specific implementation manner of the embodiment of the present invention, after capturing threshold voltage cells with suffix name not × _ LVT, BUFX8_ RVT replaces these threshold voltage cells with program scripts:
Error：CTS cell clkgen/U1 using BUF8X_RVT,not CLK*&*_LVT cell；
size_cell clkgen/U1 CLKBUFX8_LVT；
Error：CTS cell clkdiv/U2 using MUX2X2_HVT,not CLK*&*_LVT cell；
size_cell clkdiv/U2 CLKMUX2X2_LVT。
the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the
Further, the replacement module in the embodiment of the present invention replaces the threshold units used in the clock tree with the low-voltage threshold voltage units according to the preset replacement rule, so that the threshold voltage units used in the clock tree are unified into the same threshold voltage power supply, when the characteristics of the clock tree are propagated among the threshold voltage units of the same type, the characteristics of the clock can be well described by the units, the propagation speeds of the rising edge and the falling edge of the library unit are substantially the same, and the duty ratio of the high level and the low level tends to 50%: 50%, the balance of the propagation of the rising edge and the falling edge is kept, and the robustness of the clock waveform is ensured; and the low-voltage threshold voltage unit has small variation in OCV, so that the delay difference of the whole clock tree is favorably reduced, and the area and the power consumption expenditure in the time sequence convergence process are favorably reduced.
The foregoing is a preferred embodiment of the present invention, and it should be noted that it would be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the principles of the invention, and such modifications and enhancements are also considered to be within the scope of the invention.
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