Method and apparatus for driving word lines in a memory
阅读说明：本技术 用于驱动存储器中的字线的方法和装置 (Method and apparatus for driving word lines in a memory ) 是由 C·L·英戈尔斯 T·H·金 于 2020-02-27 设计创作，主要内容包括：本申请涉及一种用于驱动存储器装置中的字线的方法和装置。一种子字线电路,其具有相位驱动器电路,所述相位驱动器电路用于提供第一相位信号和第二相位信号。所述子字线电路包含子字线驱动器电路,所述子字线驱动器电路具有上拉电路,所述上拉电路被配置成接收所述第一相位信号和全局字线信号。所述上拉电路被进一步配置成当所述第一相位信号处于第一值时驱动局部字线跟随所述全局字线信号并且当所述第一相位信号处于第二值时将所述局部字线与所述全局字线信号隔离。所述子字线电路还包含处理装置,所述处理装置在所述全局字线信号进入有效状态之前将所述第一相位信号设置为第一值,并且仅在所述全局字线信号已经进入预充电状态之后才将所述第一相位信号设置为所述第二值。(The present application relates to a method and apparatus for driving a word line in a memory device. A sub-wordline circuit has a phase driver circuit for providing a first phase signal and a second phase signal. The sub-wordline circuit includes a sub-wordline driver circuit having a pull-up circuit configured to receive the first phase signal and a global wordline signal. The pull-up circuit is further configured to drive a local wordline to follow the global wordline signal when the first phase signal is at a first value and to isolate the local wordline from the global wordline signal when the first phase signal is at a second value. The sub-wordline circuit also includes a processing device that sets the first phase signal to a first value before the global wordline signal enters an active state and sets the first phase signal to the second value only after the global wordline signal has entered a pre-charge state.)
1. A sub-word line circuit for a memory device, comprising:
a phase driver circuit configured to provide a first phase signal and a second phase signal;
a sub-word line driver circuit, the sub-word line driver circuit comprising:
a pull-up circuit configured to receive the first phase signal and a global word line signal, the pull-up circuit further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and to isolate the local word line from the global word line signal when the first phase signal is at a second value; and
a processing device operably coupled to the phase driver circuit, the processing device configured to:
setting the first phase signal to the first value before the global word line signal enters an active state; and is
Setting the first phase signal to the second value only after the global word line signal has entered a precharge state.
2. The sub-wordline circuit of claim 1, wherein the sub-wordline driver includes a pull-down circuit configured to receive the second phase signal and a low voltage signal, the pull-down circuit further configured to drive the local wordline to follow the low voltage signal when the second phase signal is at a third value and to isolate the local wordline from the low voltage signal when the second phase signal is at a fourth value, and
Wherein the processing means sets the second phase signal to the third value while the first phase signal is set to the first value and sets the second phase signal to the fourth value while or after the first phase signal is set to the second value.
3. The sub-wordline circuit of claim 2, wherein the sub-wordline driver includes only NMOS type transistors.
4. The sub-wordline circuit of claim 3, wherein the pull-up circuit is a first NMOS transistor having a gate connected to a first output line of the phaser driver circuit that carries the first phase signal, a source connected to a global wordline that carries the global wordline signal, and a drain connected to the local wordline,
wherein the pull-down circuit is a second NMOS transistor having a gate connected to a second output line of the phase driver circuit that carries the second phase signal, a source connected to a voltage source that provides the low voltage signal, and a drain connected to the local word line.
5. The sub-wordline circuit of claim 1, wherein the first value of the first phase signal is higher in voltage than a value of the global wordline in the active state by at least a threshold of a transistor in the pull-up circuit.
6. The sub-wordline circuit of claim 5, wherein the first value is in a range of 4.2 volts to 4.5 volts.
7. The sub-wordline circuit of claim 2, wherein the low voltage signal is-0.2 volts.
8. A method, comprising:
generating a first phase signal and a second phase signal in a memory device;
driving a local wordline of the memory device to follow a global wordline signal by setting the first phase signal to be at a first value before the global wordline signal enters an active state; and
isolating the local wordline from the global wordline signal by setting the first phase signal to be at the second value only after the global wordline signal has entered a pre-charge state.
9. The method of claim 8, further comprising:
driving the local word line to follow a low voltage signal by setting the second phase signal at a third value while the first phase signal is set to the first value; and
isolating the local word line from the low voltage signal by setting the second phase signal at a fourth value at the same time or after the first phase signal is set to the second value.
10. The method of claim 9, wherein the driving of the local word line is performed by a sub-word line driver including only NMOS type transistors.
11. The method of claim 10, wherein the sub-wordline driver includes a first NMOS transistor having a gate that receives the first phase signal, a source that receives the global wordline signal, and a drain connected to the local wordline,
wherein the sub-word line driver further includes a second NMOS transistor having a gate receiving the second phase signal, a source receiving a low voltage signal, and a drain connected to the local word line.
12. The method of claim 8, wherein the first value of the first phase signal is higher in voltage than a value of the global word line in the active state at least to perform the driving of the local word line to follow a threshold voltage of a transistor of the global word line signal.
13. The method of claim 12, wherein the first value is in a range of 4.2 volts to 4.5 volts.
14. The method of claim 10, wherein the low voltage signal is-0.2 volts.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
generating a first phase signal and a second phase signal in a memory device;
driving a local wordline of the memory device to follow a global wordline signal by setting the first phase signal to be at a first value before the global wordline signal enters an active state; and is
Setting the first phase signal to be at a second value to isolate the local wordline from the global wordline signal only after the global wordline signal has entered a precharge state.
16. The non-transitory computer storage medium of claim 15, further causing the processing device to:
driving the local word line to follow a low voltage signal by setting the second phase signal at a third value while the first phase signal is set to the first value; and is
Isolating the local word line from the low voltage signal by setting the second phase signal at a fourth value at the same time or after the first phase signal is set to the second value.
17. The non-transitory computer-readable storage medium of claim 16, wherein the driving of the local wordline is performed by a sub-wordline driver including only NMOS type transistors.
18. The non-transitory computer-readable storage medium of claim 17, wherein the sub-wordline driver includes a first NMOS transistor having a gate that receives the first phase signal, a source that receives the global wordline signal, and a drain connected to the local wordline,
wherein the sub-word line driver further includes a second NMOS transistor having a gate receiving the second phase signal, a source receiving a low voltage signal, and a drain connected to the local word line.
19. The non-transitory computer-readable storage medium of claim 15, wherein the first value of the first phase signal is higher in voltage than a value of the global word line in the active state at least to perform the driving of the local word line to follow a threshold voltage of a transistor of the global word line signal.
20. The non-transitory computer-readable storage medium of claim 19, wherein the first value is in a range of 4.2 volts to 4.5 volts.
Technical Field
Embodiments of the invention relate to a signal driver for a word line circuit and a method of driving a word line in a memory device.
Background
Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are typically provided in the form of internal semiconductor integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory, including Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), may require the application of power to maintain their data. In contrast, a non-volatile memory can retain its stored data even without the use of an external power source. Non-volatile memory may be used in various technologies, including flash (e.g., NAND and NOR) Phase Change Memory (PCM), ferroelectric random access memory (FeRAM), Resistive Random Access Memory (RRAM), Magnetic Random Access Memory (MRAM), and the like. Improving memory devices may generally include increasing memory cell density, increasing read/write speed or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs, among other metrics.
Memory devices employ various signals within various circuits of the memory device. Signal drivers for applying signals to signal lines are commonly used in electronic devices such as integrated circuits. One such signal driver may be used to apply voltages to word lines in an array of memory cells. The word lines may extend from a set of global word line drivers (also referred to herein as "master word line drivers" and "MWD") through the memory cell array. The global word line driver may selectively actuate each of the word lines in response to the memory device receiving a row address corresponding to the word line. Then, each of the memory cells in the row corresponding to the received row address applies the stored data to a corresponding sense amplifier.
Each of the word lines extending through the array may be relatively long and therefore may have a substantial capacitance. In addition, the word lines may be made of polysilicon, which may have a relatively high resistance. The combination of the relatively high capacitance and the relatively high resistance of the word lines may make it difficult for the global word line driver to quickly switch the signal level on the word lines, especially in portions of the memory cell array that are farther from the global word line driver. To alleviate this problem, memory cell arrays are typically divided into smaller memory cell arrays, and local word line drivers (also referred to herein as "sub-word line drivers" and "SWDs") are fabricated between at least some of these smaller memory cell arrays. The local word line driver may receive a signal that is substantially the same as a signal used to control the global word line driver to drive the word line such that the word line may apply the same level to the word line as the global word line driver applies to the word line.
The use of local word line drivers may improve the switching speed of the word lines, and prior art designs typically include at least one PMOS transistor and at least one NMOS transistor in each local word line driver. The use of PMOS transistors allows the local word line voltage to be the same as the global word line voltage due to the threshold voltage of the NMOS transistors, which uses a lower phase voltage than NMOS local word line drivers alone. However, while the NMOS transistors used in the local word line drivers may be fabricated in the same p-type substrate as the access transistors of the memory cells, the PMOS transistors used in the local word line drivers may require the fabrication of an n-well in the p-type substrate to provide n-type material for the fabrication of the PMOS transistors. Forming an n-well for each of the local word line drivers may greatly increase the area of the semiconductor substrate used to fabricate the local word line drivers, potentially increasing cost or reducing the capacity of the memory device.
Some semiconductor memory devices, such as DRAMs, store information in the form of charges accumulated in cell capacitors ("cells"), where the cells are organized in rows. In some cases, the charge applied to a cell in a row may interfere with the charge in one or more adjacent "victim" rows, or the cell may otherwise lose its charge, an occurrence known as "leakage". Some leakage instances may occur when a memory row undergoes "row hammering," i.e., repeatedly driving the row to an active level for a short period of time (e.g., the elapsed duration is less than the duration between sequential refresh operations) and activation affects one or more adjacent victim rows. This may cause the cell charge in the victim row to change, putting the information stored there at risk.
Various memory systems use one or more strategies to address leakage, such as row hammer stress mitigation or Targeted Row Refresh (TRR). Row hammer stress mitigation may involve the host or controller automatically performing refresh operations on victim rows on a random or periodic basis. In some embodiments, row hammer stress mitigation may include controlling the local word line voltage such that the local word line voltage pauses at an intermediate voltage level for a predetermined period of time when changing from an active level to a pre-charge level or a standby level. By pausing at the intermediate voltage, adjacent memory rows are not affected by rapid changes in voltage levels and row hammer stress can be mitigated.
Disclosure of Invention
In some embodiments, a sub-word line circuit for a memory device is provided, the sub-word line circuit for a memory device comprising: a phase driver circuit configured to provide a first phase signal and a second phase signal; a sub-wordline driver circuit including a pull-up circuit configured to receive the first phase signal and a global wordline signal, the pull-up circuit further configured to drive a local wordline to follow the global wordline signal when the first phase signal is at a first value and to isolate the local wordline from the global wordline signal when the first phase signal is at a second value; and a processing device operatively coupled to the phase driver circuit, the processing device configured to set the first phase signal to a first value before the global wordline signal enters an active state and to set the first phase signal to the second value only after the global wordline signal has entered a pre-charge state.
In some embodiments, a method is provided. The method comprises the following steps: generating a first phase signal and a second phase signal in a memory device; driving a local wordline of the memory device to follow a global wordline signal by setting the first phase signal to be at a first value before the global wordline signal enters an active state; and isolating the local wordline from the global wordline signal by setting the first phase signal to be at the second value only after the global wordline signal has entered a pre-charge state.
In some embodiments, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium comprises instructions that, when executed by a processing device, cause the processing device to: generating a first phase signal and a second phase signal in a memory device; driving a local wordline of the memory device to follow a global wordline signal by setting the first phase signal to be at a first value before the global wordline signal enters an active state; and isolating the local wordline from the global wordline signal by setting the first phase signal to be at the second value only after the global wordline signal has entered a pre-charge state.
Drawings
FIG. 1 is a block diagram of an embodiment of a memory system according to the present disclosure.
FIG. 2 is a block diagram of a portion of a memory bank array that may be used in the memory system of FIG. 1.
FIG. 3A is a schematic diagram of an embodiment of a master wordline driver according to the present disclosure.
FIG. 3B is a signal timing diagram for the master wordline driver of FIG. 3A.
Fig. 3C is a schematic diagram of an embodiment of an RF driver with optional row hammer stress mitigation for the master wordline driver of fig. 3A according to the present disclosure.
FIG. 3D is a flow chart of operations for managing master wordline drivers according to the present disclosure.
FIG. 4A is a schematic diagram of an embodiment of a master word line driver array according to the present disclosure.
FIG. 4B is a schematic diagram of an embodiment of a sub-wordline driver array according to the present disclosure.
FIG. 5A is a schematic diagram of another embodiment of a sub-wordline driver array according to the present disclosure.
Fig. 5B is a signal timing diagram of the sub word line driver of fig. 5A.
FIG. 6 is a schematic diagram of an embodiment of an FX phase driver according to the disclosure.
FIG. 7 is a flow chart of operations for managing sub-wordline drivers according to the present disclosure.
Detailed Description
As discussed in more detail below, the technology disclosed herein relates to signal drivers for word line drivers and associated circuitry in memory systems and devices. However, it will be understood by those skilled in the art that the present technology is capable of additional embodiments and of being practiced without several of the details of the embodiments described below with reference to FIGS. 1-6. In the embodiments illustrated below, the memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured in accordance with other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), Erasable Programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric storage media, magnetoresistive storage media, and other storage media including non-volatile flash (e.g., NAND and/or NOR) storage media.
FIG. 1 is a block diagram schematically showing a memory device 100, in accordance with an embodiment of the present technology. Memory device 100 may include an array of memory cells, such as
Memory device 100 may employ a plurality of external terminals to communicate with an external memory controller and/or a host processor (not shown). The external terminals may include command terminals and address terminals coupled to the command bus and address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS; a clock terminal for receiving clock signals CK and CKF; a data clock terminal for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI, and DMI; power supply terminals VDD, VSS, VDDQ, and VSSQ.
Address signals and bank address signals may be provided to the command terminals and address terminals from an external memory controller and/or a host processor. The address signal and the group address signal supplied to the address terminal may be transmitted to the
Command signals CMD, address signals ADDR, and chip select signals CS may be provided from the memory controller to the command and address terminals. The command signals may represent various memory commands (e.g., including access commands, which may include read commands and write commands) from a memory controller. The select signal CS may be used to select the memory device 100 in response to commands and addresses provided to the command terminal and the address terminal. When the active CS signal is provided to the memory device 100, the command and address may be decoded and the memory operation may be performed. The command signal CMD may be provided to the
When a read command is issued and a row address and a column address are provided in time with the read command, read data may be read from the memory cells in the
When a write command is issued and a row address and a column address are provided in time with the command, write data may be provided to the data terminals DQ, DBI and DMI according to the WCK and WCKF clock signals. The write command may be received by
The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal
Fig. 2 shows a simplified block diagram of an exemplary structure of a memory bank MB of the
Each memory bank MB includes one or more FXDs providing phase signals PH and PHF for selecting SWD based on decoded row address signals and timing control signals. As shown in fig. 2, the PH and/or PHF signals may be provided to the SWD in one or more of the segments SECT0-SECTn to select the appropriate SWD. For example, in some embodiments, each set of PH/PHF signals from the FXD may be coupled to the SWD in each of a predetermined number of the segments SECT0 through SECTn. The predetermined number of sections may be seven sections, and the set of PH/PHF signals may be connected to the SWD in each of the seven sections. However, in other exemplary embodiments, the predetermined number may be greater than seven portions or less than seven portions. FXD is discussed in more detail below.
FIG. 3A illustrates an exemplary embodiment of a master wordline driver 300. MWD 300 may include a first type of transistor 302 (e.g., a PMOS transistor) having a source coupled to signal ARMW. The signal ARMW and the voltage of its complementary ARMWF may correspond to a decoded address signal, e.g., a first portion of a decoded row address. For example, the decoded row address armw (armwf) may correspond to one or more MWD of the memory bank MB. The drain of transistor 302 may be connected to a drain of transistor 304 (e.g., an NMOS transistor), which may be different from the first type. The interconnected drains of the transistors 302, 304 are coupled to a global word line GR. The source of transistor 304 may be connected to a voltage source, which may be, for example, in the range of-0.25 volts to 0 volts. For example, as shown in FIG. 3A, the voltage source is at Vnwl. However, in other embodiments, the voltage source may be at Vss or at some other low voltage value. The gate of transistor 304 may be connected to the ARMWF signal. The gate of transistor 302 is driven by the RFF signal. The RFF and RF signals may correspond to a portion of the decoded row address, which may relate to one or more MWD of the memory bank MB, for example.
In addition to transistors 302 and 304, MWD 300 can also include series-connected transistors 306 and 308 (which can be, for example, NMOS transistors). The drain of transistor 306 may be connected to the global word line GR and the source of transistor 306 may be connected to the drain of transistor 308. The gate of transistor 306 may be connected to the decoded address signal ARMW and the gate of transistor 308 may be connected to the RFF signal. A source of transistor 308 may be connected to the RF signal. Based on the voltage values (high or low) of the ARMW, ARMWF, RF and/or RFF signals, the MWD sets the corresponding global word line GR to the active state or the pre-charge state or the standby state. As discussed above, the active or high state of the global word line GR may be at Vcc, Vccp, or some other voltage level corresponding to an active or high state, and the precharge or standby state of the global word line GR may be at Vss, Vnwl, or some other voltage level corresponding to a precharge or standby state. The high states of the ARMW, ARMWF, RF and RFF signals may be voltages in the range of 2.3 volts to 3.5 volts, for example, while the low states may be voltages in the range of-0.25 volts to 0 volts (ground). For example, when in a high state, the ARMW, ARMWF, RF, and RFF signals may be at voltage levels corresponding to Vcc (e.g., in the range of about 2.3 volts to 2.7 volts, e.g., 2.5 volts), Vccp (e.g., in the range of about 3.0 volts to 3.5 volts, e.g., 3.2 volts), or some other voltage level corresponding to the high state of the signals. When in the low state, the ARMW, ARMWF, RF, and RFF signals may be at voltage levels corresponding to Vss (e.g., ground or 0 volts), Vnwl (e.g., in the range of about-0.1 volts to-0.25 volts, e.g., -0.2 volts), or some other voltage level corresponding to the low state.
The value of the high state is not necessarily the same for all signals. For example, one or more of the signals may have a high state at 3.2 volts, while one or more of the remaining signals may have a high state at 2.5 volts (or some other suitable high voltage value). Similarly, the value of the low state is not necessarily the same for all signals. For example, one or more of the signals may have a low state at-0.2 volts, while one or more of the remaining signals may have a low state at 0 volts (or some other suitable low voltage value). In some embodiments, the high state may be based on a high voltage source, e.g., Vcc, Vccp, or some other high voltage source, while the low state may be based on a low voltage source, e.g., Vss, vnwl, or some other low voltage source. In some embodiments, one or more signals (e.g., RF signals) and/or the global word line GR may be set to an intermediate voltage state Voff to mitigate the effects of row hammer stress.
In operation, the MWD 300 receives the ARMW, ARMWF, RF and RFF signals, and then sets the state of the global word line GR based on the values of the signals. Processor 116 (and/or another processor) may control the decoded row address signals ARMW/ARMWF and RF/RFF to operate MWD 300. Circuits (not shown) for generating the ARMW and ARMWF signals are known in the art and, therefore, will not be discussed further for the sake of brevity. Fig. 3C illustrates an exemplary RF driver circuit for generating RF and RFF signals (also referred to herein as "row factor" signals) in accordance with an embodiment of the present disclosure. MWD 300 may include a pull-up circuit 301, a pull-down circuit 304, and an intermediate voltage circuit 305. Pull-up circuit 301 may include PMOS transistor 302. The source of the PMOS transistor 302 may be connected to the decoded address signal ARMW, and the gate of the PMOS transistor 302 may be connected to the row factor signal RFF. The drain of the PMOS transistor may be connected to the global word line GR. The pull-down circuit 303 may include an NMOS transistor 304. The drain of NMOS transistor 304 may be connected to global word line GR, and the gate of NMOS transistor 304 may be connected to decoded address signal ARMWF. The source of NMOS 304 may be connected to a low voltage source, such as Vnwl (or Vss or another low voltage source, for example). MWD 300 may also include an intermediate voltage circuit 305. The intermediate voltage circuit 305 includes an NMOS transistor 306 connected in series with a NOMS transistor 308. The drain of the NMOS transistor 306 may be connected to the global word line GR and the gate of the NMOS transistor may be connected to the decoded address signal ARMW. The source of NMOS transistor 306 may be connected to the drain of NMOS transistor 308. The gate of the NMOS transistor 308 may be connected to the row factor signal RFF, and the source of the NMOS transistor 308 may be connected to the row factor signal RF. As discussed below, the intermediate voltage circuit 305 allows the voltage on the global word line GR to be pulled down to an intermediate voltage between the active voltage state and the precharge voltage state to achieve row hammer stress mitigation. Of course, in some embodiments, the functionality of the pull-down circuit 304 and the intermediate voltage circuit 305 may be combined into a single circuit.
Referring to fig. 3A and 3B, the MWD300 may be configured such that if the ARMW signal is in a high state and the RFF signal is in a low state, the global word line GR is set to be in an active state or a high state (see signal at t 0). With the RFF signal in a low state and the ARMW signal in a high state, transistor 302 will turn on to pull up the global word line GR to the value of the ARMW signal, which may be at Vcc, Vccp, or some other suitable high voltage value. With the RFF signal in a low state, the transistor 308 will be turned off to isolate the global word line GR from the value of the RF signal. Those skilled in the art understand that "isolation" as used herein means actual isolation between the source and drain of a transistor, and does not necessarily mean complete electrical isolation, as some leakage current may be present in a transistor in some cases. Additionally, with the ARMWF signal in a low state, transistor 304 will turn off to isolate the global word line GR from the voltage source Vnwl (or, for example, Vss or some other low voltage source).
In some embodiments, when transitioning from an active state or high state to a pre-charge state or standby state, MWD300 enters an intermediate voltage state (or row hammer stress mitigation state) before entering the pre-charge state or standby state. For example, at time t1, when the RFF signal is set to a high state, the RF signal is set to an intermediate state having a voltage Voff for a predetermined period of time (e.g., time t1 to t 2). In some embodiments, Voff may be a value in the range of 0.25 volts to 0.75 volts, for example, 0.5 volts. Turning to fig. 3A, with the RFF and ARMW signals set to a high state, transistors 306 and 308 turn on to pull down the value of the global word line GR to the value of the RF signal (which is at Voff). Additionally, with the RFF signal in a high state, the transistor 302 is turned off to isolate the value of the ARMW signal from the global word line GR. Thus, in this embodiment, the global word line GR transitions from the active state or high state to the intermediate voltage Voff before transitioning to the precharge state or standby state at time t 2. By limiting the step change in voltage when changing from the active state or the high state to the precharge state or the standby state, the adjacent word lines WL in the memory group MB are not affected by a rapid change in voltage level, and the row hammer stress can be relieved. In some embodiments, when row hammer stress mitigation is not needed or desired, the RF signal is not set to Voff and the global word line GR transitions from an active or high state to a pre-charge or standby state without first changing to an intermediate voltage (see, e.g., dashed lines in fig. 3B).
In some embodiments, at time t1 (no row hammer stress mitigation) or time t2 (row hammer stress mitigation), the ARMWF signal may be set to a high state to turn on transistor 304 to connect the global word line GR to Vnwl (or Vss or some other low voltage source, for example). With the ARMW now in the low state, transistor 306 will turn off to isolate the RF signal from the global word line GR. Additionally, the value of the RFF signal is in a high state to ensure that the transistor 302 is turned off to isolate the global word line GR from the ARMW signal. Table 1 provides a logic table that shows the state of the global word line GR (a-active, P-precharge or I-intermediate voltage (row hammer stress mitigation)) based on the states of the decoded address signal and row factor signal of MWD 300.
TABLE 1
ARMW
ARMWF
RFF
RF
GR
L
H
H
L
P
H
L
L
H
A
H
L
H
I
I
Fig. 3C is a schematic diagram of an exemplary embodiment of a row factor driver circuit ("RF driver circuit") with row hammer stress mitigation. As shown in FIG. 3C, the RFF and RF signals used by MWD 300 can be generated by RF driver circuit 310. RF driver circuit 310 may receive input signals RMSMWP, RFX _ n, and RMSXDP, which are decoded row address and/or timing signals from a row decoder (not shown). For example, the RFX _ n signal may be a decoded address signal corresponding to a memory bank and/or one or more MWD of the memory bank, where X may represent a memory bank and n may represent a corresponding one or more MWD within the memory bank. The RMSMWP signal and the RMSXDP signal may be timing signals used to generate the RFF signal and the RF signal used in the operation of the corresponding MWD or MWD.
Prior to time t0 (see fig. 3B), the RFX _ n signal may be set to a low state, which may mean that the associated memory bank and/or corresponding MWD is not selected for operation. That is, with the RFX _ n signal in a low state, the output of the NAND gate 312, and therefore the RFF signal, is high to isolate the global word line GR from the ARMW signal. In addition, a low RFX _ n signal means that the output of NAND gate 316 is also high. When the output on NAND gate 316 is high, NMOS transistor 332 is turned on. Since NMOS transistor 330 is a continuously gated transistor, node 321, and thus the RF signal, is pulled down to the value of Vnwl (or Vss or some other low voltage source, for example) through transistor 332. Thus, prior to t0, the RFF signal and the RF signal to the MWD300 will be high and low, respectively.
Additionally, where the RFX _ n signal is low, the output of AND gate 314 is low AND NMOS transistor 322 is off, which isolates voltage Voff (for row hammer stress mitigation) from node 321 even though NMOS transistor 326 is turned on due to the high RFF signal. Similarly, PMOS transistor 320 turns off to isolate voltage V1 from node 321. In some embodiments, the PMOS transistor 320 is turned off because the source voltage V1 is set to be lower than the high voltage value of the RFF signal. For example, if the high voltage value of the RFF is at Vccp, voltage V1 may be Vccp-Vt, where Vt is the threshold voltage of transistor 320 (e.g., V1 is 2.5 volts if Vccp is 3.2 volts and Vt is 0.7 volts). Voltage V1 may be set to be at least the threshold voltage of transistor 320 below the high voltage value of the RFF signal to prevent unreliable operation of transistor 320.
The RFX _ n signal may be set to a high state (e.g., corresponding to time t0 in fig. 3B) to select an associated memory bank and/or corresponding MWD for operation. In some embodiments, timing signals RMSWMP and RMSXDP are also set to a high state when RFX _ n is in a high state. With the RFX _ n and RMSWMP signals in a high state, the output of NAND gate 312 is low, which means the RFF signal is low. A low signal value on RFF means that the ARMW signal is connected to global word line GR in MWD 300. Additionally, a low signal value on RFF means NMOS transistor 326 is turned off to isolate Voff from node 321. With RFF low, PMOS transistor 320 turns on to pull up node 321 and thus the RF signal, high to voltage V1. In some embodiments, V1 may be 2.5 volts, and the RF signal may be pulled up to a value of 2.5 volts. With the RFX _ n signal and the RMSXDP signal in a high state, the NMOS transistor 322 is turned on, but since the NMOS transistor 326 is turned off, the node 321 remains isolated from the voltage source Voff. To prevent unreliable operation, a continuously gated NMOS transistor 324 is provided in series between NMOS transistor 322 and NMOS transistor 326. The NMOS transistor 324 has a gate voltage Von sufficient to keep the transistor 324 continuously gated. The inclusion of the continuously gated transistor 324 provides greater reliability for the RF driver circuit 310 by providing a resistive path for the leakage current through the NMOS transistor 326 to create a voltage drop in the leakage current path when the NMOS transistor 326 is off.
With the RFX _ n and RMSXDP signals in a high state, the output of NAND gate 316 is low, which means NMOS transistor 332 is turned off to isolate node 321 from voltage source Vnwl (or Vss or some other low voltage source, for example). To prevent unreliable operation, a continuously gated NMOS transistor 330 is provided in series between node 321 and NMOS transistor 332. The signal at the gate of transistor 330 may be at a voltage Vccp (as shown in fig. 3C), Vcc, or some other suitable voltage to keep transistor 330 on. The continuously gated NMOS transistor 330 provides greater reliability for the RF driver circuit 310 by providing a resistive path for the leakage current through the NMOS transistor 332 to create a voltage drop in the leakage current path when the NMOS transistor 332 is off.
After a predetermined period of time (e.g., at time t1, see fig. 3B), the timing signal RMSMWP may be set to a low state, which sets the output of the NAND gate circuit 312, and thus the RFF signal, to a high state. With the RFF signal in a high state, the ARMW signal is isolated from the global word line GR. With the RFF signal in the high state, the PMOS transistor 320 is turned off to isolate the node 321 from the voltage source V1, and the NMOS transistor 326 is turned on.
In some embodiments, when row hammer stress mitigation is desired, the RMSXDP signal remains high for a predetermined period of time (e.g., from time t1 to t2, see fig. 3B) to allow for a "soft landing" of the RF voltage and, thus, the global word line voltage GR. As discussed below, a "soft landing" on a global word line GR also means a "soft landing" on a local word line WL to mitigate row hammer stress between adjacent local word lines WL in the memory bank MB. To alleviate row hammer stress, the global word line GR is stepped down to an intermediate voltage Voff before entering the precharge state or standby state. This is accomplished by having the global word line GR follow the RF signal for a predetermined period of time (e.g., between t1 and t2, see fig. 3B). For example, in the case where the RMSXDP signal AND the RFX _ n signal are in a high state, the output of the AND gate 314 is kept in a high state to keep the NMOS transistor 322 turned on. With NMOS transistors 322, 324, and 326 all on, node 321, and thus the RF signal, is pulled down to voltage Voff, which may be, for example, 0.5 volts. The predetermined period of time that the RMSXDP signal remains high after the RMSMWP signal is set to the low state may correspond to a period of time between t1 and t 2. In some embodiments, when row hammer stress mitigation is not desired, the RMSXDP signal may be set to a low state while the RMSMWP signal is set to a low state. When the RMSXDP signal is set to a low state, the output of AND gate 314 is set low to isolate node 321 from voltage Voff. In addition, the output of NAND gate 316 is set high to turn on NMOS transistor 332, thereby pulling node 321 down to voltage Vnwl (or, for example, Vss or some other low voltage source). As discussed above, the RFF signal and the RF signal generated by the RF driver 310, along with the ARMW signal and the ARMWF signal, can be used by the MWD 300 to set the global wordline voltage.
Fig. 3D is a flow chart illustrating an example method 350 for managing the operation of an MWD. Method 350 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 350 is performed by
At block 360, a processing device (e.g., the
Fig. 4A illustrates an exemplary arrangement of a portion of the MWD array in memory bank MB. For simplicity, FIG. 4A shows only four global word lines GR0, GR1, GR2, and GR3, and the corresponding
TABLE 2
ARMW0
ARMW0F
ARMW1
ARMW1F
RF3F<0>
RF3<0>
RF3F<1>
RF3<1>
GR0
GR1
GR2
GR3
H
L
L
H
L
H
H
L
A
P
P
P
H
L
L
H
H
I
H
L
I
P
P
P
H
L
L
H
H
L
L
H
P
A
P
P
H
L
L
H
H
L
H
I
P
I
P
P
L
H
H
L
L
H
H
L
P
P
A
P
L
H
H
L
H
I
H
L
P
P
I
P
L
H
H
L
H
L
L
H
P
P
P
A
L
H
H
L
H
L
H
I
P
P
P
I
As discussed above, each of the global word lines (e.g., GR0 through GR3) is connected to the SWD in order to quickly drive the signal levels on the respective word lines. FIG. 4B illustrates an exemplary embodiment of an SWD array arrangement corresponding to global word lines GR0 and
SWD 450 may include a pull-up circuit having a PMOS transistor 452 that turns on when the PHF phase signal connected to the gate of PMOS transistor 452 is low (e.g., at Vnwl, Vss, or another low value). The SWD 450 may also include an NMOS transistor 456 placed in parallel with the PMOS transistor 452. NMOS transistor 456 may act as a pull-up or pull-down circuit based on the voltage on global word line GR0 and turn on when the PH phase signal connected to the gate of NMOS transistor 456 is high (e.g., Vccp, Vcc, or another high voltage value). SWD 450 may also include a pull-down circuit having an NMOS transistor 454 that turns on when the PHF phase signal connected to the gate of NMOS transistor 454 is high (e.g., Vccp, Vcc, or another high voltage value). The sources of transistors 452 and 456 may be connected to a global word line GR0, and the drains of transistors 452 and 456 may be connected to the drain of transistor 454. The interconnected drains of the transistors 452, 456, and 454 are coupled to a local
As shown in fig. 4B, the selection of the SWD, and thus the local word line WL, for accessing the appropriate memory cell is determined by the PHn/PHFn signal (also referred to herein as the phase signal) corresponding to the decoded row address signal, where n is 0 or 1 in the exemplary embodiment of fig. 4B. The PHn phase signal and the PHFn phase signal may be connected to one or more SWDs. For example, in FIG. 4B, each set of phase signals (e.g., PH0/PHF0 and PH1/PHF1) is shown connected to two SWDs (e.g., 450/470 and 460/480, respectively). However, the set of phase signals may be connected to more than two SWDs. For example, in some embodiments, each set of PH/PHF signals may be coupled to the SWD in each of a predetermined number of the sections SECT0 through SECTn (see fig. 2). For example, the predetermined number of sections may be seven sections, and the set of PH/PHF signals may be connected to the SWD in each of the seven sections. However, in other exemplary embodiments, the predetermined number may be greater than seven portions or less than seven portions. In some conventional SWDs, a global wordline signal is used to switch the transistors in the SWD (e.g., a complement of the GR0 signal may be connected to the gates of the pull-up PMOS transistors and the PH phase signal may be connected to the sources of the pull-up PMOS transistors in some conventional transistors). However, by switching the transistor gates of the SWDs using the PH phase signal and the PHF phase signal and connecting the set of PH/PHF phase signals to the SWDs in one or more of the sections SECT0 through SECTn, the required layout area for the phase drivers on memory device 100 may be reduced.
As shown in FIG. 4B, the global word line GR0 signal is provided by the MWD (e.g., MWD 410) as discussed above. As known to those skilled in the art, the PH0 phase signal and the PHF0 phase signal may be set by the phase drivers to appropriate states to place the SWD 450 in an active state, an intermediate voltage state, and a precharge state. For example, as shown in FIG. 4B, the PH0 phase signal may be set to a high state with a value of Vccp, which may be in the range of 3.0 volts to 3.5 volts. In some embodiments, the value of Vccp may be 3.2 volts. In some embodiments, the high state may be Vcc. The PHF0 phase signal may be set to a low state having a value such as Vnwl (or Vss or another low voltage value, for example). With PH0 in a high state, SWD 450 is selected to be in an active state to receive and follow the value of global word line GR0, and memory cells attached to WL0 may be accessed for memory operations (e.g., read, write, etc.) based on the value of global
FIG. 5A illustrates another exemplary embodiment of a SWD array arrangement corresponding to global word lines GR0 and
Timing control of NMOS transistors, such as those used in, for example, SWD 510-540, may create problems with the stability and reliability of the NMOS transistors. For example, if an NMOS transistor switches in the presence of a high source-to-drain voltage (Vsd) or drain-to-source voltage (Vds), the stability and reliability of the NMOS transistor may be affected. In exemplary embodiments of the present disclosure, the timing operation of one or more of the NMOS transistors in the SWD and/or the signal to the SWD is controlled such that switching occurs at a minimum or reduced Vds or Vsd magnitude.
Fig. 5B illustrates a timing diagram that provides stability and reliability for the operation of the NMOS-only SWD of fig. 5A. For simplicity, only the timing of the SWD 510 is shown, but those skilled in the art will appreciate that the timing diagrams for other SWDs will be similar. The global word line GR0 signal is provided by the MWD (e.g., MWD 410) as discussed above. For example, the value of the global wordline GR0 may be at Vccp (or another high voltage level), Voff (or another intermediate voltage level), or Vnwl (or another low voltage level). Prior to time T0, the PH0 phase signal may be set to a high state with a value of Vccp2, which may be in the range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 may be in the range of 4.2 volts to 4.5 volts, e.g., 4.2 volts or 4.5 volts. The PHF0 phase signal may be set to a low state having a value such as Vnwl (or Vss or another low voltage value, for example). The PH0 phase signal and the PHF0 phase signal may be set to their respective states by the FX phase drivers, see FIG. 6 discussed below. With PH0 in a high state, SWD 510 is selected to be in an active state to receive and follow the value of global word line GR0, and memory cells attached to WL0 may be accessed for memory operations (e.g., read, write, etc.) based on the value of global
Operation of the SWD 510 is provided with reference to fig. 5A and 5B. At time T0, the processor 116 (and/or another processor) may control input signals to an FX phase driver (e.g.,
Turning to FIG. 5B, at time T2, the processor 116 (and/or another processor) may control the input signal to the MWD (e.g., the
After the global word line GR0 has reached the precharge state, at time T4, the processor 116 (and/or another processor) may control the input signal to the FX phase driver (e.g.,
As discussed above, in some sub-wordline drivers (see, e.g., fig. 4B), a PMOS transistor is included in each of the SWDs. The PMOS transistor allows the word line WL to reach the full high voltage of the global word line GR. For example, if a global word line (e.g., GR0, GR1, GR2, or GR3) is at 3.2 volts, the corresponding local word line (e.g., WL0, WL1, WL2, or WL3) may be pulled up to full 3.2 volts by the PMOS transistors. However, PMOS transistors may require an n-well in the p-well where an entire column of memory cells is formed, making the layout area for SWD larger. Since there are a large number of global word lines in a typical memory device, an NMOS-only SWD, such as the NMOS-only SWD shown in fig. 5A, reduces the amount of space required for the SWD by avoiding the need for an n-well for each of the SWDs (which reduces the area required for the SWD on the semiconductor substrate). However, with an SWD that becomes NMOS-only, the full voltage at the local word lines (e.g., WL0, WL1, WL2, WL3) may not be achieved unless the gate voltage required to couple the voltage from the global word line (e.g., GR0, GR1, GR2, GR3) to the corresponding local word line (e.g., WL0, WL1, WL2, WL3) is increased by at least the threshold voltage of the NMOS transistor. For example, in the embodiment of FIG. 5A discussed above, the gate voltage of Vccp2 (e.g., 4.2 volts, 4.5 volts) is applied by the PH0 phase signal, rather than the gate voltage of Vccp (e.g., 3.2 volts) used in conventional circuits. Thus, the voltage of the PHn phase signal applied to the gate of the pull-up NMOS transistor in the NMOS-only SWD may be higher (e.g., Vccp2) than the voltage (e.g., Vcc, Vccp, etc.) used for the pull-up PMOS transistor in the conventional SWD. In some embodiments, Vccp2 may be in the range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 may be in the range of 4.2 volts to 4.5 volts, e.g., 4.2 volts or 4.5 volts. Conventional FX phase drivers cannot provide such high PH phase signal voltages without experiencing stability and reliability issues.
In an exemplary embodiment of the present disclosure, the FX phase driver providing the PHn phase signal and the PHFn phase signal is configured to reliably provide a signal voltage ranging from Vnwl to Vccp2 (e.g., -0.2 volts to 4.7 volts). As shown in FIG. 6, the
As shown in FIG. 6, the gates of
The PHF signal is transmitted to the
The transistor 622 (which may be a PMOS transistor) may have a drain connected to the source of the transistor 624 (which may be a PMOS transistor). The source of
As shown in fig. 6, the gates of the
When the timing signal R2ACF is low, the
TABLE 3
In some embodiments, rows 1A and 1B in table 3 may correspond to time periods before T0 and after T4 in fig. 5B. During these periods, the corresponding SWD (e.g., SWD 510, 520, 530, or 540) is in a pre-charge state or a standby state. Row 2 may correspond to the time period between T0 and T3. During this time period, the corresponding SWD (e.g., SWD 510, 520, 530, or 540) is in an active/intermediate voltage state, and as discussed above, the local word line WL (e.g., WL0, WL1, WL2, or WL3) follows the voltage on the respective global word line GR (e.g., GR0, GR1, GR2, or GR 3). If it is desired for any reason to delay setting PHF0 to the high state after PH0 enters the low state, row 3 may correspond to a time when both the PHF signal and the PH signal are low.
Fig. 7 is a flow chart illustrating an example method 700 of operation for managing SWD. Method 700 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 700 is performed by
At block 710, a processing device (e.g., the
At block 730, the processing device (e.g., the
Although the present invention has been described with reference to the disclosed embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the invention. For example, although the exemplary embodiments have been explained with respect to NMOS transistors being the only transistors used in the SWD, it should be understood that in other embodiments PMOS transistors may be substituted for the NMOS embodiments and vice versa, in which case the memory cell array and SWD may be fabricated in an n-type substrate instead of a p-type substrate. Such modifications are well within the ability of one of ordinary skill in the art. Accordingly, the invention is not limited except as by the appended claims.
The above detailed description of embodiments of the present technology is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. While specific embodiments of, and examples for, the technology are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the technology, as those skilled in the relevant art will recognize. For example, while the steps are presented in a given order, alternative embodiments may perform the steps in a different order. The various embodiments described herein may also be combined to provide further embodiments.
From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Where the context permits, singular or plural terms may also encompass plural or singular terms, respectively. Furthermore, when referring to a list of two or more items, the use of "or" in such a list should be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list, unless the word "or" is expressly limited to refer to only a single item and not to other items. Furthermore, the terms "comprising," "including," "having," and "with" are used throughout to mean including at least one or more of the recited features, such that any greater number of the same feature and/or additional types of other features are not excluded.
The processing device (e.g., the
A machine-readable storage medium (also referred to as a computer-readable medium) stores one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The machine-readable storage medium may be, for example, memory device 100 or another memory device. The term "machine-readable storage medium" shall be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.
The present disclosure also relates to apparatus for performing the operations herein. Such an apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.
The present disclosure may be provided in the form of a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.
It should also be understood that various modifications may be made without departing from the disclosure. For example, one of ordinary skill in the art will appreciate that the various components of the present technology may be further divided into sub-components, or the various components and functions of the present technology may be combined and integrated. In addition, certain aspects of the present technology described in the context of particular embodiments may also be combined or omitted in other embodiments. Additionally, while advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present technology. Accordingly, the present disclosure and associated techniques may encompass other embodiments not explicitly shown or described.
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