Method for forming chip packaging structure
阅读说明:本技术 形成芯片封装结构的方法 (Method for forming chip packaging structure ) 是由 陈俊廷 施应庆 卢思维 吴志伟 于 2020-04-10 设计创作,主要内容包括:本公开提供一种形成芯片封装结构的方法,包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开。第一芯片结构与第二芯片结构之间具有第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽,此沟槽部分地位在第一芯片结构以及第二芯片结构之中,且部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条在第一芯片结构、第二芯片结构、以及第一间距上方。(The present disclosure provides a method of forming a chip package structure including bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure is spaced apart from the second chip structure. The first chip structure and the second chip structure have a first distance therebetween. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench, the trench being located partially within the first chip structure and the second chip structure and partially above the first pitch. The method includes forming an anti-buckling strip in the trench. The anti-warping bar is over the first chip structure, the second chip structure, and the first pitch.)
1. A method of forming a chip package structure, comprising:
bonding a first chip structure and a second chip structure to a surface of a substrate, wherein the first chip structure is spaced apart from the second chip structure with a first spacing therebetween;
removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench, the trench being partially located in the first chip structure and the second chip structure and partially located above the first pitch; and
An anti-warping bar is formed in the trench, wherein the anti-warping bar is above the first chip structure, the second chip structure and the first space.
Technical Field
The embodiment of the disclosure relates to a chip packaging structure and a forming method thereof.
Background
Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit features and elements on the material layers.
Typically, many integrated circuits are fabricated on a semiconductor wafer. The die may be processed and packaged at the wafer level on the wafer level, and various techniques for wafer level packaging have been developed. Since a chip package may require different chips with different functions, it is a challenge to form a reliable chip package with different chips.
Disclosure of Invention
According to some embodiments, the present disclosure provides a method of forming a chip package structure, comprising bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure is spaced apart from the second chip structure. The first chip structure and the second chip structure have a first distance therebetween. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench, the trench being located partially within the first chip structure and the second chip structure and partially above the first pitch. The method includes forming an anti-buckling strip in the trench. The anti-warping bar is over the first chip structure, the second chip structure, and the first pitch.
According to some embodiments, the present disclosure provides a method of forming a chip package structure. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure is separated from the second chip structure by a first pitch. The method includes removing a first portion of a first chip structure and a second portion of a second chip structure to form a trench, the trench residing partially in the first chip structure, partially in or over the second chip structure, and partially over the first pitch. The method includes forming an anti-buckling strip in the trench. The warp-resistant strip extends across the first pitch.
According to some embodiments, the present disclosure provides a chip packaging structure. The chip packaging structure comprises a substrate. The chip packaging structure comprises a first chip structure and a second chip structure, and is positioned above the substrate. The first chip structure is spaced apart from the second chip structure. The chip packaging structure comprises an anti-warping strip, and is positioned in the first chip structure and positioned in or above the second chip structure. The anti-warp strip extends continuously from the second chip structure into the first chip structure.
Drawings
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not shown to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present disclosure.
Fig. 1A to 1I are cross-sectional views of various stages of a process of forming a chip package structure.
Fig. 1A-1 is a top view of the chip package structure of fig. 1A, according to some embodiments.
FIG. 1B-1 is a top view of the chip package structure of FIG. 1B, according to some embodiments.
Fig. 1C-1 is a top view of the chip package structure of fig. 1C, according to some embodiments.
FIG. 1I-1 is a top view of the chip package structure of FIG. 1I, according to some embodiments.
Fig. 2A is a cross-sectional view of a chip package structure according to some embodiments.
Fig. 2B is a top view of the chip package structure of fig. 2A, according to some embodiments.
Fig. 3 is a top view of a chip package structure according to some embodiments.
Fig. 4A is a top view of a chip package structure according to some embodiments.
Fig. 4B is a cross-sectional view of the chip package structure shown along section line I-I' in fig. 4A, according to some embodiments.
Fig. 5 is a top view of a chip package structure according to some embodiments.
Fig. 6 is a cross-sectional view of a chip package structure according to some embodiments.
Fig. 7 is a cross-sectional view of a chip package structure according to some embodiments.
Fig. 8A is a top view of a chip package structure according to some embodiments.
Fig. 8B is a cross-sectional view of the chip package structure shown along section line I-I' in fig. 8A, according to some embodiments.
Wherein the reference numerals are as follows:
10: seed layer
100, 200, 300, 400, 500, 600, 700, 800: chip package structure 110: substrate
111: semiconductor structure
111a, 111 b: surface of
112: guide hole
113: insulating layer
114, 117: redistribution structure
114a, 117 a: dielectric layer
114b, 117 b: line layer
114c, 117 c: guide hole
115: conducting pad
116: insulating layer
118: conducting pad
119: buffer ring
120, 130: wafer structure
124, 139, 162, 172: top surface
131, 132, 133, 134: semiconductor die
132a, 133a, 134a, 158a, 158 b: side wall
135, 170: molding layer
135a, 156: lower surface
136: conductive bonding structure
137, 150: underfill layer
138: guide hole
140, 192: conductive bump
152, 154, 174, 176: in part
160: anti-warping strip
164a, 164 b: end part
180: mask layer
182: opening of the container
212: solder layer
212 a: solder ball
610: substrate
A: adhesive layer
B: bottom surface
C: inner wall
G1, G2, G3, G4: distance between each other
I-I': section line
L1, L2, L3: length of
R: groove
SC: cutting path
T1, T2, T3, T4, T5: thickness of
W1, W2, W3, W4, W5, W6: width of
Detailed Description
Various embodiments or examples are disclosed below to practice various features of the provided subject matter, and embodiments of specific elements and arrangements thereof are described below to illustrate the present disclosure. These examples are, of course, intended to be illustrative only and should not be construed as limiting the scope of the disclosure. For example, references in the specification to a first feature being formed over a second feature include embodiments in which the first feature is in direct contact with the second feature, as well as embodiments in which additional features are provided between the first feature and the second feature, i.e., the first feature and the second feature are not in direct contact. Moreover, where specific reference numerals or designations are used in the various embodiments, these are merely used to clearly describe the disclosure and are not intended to necessarily indicate a particular relationship between the various embodiments and/or structures discussed.
Furthermore, spatially relative terms, such as "between …", "below", "lower", "above", "upper" and the like, may be used herein to facilitate describing the relationship of element(s) or feature(s) to one another in the drawings and are intended to encompass different orientations of the device in which the features are included. When the device is turned to a different orientation (rotated 90 degrees or otherwise), then the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation. It will be understood that additional operations may be provided before, during or after the methods described above, and that some of the operations described may be substituted or eliminated with respect to other embodiments of the methods described above.
Some embodiments of the disclosure are described below. Additional operations may be provided before, during and/or after the stages described in the embodiments. Certain stages described may be replaced or eliminated with respect to different embodiments. Additional features may be added to the semiconductor device structure. Certain functions described below may be replaced or removed for different embodiments. Although some embodiments are discussed using operations that are performed in a particular order, the operations may be performed in other logical orders.
Other features and processes may also be included in the present disclosure. For example, test structures may be included to facilitate verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate to allow testing of 3D packages or 3 DICs, use of probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structure as well as the final structure. In addition, the structures and methods disclosed in the present disclosure may be used with intermediate verification test methods of known good dies to increase yield and reduce cost.
Fig. 1A to 1I are cross-sectional views of various stages of a process of forming a chip package structure. Fig. 1A-1 is a top view of the chip package structure of fig. 1A, according to some embodiments. Fig. 1A is a cross-sectional view of a chip package structure shown along section line I-I' in fig. 1A-1, according to some embodiments.
According to some embodiments, as shown in FIG. 1A and FIG. 1A-1, a
According to some embodiments, the
In some other embodiments, the
In some embodiments, the
According to some embodiments, the insulating
In other embodiments, the
For example, the transistors may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), high-voltage transistors (high-voltage transistors), high-frequency transistors (high-frequency transistors), p-channel and/or n-channel field effect transistors (PFETs/NFETs), and the like. Various processes are performed to form various device elements, such as front-end-of-line (FEOL) semiconductor processes. The front end of line semiconductor manufacturing process may include deposition, etching, implantation, lithography, annealing, planarization, one or more other suitable processes, or a combination thereof.
In some embodiments, isolation features (not shown) are formed in the
According to some embodiments,
As shown in fig. 1A, according to some embodiments, vias 114c make electrical connections between different line layers 114b, and between line layer 114b and
According to some embodiments, as shown in fig. 1A,
According to some embodiments, the
In some embodiments,
In some embodiments, semiconductor dies 132, 133, and 134 are memory dies. The memory die may include memory devices, such as Static Random Access Memory (SRAM) devices, Dynamic Random Access Memory (DRAM) devices, other suitable devices, combinations thereof, or the like. In some embodiments, semiconductor die 131 is a control die electrically connected to memory dies (e.g., semiconductor dies 132, 133, and 134) stacked on semiconductor die 131. The
Various changes and/or modifications may be made to the embodiments of the present disclosure. In some embodiments,
In some embodiments, an underfill layer 137 is formed between the
In some embodiments, as shown in fig. 1A, a plurality of
According to some embodiments, as shown in fig. 1A and 1A-1,
According to some embodiments,
FIG. 1B-1 is a top view of the chip package structure of FIG. 1B, according to some embodiments. Fig. 1B is a cross-sectional view of a chip package structure shown along section line I-I' in fig. 1B-1, according to some embodiments. According to some embodiments, as shown in fig. 1B and 1B-1, portions of the
According to some embodiments, after the removal process, the
According to some embodiments, the removal process forms trenches R in part in
According to some embodiments, as shown in fig. 1B, the lower surface 122 of the
Fig. 1C-1 is a top view of the chip package structure of fig. 1C, according to some embodiments. Fig. 1C is a cross-sectional view of a chip package structure shown along section line I-I' in fig. 1C-1, according to some embodiments. As shown in fig. 1C and 1C-1, the
According to some embodiments,
According to some embodiments, the
According to some embodiments, the
According to some embodiments, the gap G2 has a width W3. According to some embodiments, the width W2 of the trench R is greater than the width W3. According to some embodiments, the
According to some embodiments, the
According to some embodiments, the width W4 is in a range from about 100 μm to about 2000 μm. According to some embodiments, width W5 is greater than width W3. According to some embodiments, the width W5 is in a range from about 100 μm to about 2000 μm. In some embodiments, width W4 is greater than width W5.
According to some embodiments, the
According to some embodiments, the metallic material comprises copper, gold, silver, aluminum, alloys thereof, combinations thereof, or other suitable materials. According to some embodiments, if the
The semiconductor material comprises an elemental semiconductor material comprising silicon or germanium in a single crystal, polycrystalline, or amorphous structure. In other embodiments, the warp
According to some embodiments, as shown in fig. 1C, each
According to some embodiments, the adhesion layer a directly contacts the upper
According to some embodiments, as shown in fig. 1D, a
According to some embodiments, as shown in fig. 1E,
According to some embodiments, a portion 174 of the
According to some embodiments, portion 176 surrounds
According to some embodiments, as shown in fig. 1F, a lower portion of
According to some embodiments, the via 112 and the insulating
According to some embodiments,
In some embodiments, redistribution structure 117 is formed on
According to some embodiments, as shown in fig. 1G, a conductive pad 118 is formed on the redistribution structure 117. According to some embodiments, the vias 117c electrically connect between different line layers 117b and between the line layer 117b and the conductive pads 118. According to some embodiments, fig. 1G shows only one of the line layers 117b for the sake of brevity. According to some embodiments, the via 112 is electrically connected to the conductive pad 118 through the line layer 117b and the via 117 c.
According to some embodiments, a buffer ring 119 is formed over the conductive pad 118, as shown in FIG. 1G. According to some embodiments, the buffer ring 119 has an opening 119a to expose the underlying conductive pad 118. According to some embodiments, the buffer ring 119 is configured to buffer stress between bumps subsequently formed over the buffer ring 119 and the
According to some embodiments, the cushion ring 119 is made of an elastomeric material, such as a polymeric material (e.g., polyimide). In some other embodiments (not shown), the buffer ring 119 is replaced with a buffer layer having an opening to expose the conductive pad 118.
According to some embodiments, as shown in fig. 1G, a
According to some embodiments, a masking layer 180 is formed over
According to some embodiments, as shown in fig. 1H, a
According to some embodiments, as shown in fig. 1H, a solder layer 212 is formed over the
As shown in FIG. 1I, according to some embodiments, the masking layer 180 is removed. According to some embodiments, as shown in fig. 1I, the
FIG. 1I-1 is a top view of the chip package structure of FIG. 1I, according to some embodiments. FIG. 1I is a cross-sectional view of a chip package structure shown along section line I-I' in FIG. 1I-1, according to some embodiments. According to some embodiments, as shown in fig. 1H, 1I and 1I-1, a cutting process is performed to cut the
According to some embodiments, the chip package 100 is flipped upside down as shown in fig. 1I. According to some embodiments, as shown in fig. 1I-1, portion 174 of
Since the
Fig. 2A is a cross-sectional view of a
According to some embodiments, as shown in fig. 2A and 2B, the structure and formation method of the
The forming manner of the
According to some embodiments, the thinning process comprises a Chemical Mechanical Polishing (CMP) process. According to some embodiments, the
Fig. 3 is a top view of a chip package structure 300, according to some embodiments. According to some embodiments, as shown in fig. 3, the chip package structure 300 is similar to the
Fig. 4A is a top view of a
According to some embodiments, as shown in fig. 4A and 4B,
Fig. 5 is a top view of a
Fig. 6 is a cross-sectional view of a chip package structure 600, according to some embodiments. According to some embodiments, as shown in fig. 6, the
According to some embodiments, the
The substrate 610 may be a wiring substrate or a built-in substrate. In some other embodiments, the
Fig. 7 is a cross-sectional view of a chip package structure 700 according to some embodiments. According to some embodiments, as shown in fig. 7, chip package structure 700 is similar to
Fig. 8A is a top view of a
According to some embodiments, as shown in fig. 8A and 8B,
The processes and materials used to form the
According to some embodiments, the present disclosure provides a chip packaging structure and a method of forming the same. The method (for forming the chip package structure) forms anti-warp bars in the first and second wafer structures that extend across a gap between the first and second wafer structures. The anti-warpage strip reduces warpage of the chip package structure caused by a mismatch in thermal expansion coefficients between the first and second wafer structures.
According to some embodiments, the present disclosure provides a method of forming a chip package structure, comprising bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure is spaced apart from the second chip structure. The first chip structure and the second chip structure have a first distance therebetween. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench, the trench being located partially within the first chip structure and the second chip structure and partially above the first pitch. The method includes forming an anti-buckling strip in the trench. The anti-warping bar is over the first chip structure, the second chip structure, and the first pitch.
In some embodiments, the method of forming a chip package structure further comprises forming an underfill layer in the first pitch and in a second pitch after bonding the first chip structure and the second chip structure to the surface of the substrate and before removing the first portion of the first chip structure and the second portion of the second chip structure, the second pitch being between the first chip structure and the surface and between the second chip structure and the surface, wherein removing the first portion of the first chip structure and the second portion of the second chip structure further comprises removing a third portion of the underfill layer in the first pitch. In some embodiments, the anti-warp bars are located over the underfill layer in the first pitch. In some embodiments, the anti-warp bars are harder than the underfill layer. In some embodiments, the method of forming the chip package structure further includes forming a molding layer over the surface and in the trench after forming the anti-warpage strip in the trench, wherein the molding layer over the surface surrounds the first chip structure and the second chip structure, and the molding layer in the trench surrounds the anti-warpage strip. In some embodiments, the first width of the anti-warp bars is less than the second width of the trenches. In some embodiments, the anti-buckling bars are spaced apart from the inner walls of the grooves by a second pitch, and the molding layer fills the second pitch. In some embodiments, the warp-resistant strip is harder than the shaping layer. In some embodiments, the anti-warp strip is bonded to the first chip structure and the second chip structure by an adhesive layer between the anti-warp strip and the first chip structure and between the anti-warp strip and the second chip structure. In some embodiments, the width of the anti-buckling strip is less than the length of the anti-buckling strip.
According to some embodiments, the present disclosure provides a method of forming a chip package structure. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure is separated from the second chip structure by a first pitch. The method includes removing a first portion of a first chip structure and a second portion of a second chip structure to form a trench, the trench residing partially in the first chip structure, partially in or over the second chip structure, and partially over the first pitch. The method includes forming an anti-buckling strip in the trench. The warp-resistant strip extends across the first pitch.
In some embodiments, the method of forming the chip package structure further includes forming an underfill layer in the first pitch and in a second pitch between the first chip structure and the surface and between the second chip structure and the surface after bonding the first chip structure and the second chip structure to the surface of the substrate and before removing the first portion of the first chip structure and the second portion of the second chip structure, wherein removing the first portion of the first chip structure and the second portion of the second chip structure further includes removing a third portion of the underfill layer in the first pitch and the first lower surface of the first chip structure, the second lower surface of the second chip structure, and the third lower surface of the underfill layer together form a bottom surface of the trench, and the anti-warpage bar is located above the bottom surface. In some embodiments, the anti-warpage strip is bonded to the first chip structure, the second chip structure, and the underfill layer by an adhesive layer, and the adhesive layer directly contacts the anti-warpage strip, the first chip structure, the second chip structure, and the underfill layer. In some embodiments, the anti-warp bars are harder than the underfill layer. In some embodiments, the anti-warp strip extends across the second chip structure.
According to some embodiments, the present disclosure provides a chip packaging structure. The chip packaging structure comprises a substrate. The chip packaging structure comprises a first chip structure and a second chip structure, and is positioned above the substrate. The first chip structure is spaced apart from the second chip structure. The chip packaging structure comprises an anti-warping strip, and is positioned in the first chip structure and positioned in or above the second chip structure. The anti-warp strip extends continuously from the second chip structure into the first chip structure.
In some embodiments, the chip package structure further includes an underfill layer positioned between the first chip structure and the second chip structure, between the first chip structure and the substrate, and between the second chip structure and the substrate. In some embodiments, the anti-warpage strip is located over the underfill layer and between the first chip structure and the second chip structure. In some embodiments, the anti-warping strip is spaced apart from the first chip structure and the second chip structure. In some embodiments, the chip package structure further includes an adhesive layer between the anti-warpage strip and the first chip structure, and between the anti-warpage strip and the second chip structure.
The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art may readily devise many other varied processes and structures that are consistent with the present disclosure and which will still achieve the same objects and/or advantages as those achieved by the embodiments of the present disclosure. Those skilled in the art should also realize that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure, and that such departures from the present disclosure are intended to be embraced therein.
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