阅读说明：本技术 用于对线程同步的阶段进行协调的技术 (Techniques for coordinating phases of thread synchronization ) 是由 H·C·爱德华兹 于 2021-03-19 设计创作，主要内容包括：本发明公开了用于对线程同步的阶段进行协调的技术,具体公开了用于利用应用程序编程接口执行并行计算(诸如CUDA)来在一个或更多个程序中执行数据相关的并行运算而不依赖于一个或更多个程序之间的同步操作的装置、系统和技术。例如,至少一个实施例涉及处理器或计算系统,其用于确定线程组中的哪个线程最后完成修改共享数据,并且选择该线程来执行来自所述线程组的附加的数据相关计算。(Disclosed are techniques for coordinating phases of thread synchronization, and in particular, apparatus, systems, and techniques for performing parallel computations (such as CUDA) using an application programming interface to perform data-dependent parallel operations in one or more programs without relying on synchronous operations between the one or more programs. For example, at least one embodiment relates to a processor or computing system for determining which thread in a thread group last completed modifying shared data, and selecting that thread to perform additional data-dependent computations from the thread group.)

1. A machine-readable medium having stored thereon an Application Programming Interface (API), which if executed by one or more processors, causes the one or more processors to indicate at least an order of arrival of threads in a thread group.

2. The machine-readable medium of claim 1, wherein:

a first thread of the thread group modifies a first shared data value;

a second thread of the thread group modifies a second shared data value;

when the first thread has finished modifying the first shared data value, the first thread indicates a first arrival to the API;

when the second thread has finished modifying the second shared data value, the second thread indicates a second arrival to the API; and

the first thread or the second thread is selected by one or more threads from the group of threads to perform a set of operations dependent on the first shared data value and the second shared data value, the selection based at least in part on the order of arrival including the first arrival and the second arrival indicated by the API.

3. The machine readable medium of claim 2, wherein the first thread and the second thread complete modifying the first shared data value and the second shared data value when the first thread and the second thread do not contain additional instructions that depend on the first shared data value and the second shared data value.

4. The machine-readable medium of claim 2, wherein the first thread and the second thread indicate to the API by performing a function call.

5. The machine-readable medium of claim 2, wherein the first thread or the second thread is selected by receiving the arrival order from the API and determining whether the first thread or the second thread has a lowest value in the arrival order.

6. The machine-readable medium of claim 2, wherein the set of operations dependent on the first shared data value and the second shared data value is a conclusion.

7. The machine-readable medium of claim 1, wherein the API, when executed by the one or more processors, facilitates parallel computations performed by each thread of the thread group.

8. The machine-readable medium of claim 1, wherein each thread in the thread group is synchronized by waiting for one or more arrivals indicated in the arrival order.

9. The machine-readable medium of claim 1, wherein a first thread in the thread group is selected to execute the set of pre-processing instructions based at least in part on whether the first thread is available to execute the set of pre-processing instructions before other threads in the thread group.

10. The machine-readable medium of claim 9, wherein if the first thread is unavailable to execute the set of pre-processing instructions before other threads of the thread group, selecting a second thread of the thread group to execute the set of pre-processing instructions.

11. A method, comprising:

the order of arrival of the threads in the thread group is indicated by an Application Programming Interface (API).

12. The method of claim 11, further comprising:

determining whether the thread is the last in the arrival order;

selecting the thread from the group of threads to execute a set of instructions that depends on one or more shared data values, the selecting based at least in part on whether the thread is the last in the order of arrival;

Executing the set of instructions if the thread is selected; and

if the thread is not selected, the set of instructions is executed by a second thread from the group of threads that is the last in the arrival order.

13. The method of claim 12, wherein the set of instructions that depend on the one or more shared data values is a conclusion.

14. The method of claim 12, wherein the thread is determined to be the last in the order of arrival based at least in part on a count value provided by the API.

15. The method of claim 12, wherein the order of arrival is determined based on when each thread in the thread group has completed modifying one or more shared data items.

16. The method of claim 15, wherein when each thread in the thread group does not contain additional modifications required by the instruction set, then each thread in the thread group has completed modifying one or more shared data items.

17. The method of claim 11, wherein if the thread is a first one of the thread groups available to perform one or more operations to prepare shared data, selecting the thread to perform the one or more operations to prepare the shared data.

18. The method of claim 11, wherein the API provides one or more function calls that facilitate parallel computations performed by each thread in the thread group.

19. The method of claim 11, wherein each thread in the thread group is synchronized by waiting for one or more arrivals indicated in the arrival order.

20. A processor, comprising:

one or more circuits to indicate, by an Application Programming Interface (API), an order of arrival of threads in a thread group.

21. The processor of claim 20, wherein:

determining an arrival index for the thread based on the arrival order;

if the arrival index of the thread is the last in the order of arrival, the thread executing a set of instructions that depend on one or more shared data values; and

determining a second thread to execute the instruction set based on the arrival order if the arrival index of the thread is not the last in the arrival order.

22. The processor of claim 21, wherein the arrival index is determined based at least in part on a count value provided by the API.

23. The processor of claim 21, wherein the second thread executes the set of instructions if the second thread is the last in the arrival order.

24. The processor of claim 21, wherein the set of instructions that depend on the one or more shared data values is a stop.

25. The processor of claim 21, wherein the order of arrival is determined based on when each thread in the group of threads has completed modifying the one or more shared data items during execution.

26. The processor of claim 25, wherein each thread in the thread group has completed modifying the one or more shared data items when each thread in the thread group does not contain additional modifications to the one or more shared data items required by the instruction set.

27. The processor of claim 20, wherein each thread in the thread group is synchronized by waiting for one or more arrivals indicated in the arrival order.

28. The processor of claim 20, wherein if the thread is a first one of the group of threads available to perform one or more operations to prepare one or more shared data items, the thread is selected to perform the one or more operations to prepare the one or more shared data items.

29. The processor of claim 20, wherein the API provides one or more function calls that facilitate parallel computations performed by each thread in the thread group.

30. A system, comprising:

one or more circuits to indicate, via an Application Programming Interface (API), an order of arrival of threads in a thread group.

31. The system of claim 30, wherein:

a first thread of the thread group modifies a first shared data value;

a second thread of the thread group modifies a second shared data value;

when the first thread has finished modifying the first shared data value, the first thread indicates a first arrival to the API;

when the second thread has finished modifying the second shared data value, the second thread indicates a second arrival to the API; and

the first thread or the second thread is selected by one or more threads of the thread group to perform a set of operations dependent on the first shared data value and the second shared data value, the selection based at least in part on the arrival order, including the first arrival and the second arrival indicated by the API.

32. The system of claim 31, wherein the set of operations dependent on the first shared data value and the second shared data value is a conclusion.

33. The system of claim 31, wherein the first thread or the second thread is selected by receiving the arrival order from the API and determining whether the first thread or the second thread is the last in the arrival order.

34. The system of claim 31, wherein the first thread and the second thread complete modifying the first shared data value and the second shared data value when the first thread and the second thread do not include an operation that computes one or more new values for the first shared data value and the second shared data value.

35. The system of claim 31, wherein the first thread and the second thread indicate to the API by executing a function call provided by the API.

36. The system of claim 30, wherein the API provides one or more function calls that facilitate parallel computing.

37. The system of claim 30, wherein each thread in the thread group is synchronized by waiting for one or more arrivals indicated in the arrival order.

38. The system of claim 30, wherein the thread is selected to execute the prolog instruction set based at least in part on whether the thread is the first of the group of threads available to execute the prolog instruction set.

39. The system of claim 38 wherein a second thread is selected to execute the prolog instruction set if the first thread is not the first of the thread groups available for execution of the prolog instruction set and the second thread is the first of the thread groups available for execution of the prolog instruction set.

Technical Field

At least one embodiment relates to a processing resource for performing data-dependent parallel operations in one or more programs that utilize an application programming interface to perform parallel computations, such as a CUDA. For example, at least one embodiment relates to a processor or computing system for determining which programs in a program suite are to perform shared data-related operations based on their locations in execution using the various novel techniques described herein.

Background

A parallel program contains multiple threads that compute different data values in parallel. These data values are typically shared, in whole or in part, between each thread as part of a larger computation. Shared memory is used to store these shared data values, and in some examples, each thread must copy to and from shared memory to ensure that it operates on the most current data. Shared memory dependencies have presented performance bottlenecks in parallel computing platforms, such as Graphics Processing Units (GPUs). During execution, a multi-threaded program running on a parallel computing platform performs many expensive synchronization operations to ensure that any shared data used by each thread is current.

Drawings

FIG. 1 is a block diagram illustrating thread synchronization in a classic parallel computing environment on a Graphics Processing Unit (GPU), according to at least one embodiment;

FIG. 2A is a block diagram illustrating multiple threads performing operations including both prolog and epilogue operations with synchronization in accordance with at least one embodiment;

FIG. 2B is a block diagram illustrating multiple threads performing operations including prolog and epilogue operations using the various novel techniques for thread data management described herein, in accordance with at least one embodiment;

FIG. 3 is a block diagram illustrating determining a thread for performing prolog operations in accordance with at least one embodiment;

FIG. 4 is a block diagram illustrating determining a thread for safely performing a conclusion operation in accordance with at least one embodiment;

FIG. 5 illustrates a process for determining one or more threads in a thread group for performing prologue and epilogue operations in accordance with at least one embodiment;

FIG. 6 illustrates an exemplary data center in accordance with at least one embodiment;

FIG. 7 illustrates a processing system in accordance with at least one embodiment;

FIG. 8 illustrates a computer system in accordance with at least one embodiment;

FIG. 9 illustrates a system in accordance with at least one embodiment;

FIG. 10 illustrates an exemplary integrated circuit in accordance with at least one embodiment;

FIG. 11 illustrates a computing system in accordance with at least one embodiment;

FIG. 12 illustrates an APU in accordance with at least one embodiment;

FIG. 13 illustrates a CPU according to at least one embodiment;

FIG. 14 illustrates an exemplary accelerator integration slice in accordance with at least one embodiment;

15A-15B illustrate an exemplary graphics processor in accordance with at least one embodiment;

FIG. 16A illustrates a graphics core in accordance with at least one embodiment;

FIG. 16B illustrates a GPGPU in accordance with at least one embodiment;

FIG. 17A illustrates a parallel processor in accordance with at least one embodiment;

FIG. 17B illustrates a processing cluster in accordance with at least one embodiment;

FIG. 17C illustrates a graphics multiprocessor in accordance with at least one embodiment;

FIG. 18 illustrates a graphics processor in accordance with at least one embodiment;

FIG. 19 illustrates a processor in accordance with at least one embodiment;

FIG. 20 illustrates a processor in accordance with at least one embodiment;

FIG. 21 illustrates a graphics processor core in accordance with at least one embodiment;

FIG. 22 illustrates a PPU in accordance with at least one embodiment;

FIG. 23 illustrates a GPC according to at least one embodiment;

FIG. 24 illustrates a streaming multiprocessor in accordance with at least one embodiment;

FIG. 25 illustrates a software stack of a programming platform in accordance with at least one embodiment;

FIG. 26 illustrates a CUDA implementation of the software stack of FIG. 25 in accordance with at least one embodiment;

FIG. 27 illustrates a ROCm implementation of the software stack of FIG. 25 in accordance with at least one embodiment;

FIG. 28 illustrates an OpenCL implementation of the software stack of FIG. 25 in accordance with at least one embodiment;

FIG. 29 illustrates software supported by a programming platform in accordance with at least one embodiment;

FIG. 30 illustrates compiled code executing on the programming platform of FIGS. 25-28, in accordance with at least one embodiment;

FIG. 31 illustrates more detailed compiled code executed on the programming platform of FIGS. 25-28, in accordance with at least one embodiment;

FIG. 32 illustrates translating source code prior to compiling the source code in accordance with at least one embodiment;

FIG. 33A illustrates a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment;

FIG. 33B illustrates a system configured to compile and execute the CUDA source code of FIG. 33A using a CPU and a CUDA-enabled GPU in accordance with at least one embodiment;

FIG. 33C illustrates a system configured to compile and execute the CUDA source code of FIG. 33A using a CPU and a CUDA-not-enabled GPU in accordance with at least one embodiment;

FIG. 34 illustrates an exemplary kernel converted by the CUDA to HIP conversion tool of FIG. 33C in accordance with at least one embodiment;

FIG. 35 illustrates the CUDA-not-enabled GPU of FIG. 33C in further detail in accordance with at least one embodiment; and

FIG. 36 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 35 in accordance with at least one embodiment.

Detailed Description

FIG. 1 is a block diagram illustrating thread synchronization 114, 118 with a shared memory 104 in a classic parallel computing environment on a Graphics Processing Unit (GPU), according to at least one embodiment. In at least one embodiment, one or more processes 102 are a logical grouping of computing units within a software program. In at least one embodiment, process 102 is executed on one or more hardware computing units, such as a Parallel Processing Unit (PPU) or a Graphics Processing Unit (GPU), each containing multiple hardware cores for executing instructions, as further described herein. In at least one embodiment, the process 102 executes one or more threads 106, 108, 110, 112 corresponding to the process 102 using one or more hardware computing units.

In at least one embodiment, the threads 106, 108, 110, 112 are individual compute units containing instructions that, when executed by a hardware compute unit, perform operations on data, as described further herein. In at least one embodiment, the threads 106, 108, 110, 112 contain instructions that, when executed, perform operations on or manipulate data. In at least one embodiment, one or more threads 106, 108, 110, 112 contain instructions that, when executed, modify data objects stored in the shared memory 104. In at least one embodiment, one or more threads 106, 108, 110, 112 perform operations on data objects shared between the one or more threads 106, 108, 110, 112. In at least one embodiment, data objects shared among one or more threads 106, 108, 110, 112 are stored in the shared memory 104.

In at least one embodiment, the shared memory 104 is memory on a Parallel Processing Unit (PPU) or other computing unit, such as a Central Processing Unit (CPU) or Graphics Processing Unit (GPU), for facilitating data storage and sharing among multiple threads 106, 108, 110, 112, as described above. In at least one embodiment, the shared memory 104 is physical memory. In at least one embodiment, the shared memory 104 is an abstraction of physical memory, such as virtual memory. In at least one embodiment, an abstraction of the physical memory for the shared memory 104 is provided by hardware on the PPU or GPU. In at least one embodiment, an abstraction of the physical memory of the shared memory 104 is provided by software running on the PPU or GPU to facilitate parallel computing by other software programs, such as a Compute Unified Device Architecture (CUDA) or other software described herein.

In at least one embodiment, the shared memory 104 contains data used by one or more threads 106, 108, 110, 112 to perform computations. In at least one embodiment, the data stored in the shared memory 104 is unique to each thread 106, 108, 110, 112. In at least one embodiment, the data stored in the shared memory 104 is data modified by one or more threads 106, 108, 110, 112. In at least one embodiment, if one thread 106, 108, 110, 112 is dependent on data stored in the shared memory 104, the data modified by that thread 106, 108, 110, 112 is used by another thread 106, 108, 110, 112. In at least one embodiment, the data stored in the shared memory 104 is synchronized 114, 118 to ensure that each thread 106, 108, 110, 112 uses the most up-to-date data from the shared memory 104.

In at least one embodiment, the synchronization 114, 118 is a set of software instructions that, when executed, updates data values in one or more threads 106, 108, 110, 112 from the shared memory 104. In at least one embodiment, the synchronizations 114, 118 are software function calls to an Application Programming Interface (API) to facilitate parallel computing, such as CUDA. In at least one embodiment, the synchronization 114, 118 copies data 116, 120 from the threads 106, 108, 110, 112 to the shared memory 104 to ensure that the shared memory 104 contains the most recent data values. In at least one embodiment, the synchronization 114, 118 copies the shared data values 116, 120 in the shared memory 104 to one or more threads 106, 108, 110, 112 to ensure that the threads 106, 108, 110, 112 are using the most recent data values.

In at least one embodiment, the threads 106, 108, 110, 112 are synchronized 114, 118 prior to performing computations on the shared data values, as described above. Once the data value is synchronized 114 from the shared memory 104, in an embodiment, the threads 106, 108, 110, 112 perform operations on the shared data value. In at least one embodiment, the threads 106, 108, 110, 112 are synchronized 118 with the shared memory 104 a second time upon completion of the threads 106, 108, 110, 112 performing operations on the shared data values. In at least one embodiment, once the shared data in each thread 106, 108, 110, 112 has been synchronized 118, the computation may continue in each thread 106, 108, 110, 112 using the synchronized data 124 from the shared memory 104. In at least one embodiment, data dependent computations in the threads 106, 108, 110, 112 that require the use of the synchronization data 124 must wait for the synchronization operation 118 to continue.

Fig. 2A is a block diagram illustrating multiple threads 204, 206, 208 using classical synchronization 210, 216 to perform an operation 202 that includes both prologue (prologue)210 and epilogue (epilogue)218 operations, in accordance with at least one embodiment. In at least one embodiment, one or more threads 204, 206, 208 as described herein include instructions to perform the compute operation 202 over time 220. In at least one embodiment, time 220 is a measurement that is performed when performed in sequence. In at least one embodiment, the operation 202 is performed by sequentially executing one or more instructions over time 220. In at least one embodiment, the operations 202 are sequences of software instructions that, when executed, perform computations on an execution unit, such as a Parallel Processing Unit (PPU), a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), or other execution unit as described herein.

In at least one embodiment, the operation 202 is a parallel operation performed by one or more threads 204, 206, 208. In at least one embodiment, the operation 202 includes data shared among the threads 204, 206, 208 and stored in both global memory for each thread 204, 206, 208 and shared memory shared among each thread 204, 206, 208. In at least one embodiment, data shared between threads 204, 206, 208 is synchronized by performing synchronization 210, 216.

In at least one embodiment, the synchronization 210, 216, 222, 224 as described above is a sequence of instructions that, when executed, ensures that each thread 204, 206, 208 contains updated shared data values in its global memory, in accordance with at least one embodiment. In at least one embodiment, the synchronizations 210, 216, 222, 224 are sequences of instructions or software function calls provided by an Application Programming Interface (API) to facilitate parallel computing, such as CUDA or other APIs described herein. In at least one embodiment, the synchronization 210, 216, 222, 224 is performed prior to any instruction blocks in the thread that use shared data values, such as the prologue 212, the body 214, or the epilogue 218.

In at least one embodiment, the prolog 212 is a set of instructions that, when executed, performs a set of sub-operations in the operation 202 that set one or more threads 204, 206, 208 to perform parallel computations on data including shared data, as described above. In at least one embodiment, the sub-operations include initializing data, allocating memory, performing preliminary computations, and preparing shared data for use by one or more threads 204, 206, 208 in performing the operation 202 that includes parallel computations on shared data. In at least one embodiment, prologs 212 are executed after synchronization 210 to ensure that shared data is synchronized before operation 202 including the prologs. In at least one embodiment, the prologue 212 prepares shared data for use by the subject 214 in performing the operations 202 of the parallel computations by the thread groups 204, 206, 208. In at least one embodiment, prologue 212 is a pre-processing sub-operation performed in operation 202.

In at least one embodiment, the principal 214 executes after the synchronization 222. In at least one embodiment, the subject 214 is a set of instructions that, when executed, performs parallel operations on data shared by one or more threads 204, 206, 208. In at least one embodiment, each parallel operation performed by each thread 204, 206, 208 calculates a respective value of shared data or a respective value that contributes to one or more shared data values. In at least one embodiment, an example of an operation 202 that includes sub-operations performed in parallel by one or more threads 204, 206, 208 is a euclidean norm operation. In at least one embodiment, the euclidean norm operation is defined as:

wherein for one or more data values x_iCalculating the sum of squaresThen taking the square root. In at least one embodiment, the subject 214 of each thread 204, 206, 208 computes the individual squares in parallelIn at least one embodiment, preamble 212 initializes each data value x, as described above_i. In at least one embodiment, once the various threads 204, 206, 208 have computed each individual square in parallelSum is calculated for result 218And a square root.

In at least one embodiment, the completion of a subject 214 operation that modifies one or more shared data values by a thread 204, 206, 208 is the arrival of instructions for the subject 214 operation at a point where the one or more shared data values are no longer modified. In at least one embodiment, an arrival is an indication that execution of an instruction in one or more threads 204, 206, 208 has reached a certain operation point. In at least one embodiment, a subset of instructions indicating completion of one or more threads 204, 206, 208 is reached. In at least one embodiment, an instruction arriving at an indicated thread 204, 206, 208 has reached a particular execution point. In at least one embodiment, the arrival indicates that the execution of the threads 204, 206, 208 has reached the prolog 212. In at least one embodiment, reaching occurs when execution of the threads 204, 206, 208 has reached a point where no further modifications are performed on one or more shared data values. In at least one embodiment, the arrival occurs when any of the instructions in the threads 204, 206, 208 have been entered into the prolog 212 or have completed modifying one or more shared data values.

In at least one embodiment, the conclusion 218 is a set of instructions that, when executed, performs a data-dependent operation using one or more shared data values computed in the subject 214 by one or more threads 204, 206, 208. In at least one embodiment, the final 218 is executed once each thread 204, 206, 208 has completed their subject 214 operations. As described below in conjunction with FIG. 4, in an embodiment, the ending statement 218 is executed once the last thread of the thread groups 204, 206, 208 reaches a particular execution point. In at least one embodiment, the conclusion 218 is executed once the last thread of the thread group 204, 206, 208 has completed modifying one or more shared data values. In at least one embodiment, synchronization 216, as described above, is performed to ensure that each thread 204, 206, 208 has completed its subject operations.

In at least one embodiment, the linger 218 is executed by a single thread 204, 206, 208 once each thread 204, 206, 208 has completed its individual subject 214. In at least one embodiment, once the second synchronization 216 has been performed, one or more threads 204, 206, 208 are selected to execute the conclusion 218. As described below, in an embodiment, once all threads 204, 206, 208 have completed their subject 214, one or more threads 204, 206, 208 are selected to execute a conclusion 218.

In at least one embodiment, one or more threads 204, 206, 208 are monitored by the API to perform parallel computations, such as CUDA, and once each thread 204, 206, 208 has completed its subject 214, a single thread 204, 206, 208 in the thread group 204, 206, 208 is selected to perform the conclusion 218 without performing synchronization 216, as described below in connection with FIG. 4.

FIG. 2B is a block diagram illustrating multiple threads 226, 228, 230 performing an operation 232 including prologue 236 and epilogue 240 operations using various novel techniques for thread data management described below in connection with FIGS. 3 and 4, in accordance with at least one embodiment. In at least one embodiment, threads 226, 228, 230 include instructions that execute over time 244, as described above in connection with FIG. 2A. Each thread 226, 228, 230 contains instructions that include an operation 232, in an embodiment, the operation 232 performs synchronization 234, 242, prologue 236, body 238, and epilogue 240, as described above in connection with fig. 2A.

In at least one embodiment, scheduling threads 226, 228, 230 to execute prologue 236 and epilogue 240 allows elimination of steps in several synchronization 216, 222 operations 232 based at least in part on whether individual threads 226, 228, 230 contain instructions to reach prologue 236 first or individual threads 226, 228, 230 contain instructions that modify the shared data value last and thus can execute epilogue 240, as further described below in connection with fig. 3 and 4. Instead, each thread 226, 228, 230 is selected or picked to execute a prologue 236 or epilogue 240, into which management operations traditionally performed by the synchronizations 216, 222 are incorporated and facilitated by an Application Programming Interface (API) to facilitate parallel computing, such as CUDA, in embodiments. In at least one embodiment, reducing the synchronization 216, 222 steps may improve the parallel performance of the threads 226, 228, 230 in the thread group. In at least one embodiment, an instruction reaches prolog 236 first if the instruction is an available instruction that can execute the prolog 236 first among the instructions in each thread 226, 228, 230.

FIG. 3 is a block diagram that illustrates determining threads 308 from a thread group 302 to perform prolog 332 operations, according to at least one embodiment. In at least one embodiment, the prolog 332 operations comprise an instruction set that when executed performs setup or preprocessing for parallel computing blocks, as described above in connection with fig. 2. In at least one embodiment, the thread group 302 is a logical group of threads 304, 306, 308, 310 that perform operations such as parallel computations. In at least one embodiment, thread group 302 is a collaboration group or any other type of thread grouping described further herein.

In at least one embodiment, the thread group 302 includes one or more threads 304, 306, 308, 310, the one or more threads 304, 306, 308, 310 including instructions 312, 314, 316, 318, 320, 322, 324, 326, 328 to perform one or more operations. In at least one embodiment, the thread group 302 includes one or more threads 304, 306, 308, 310, the threads 304, 306, 308, 310 including instructions 312, 314, 316, 318, 320, 322, 324, 326, 328 to perform one or more parallel operations including prologue 332, as described above in connection with FIG. 2.

In at least one embodiment, prologue 332 is executed by a single thread 308 selected from thread group 302. In at least one embodiment, a single thread 308 is selected from the thread group 302 to execute the prolog 332 through an Application Programming Interface (API) to facilitate parallel computing, such as CUDA or other API described herein. In at least one embodiment, the thread scheduler selects a single thread 308 from the thread group 302 based on the instructions 312, 314, 316, 318 contained in each thread 304, 306, 308, 310. In at least one embodiment, a single thread 308 is selected from the thread group 302 by the other threads 304, 306, 310 in the thread group 302 that contains the selected thread 308.

In at least one embodiment, the threads 304, 306, 308, 310 execute instructions 312, 314, 316, 318 over time 330, as described above in connection with FIG. 2. In at least one embodiment, thread C308 includes instructions 316 that arrive or are fully executed in the prologue 332 before instructions 312 in thread A304, instructions 314 in thread B306, and instructions 318 in thread D310.

Because the instruction 316 in thread C308 arrives or fully executes before the prolog 332 in all other threads 304, 306, 308, 310 in the thread group 302, in at least one embodiment, thread C308 is selected, and the instruction 320 for prolog operations is executed from the threads 304, 306, 308, 310 in the thread group 302, as described above. Once the selected thread 308 has completed executing the instruction 320 to perform the prolog 332 operations, in at least one embodiment, the threads 304, 306, 308, 310 in the thread group 302 continue execution by executing instructions 322, 324, 326, 328, which instructions 322, 324, 326, 328 implement the subject operations described above in connection with FIG. 2.

FIG. 4 is a block diagram illustrating determining threads 418 from a thread group 402 to safely execute an instruction 420 implementing a conclusion operation 424, according to at least one embodiment. In at least one embodiment, the thread group 402 described above in connection with fig. 2 and 3 includes threads 406, 418, the threads 406, 418 including instructions executed by a Parallel Processing Unit (PPU), a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), or other execution units described further herein.

Threads 406, 418 in the thread group 402 execute instructions over time 422 and execute calls 408, 412 to an Application Programming Interface (API)404 to facilitate parallel computing, such as CUDA or other APIs described herein. In at least one embodiment, the API404 is a set of function call interfaces that, when called by one or more instructions in one or more threads 406, 418, cause implementation of an instruction set that executes a function provided by the API 404. In at least one embodiment, the threads 406, 418 in the thread group 402 perform subject operations on shared data, as described above in connection with FIG. 2.

In at least one embodiment, each thread 406, 418 in the thread group 402 performs parallel computations and indicates 408, 412, via the API404, that the thread 406, 418 has reached or completed an operation or modification on shared data. As described above, the API404 collects information about unblocked (non-blocking) arrivals 410, such as a count indicating the number of outstanding unblocked arrivals 410. In at least one embodiment, the unblocked arrival 410 is an indication that the thread 406, 418 has completed a particular operation on one or more shared data values. In at least one embodiment, the unblocked reach 410 is unblocked because the threads 406, 418 in the thread group 402 are able to continue executing instructions that do not depend on shared data.

In at least one embodiment, the first thread 406 completes its body, including any modifications to the shared data, as described above in connection with FIG. 2, and executes a call 408 to the API404 indicating that it has performed an unblocked reach 410. In at least one embodiment, the arrival index is a position in an ordered set of unblocked arrivals 410, the unblocked arrivals 410 set being ordered according to when the unblocked arrivals 410 are received by the API 404. In at least one embodiment, the ordered set of unblocked arrivals 410 is one or more arrival orders. In at least one embodiment, other threads in thread group 402 continue execution and also separately execute calls to API404 indicating that they have performed an unblocked arrival. In at least one embodiment, the last thread 418 of the thread group 402 completes its body, including any modifications to the shared data, and executes a call 412 to the API404, the call 412 indicating that it has performed the final unblock reach 414. In at least one embodiment, the final unblocked arrival 414 is the unblocked arrival 410 as described above, i.e., the final unblocked arrival 414 in the sequence of unblocked arrivals 410 received by the API404 from the threads 406, 418 in the thread group 402.

In at least one embodiment, the unblocked arrival 410 is determined to be the final unblocked arrival 414 by obtaining a count of pending (pending) arrivals 416 from the API 404. In at least one embodiment, each thread 406, 418 of the thread group 402 obtains a pending count of unblocked arrivals 410 from the API404 (if requested). In at least one embodiment, if the thread 418 receives a pending arrival 416 count indicating that the thread 418 last arrived or eventually arrived unblocked, the thread 418 securely executes an instruction 420 that implements an ending operation 424, as described above in connection with FIG. 2. If thread 418 performs arrival 412 indicating to API404 as the final unblocked arrival 414, the thread last updates any shared data values used by the ending 424, and the instruction implementing ending 420 is executed by thread 418 indicating the final unblocked arrival 414.

In at least one embodiment, the threads 406, 418 in the thread group 402 determine that they have performed the final unblocked arrival 414. In at least one embodiment, the threads 406, 418 in the thread group 402 determine whether they have performed the final unblocked reach 414 based on information provided by the API 404. In at least one embodiment, the API404 provides information, such as a pending count of outstanding arrivals, which the threads 406, 418 in the thread group 402 use to determine that they have performed the final unblocked arrival 414. For example, in at least one embodiment, if a thread 406, 418 in the thread group 402 receives 416 a pending or outstanding unblocked arrival 410 count of 1 from the API404, the thread 406, 418 determines that its outstanding unblocked arrival 408, 412 is the final unblocked arrival 414.

In at least one embodiment, the threads 406, 418 in the thread group 402 perform the unblocked arrivals 408, 412 when the threads 406, 418 in the thread group 402 have completed operations in parallel computations that require the use or modification of shared data. In at least one embodiment, a thread 406, 418 in a thread group 402 is completed when the thread 406, 418 in the thread group 402 has completed executing one or more instructions that use or modify shared data in parallel computing. In at least one embodiment, when a thread 406, 418 in a thread group 420 has completed, the thread 406, 418 indicates to the API404 that it has reached 408, 412. When the thread 418 determines 416 that it last reached 414, all modifications to the shared data of the thread group 402 have been completed, as described above, and an instruction 420 of the conclusion 424, as described above in connection with FIG. 2, is executed by the thread 418.

Using the example described above in connection with fig. 2, in an embodiment, the threads 406, 418 in the thread group 402 perform euclidean norm operations defined as:

wherein for one or more data values x_iCalculating the sum of squaresThen taking the square root. In at least one embodiment, each thread 406, 418 computation of the thread group 402 includes squaring The shared data value of (2). In an embodiment, when each thread 406, 418 of the thread group 402 has completed calculating the squareWhen this is done, the thread modifies its shared data value and an indication 408, 412 is made to the API 404 that the thread 406, 418 has arrived or completed. In at least one embodiment, after a thread 406, 418 arrives or completes and has made an indication 408, 412 to the API 404, its continued execution is not dependent on the shared data valueThe instruction of (1).

In an embodiment, if a thread 406, 418 in the thread group 402 doesIf it is the final arrival or the final unblocked arrival 414 (as described above), then the shared data value is finally calculatedIn at least one embodiment, all other completed shared data values computed by other threads in the thread group 402 are givenThe threads 418 in the thread group 402 eventually compute the shared data valueThen calculateIn an embodiment, the sum is calculatedAnd the square root of the sum is the final statement 424 and is executed by the thread executing the final unblocked reach 414.

FIG. 5 illustrates a process 500 for determining one or more threads in a thread group to perform prolog 512 and epilogue 520 operations in accordance with at least one embodiment. In at least one embodiment, the process 500 for determining threads to perform prolog operations 512 and finish operations 520 begins 502 by performing a presynchronization operation 504. In at least one embodiment, the pre-synchronization operation 504 is an operation in a thread that is performed prior to the initial synchronization operation 506, as described above in connection with fig. 1 and 2.

In at least one embodiment, once the presynchronization operation 504 is complete, synchronization 506 is performed, as described above in connection with fig. 1. In at least one embodiment, synchronization 506 ensures that all shared data contains the most recent value, or that threads using shared data values are synchronized, as further described herein. In at least one embodiment, once synchronization 506 is performed, each thread performs a prolog operation 508. In at least one embodiment, the prolog operation 508 is an operation in each thread that is independent of shared data and is optional. In at least one embodiment, the thread that completes the prolog operation 508 is first determined or selected 510 to perform the prolog operation 512, as described above in connection with FIG. 3.

In an embodiment, if a thread does not first 510 complete the prolog operation 508, the thread performing the prolog operation 512 continues to perform the body operation 514 once the thread has performed the prolog operation 512. In at least one embodiment, the subject operation 514 described above in connection with fig. 2 performs a calculation that depends on or modifies one or more shared data values.

In at least one embodiment, the subject operations 514 are performed by each thread, and when each thread has completed its subject operations 514 or has completed modifying its shared data, an indication is made to an Application Programming Interface (API) to facilitate parallel computing, such as CUDA, as described above in connection with FIG. 4. In at least one embodiment, when each thread makes an indication to the API that it has reached or completed modifying its shared data, the thread determines whether it has reached 516 last, or completed modifying its shared data last.

In at least one embodiment, if the thread does not arrive 516 last, as described above in connection with FIG. 4, the thread continues to operate by performing a non-conclusion operation 518. In at least one embodiment, the non-conclusion operation 518 is an instruction that, when executed, does not depend on shared data. In at least one embodiment, if the thread last reaches 516, as described above in connection with FIG. 4, the thread performs a conclusion operation 520. In an embodiment, the result operation 520 is a shared data dependent operation performed by a thread group, as further described herein. In at least one embodiment, once the last arriving thread has performed the stop-word operation 520, the process 500 either repeats 522 for further parallel computations by the thread group or ends 522.

In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. It will be apparent, however, to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

Data center

FIG. 6 illustrates an example data center 600 in accordance with at least one embodiment. In at least one embodiment, the data center 600 includes, but is not limited to, a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

In at least one embodiment, as shown in fig. 6, the data center infrastructure layer 610 can include a resource coordinator 612, grouped computing resources 614, and node computing resources ("node c.r.") 616(1) -616(N), where "N" represents any whole positive integer. In at least one embodiment, nodes c.r.616(1) -616(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state drives or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the nodes c.r.616(1) -616(N) may be a server having one or more of the above-described computing resources.

In at least one embodiment, the grouped computing resources 614 may comprise a single group of nodes c.r. housed within one or more racks (not shown), or a number of racks housed within data centers at various geographic locations (also not shown). An individual grouping of node c.r. within grouped computing resources 614 may include computing, network, memory, or storage resources that may be configured or allocated as a group to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches, in any combination.

In at least one embodiment, the resource coordinator 612 may configure or otherwise control one or more nodes c.r.616(1) -616(N) and/or grouped computing resources 614. In at least one embodiment, the resource coordinator 612 may include a software design infrastructure ("SDI") management entity for the data center 600. In at least one embodiment, the resource coordinator 612 may comprise hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 6, framework layer 620 includes, but is not limited to, a job scheduler 632, a configuration manager 634, a resource manager 636, and a distributed file system 638. In at least one embodiment, the framework layer 620 can include a framework that supports software 652 of the software layer 630 and/or one or more applications 642 of the application layer 640. In at least one embodiment, the software 652 or applications 642 may comprise Web-based Services software or applications, respectively, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 620 may be, but is not limited to, a free and open source software network application framework, such as an Apache Spark (hereinafter "Spark") that may utilize the distributed file system 638 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 632 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 600. In at least one embodiment, configuration manager 634 may be capable of configuring different layers, such as software layer 630 and framework layer 620 including Spark and distributed file system 638 for supporting large-scale data processing. In at least one embodiment, resource manager 636 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 638 and job scheduler 632. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 614 on the data center infrastructure layer 610. In at least one embodiment, the resource manager 636 can coordinate with the resource coordinator 612 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 652 included in the software layer 630 may include software used by at least a portion of the nodes c.r.616(1) -616(N), the packet computing resources 614, and/or the distributed file system 638 of the framework layer 620. One or more types of software may include, but are not limited to, Internet web searching software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, the one or more application programs 642 included in the application layer 640 can include one or more types of application programs used by at least a portion of the nodes c.r.616(1) -616(N), the grouped computing resources 614, and/or the distributed file system 638 of the framework layer 620. The one or more types of applications may include, but are not limited to, CUDA applications.

In at least one embodiment, any of configuration manager 634, resource manager 636, and resource coordinator 612 can implement any number and type of self-modifying actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying action may mitigate a data center operator of the data center 600 from making configuration decisions that may not be good and may avoid underutilization and/or poorly performing portions of the data center.

Computer-based system

The following figures set forth, but are not limited to, an exemplary computer-based system that can be used to implement at least one embodiment.

Fig. 7 illustrates a processing system 700 in accordance with at least one embodiment. In at least one embodiment, the system 700 includes one or more processors 702 and one or more graphics processors 708, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 702 or processor cores 707. In at least one embodiment, the processing system 700 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for mobile, handheld, or embedded devices.

In at least one embodiment, the processing system 700 may include or be incorporated into a server-based gaming platform, a gaming console including gaming and media consoles, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 700 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 700 may also include a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device, coupled with or integrated in the wearable device. In at least one embodiment, the processing system 700 is a television or set-top box device having one or more processors 702 and a graphical interface generated by one or more graphics processors 708.

In at least one embodiment, the one or more processors 702 each include one or more processor cores 707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 707 is configured to process a particular instruction set 709. In at least one embodiment, the instruction set 709 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). In at least one embodiment, the multiple processor cores 707 can each process a different instruction set 709, which instruction set 709 can include instructions that facilitate emulation of other instruction sets. In at least one embodiment, processor core 707 may also include other processing devices, such as a Digital Signal Processor (DSP).

In at least one embodiment, the processor 702 includes a cache memory (cache) 704. In at least one embodiment, the processor 702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 702. In at least one embodiment, the processor 702 also uses an external cache (e.g., a level three (L3) cache or a Level Last Cache (LLC)) (not shown), which may share this logic between the processor cores 707 using known cache coherency techniques. In at least one embodiment, a register file 706 is additionally included in the processor 702, and the processor 702 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 706 may include general purpose registers or other registers.

In at least one embodiment, one or more processors 702 are coupled with one or more interface buses 710 to transmit communication signals, such as address, data, or control signals, between the processors 702 and other components in the system 700. In at least one embodiment, interface bus 710 may be a processor bus in one embodiment, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface bus 710 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 702 includes an integrated memory controller 716 and a platform controller hub 730. In at least one embodiment, the memory controller 716 facilitates communication between memory devices and other components of the processing system 700, while the Platform Controller Hub (PCH)730 provides connectivity to input/output (I/O) devices through a local I/O bus.

In at least one embodiment, memory device 720 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or have suitable capabilities to function as a processor memory. In at least one embodiment, the storage device 720 may serve as the system memory for the processing system 700 to store data 722 and instructions 721 for use when the one or more processors 702 execute applications or processes. In at least one embodiment, the memory controller 716 is also coupled with an optional external graphics processor 712, which may communicate with one or more graphics processors 708 in the processor 702 to perform graphics and media operations. In at least one embodiment, a display device 711 can be coupled to the processor 702. In at least one embodiment, the display device 711 can include one or more of an internal display device, such as in a mobile electronic device or a portable computer device or an external display device connected through a display interface (e.g., display port, etc.). In at least one embodiment, display device 711 may include a Head Mounted Display (HMD), such as a stereoscopic display device used in Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In at least one embodiment, platform controller hub 730 enables peripheral devices to be connected to memory device 720 and processor 702 via a high speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller 746, a network controller 734, a firmware interface 728, a wireless transceiver 726, touch sensors 725, a data storage device 724 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 724 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensor 725 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 726 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 728 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 734 may enable network connectivity to a wired network. In at least one embodiment, a high performance network controller (not shown) is coupled to interface bus 710. In at least one embodiment, audio controller 746 is a multi-channel high definition audio controller. In at least one embodiment, processing system 700 includes an optional legacy (legacy) I/O controller 740 for coupling legacy (e.g., personal System 2(PS/2)) devices to processing system 700. In at least one embodiment, the platform controller hub 730 may also be connected to one or more Universal Serial Bus (USB) controllers 742 that connect input devices, such as a keyboard and mouse 743 combination, a camera 744, or other USB input devices.

In at least one embodiment, the instances of memory controller 716 and platform controller hub 730 may be integrated into a discrete external graphics processor, such as external graphics processor 712. In at least one embodiment, the platform controller hub 730 and/or the memory controller 716 may be external to the one or more processors 702. For example, in at least one embodiment, the processing system 700 may include an external memory controller 716 and a platform controller hub 730, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset in communication with the processor 702.

FIG. 8 illustrates a computer system 800 in accordance with at least one embodiment. In at least one embodiment, computer system 800 may be a system with interconnected devices and components, a SOC, or some combination. In at least one embodiment, the computer system 800 is formed by a processor 802, which processor 802 may include an execution unit for executing instructions. In at least one embodiment, the computer system 800 may include, but is not limited to, a component, such as a processor 802, that employs an execution unit including logic to perform algorithms for process data. In at least one embodiment, the computer system 800 may include a processor, such as that available from Intel Corporation of Santa Clara, Calif Processor family, Xeon TM,Xscale and/or strongarm,Core^TMor Nervana^TMMicroprocessor, although other systems may be used(including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash, although other operating systems (e.g., UNIX and Linux), embedded software, and/or graphical user interfaces may also be used.

In at least one embodiment, computer system 800 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that may execute one or more instructions in accordance with at least one embodiment.

In at least one embodiment, computer system 800 may include, but is not limited to, a processor 802, which processor 802 may include, but is not limited to, one or more execution units 808, which may be configured to execute a computing unified device architecture ("CUDA") (CUDA)Developed by NVIDIA Corporation of santa clara, california). In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 800 is a single-processor desktop or server system. In at least one embodiment, computer system 800 may be a multiprocessor system. In at least one embodiment, the processor 802 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, and the processor bus 810 may be between the processor 802 and a computerData signals are transmitted between other components in the system 800.

In at least one embodiment, the processor 802 may include, but is not limited to, a level 1 ("L1") internal cache ("cache") 804. In at least one embodiment, the processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 802. In at least one embodiment, the processor 802 may include a combination of internal and external caches. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

In at least one embodiment, an execution unit 808, including but not limited to logic to perform integer and floating point operations, is also located in the processor 802. The processor 802 may also include microcode ("ucode") read only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 808 may include logic to process the packed instruction set 809. In at least one embodiment, the encapsulated data in the general purpose processor 802 can be used to perform operations used by many multimedia applications by including the encapsulated instruction set 809 in the instruction set of the general purpose processor 802, along with the associated circuitry to execute the instructions. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by performing operations on encapsulated data using the full width of the processor's data bus, which may not require transferring smaller units of data over the processor's data bus to perform one or more operations on one data element at a time.

In at least one embodiment, the execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, the memory 820 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 820 may store instructions 819 and/or data 821 represented by data signals that may be executed by the processor 802.

In at least one embodiment, a system logic chip may be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 may communicate with the MCH 816 via a processor bus 810. In at least one embodiment, the MCH 816 may provide a high bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 may initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge the data signals between the processor bus 810, the memory 820, and the system I/O822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to memory 820 through a high bandwidth memory path 818, and the Graphics/video card 812 may be coupled to the MCH 816 through an Accelerated Graphics Port (AGP) interconnect 814.

In at least one embodiment, computer system 800 may use system I/O822 as a proprietary hub interface bus to couple MCH 816 to an I/O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connectivity to certain I/O devices through a local I/O bus. In at least one embodiment, the local I/O bus can include, but is not limited to, a high speed I/O bus for connecting peripheral devices to the memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a legacy I/O controller 823 and keyboard interface containing user input 825, a serial expansion port 827 (e.g., USB), and a network controller 834. Data storage 824 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment, FIG. 8 illustrates a system including interconnected hardware devices or "chips". In at least one embodiment, fig. 8 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in fig. 8 may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using a compute express link (CXL) interconnect.

FIG. 9 illustrates a system 900 in accordance with at least one embodiment. In at least one embodiment, the system 900 is an electronic device that utilizes the processor 910. In at least one embodiment, system 900 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a telephone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as I ²A C bus, a system management bus ("SMBus"), a Low Pin Count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (version 1, 2, 3), or a universal asynchronous receiver/transmitter ("UART") bus. In at least one embodiment, FIG. 9 illustrates a system that includes interconnected hardware devices or "chips". In at least one embodiment, fig. 9 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in figure 9 may be interconnected with a proprietary interconnect line, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of fig. 9 are interconnected using computational fast link (CXL) interconnect lines.

In at least one embodiment, fig. 9 may include a display 924, a touchscreen 925, a touchpad 930, a near field communication unit ("NFC") 945, a sensor hub 940, a thermal sensor 946, an express chipset ("EC") 935, a trusted platform module ("TPM") 938, BIOS/firmware/Flash memory ("BIOS, FW Flash") 922, a DSP960, a solid state disk ("SSD") or hard disk drive ("HDD") 920, a wireless local area network unit ("WLAN") 950, a bluetooth unit 952, a wireless wide area network unit ("WWAN") 956, a Global Positioning System (GPS)955, a camera ("USB 3.0 camera") 954 (e.g., a USB 3.0 camera), or a low power double data rate ("LPDDR") memory unit ("LPDDR 35915") implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components discussed above. In at least one embodiment, an accelerometer 941, an ambient light sensor ("ALS") 942, a compass 943, and a gyroscope 944 can be communicatively coupled to the sensor hub 940. In at least one embodiment, thermal sensor 939, fan 937, keyboard 946, and touchpad 930 may be communicatively coupled to EC 935. In at least one embodiment, a speaker 963, an earphone 964, and a microphone ("mic") 965 can be communicatively coupled to the audio unit ("audio codec and class D amplifier") 964, which in turn can be communicatively coupled to the DSP 960. In at least one embodiment, audio unit 964 may include, for example, but not limited to, an audio coder/decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, the components, such as WLAN unit 950 and bluetooth unit 952, and WWAN unit 956, may be implemented as a Next Generation Form Factor (NGFF).

Fig. 10 illustrates an example integrated circuit 1000 in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1000 is a SoC, which may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1000 includes one or more application processors 1005 (e.g., CPUs), at least one graphics processor 1010, and may additionally include an image processor 1015 and/or a video processor 1020, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1000 includes peripheral or bus logic including USB controller 1025, UART controller 10 30. SPI/SDIO controllers 1035 and I²S/I²C controller 1040. In at least one embodiment, integrated circuit 1000 may include a display device 1045 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1050 and a Mobile Industrial Processor Interface (MIPI) display interface 1055. In at least one embodiment, storage may be provided by flash subsystem 1060, including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via the memory controller 1065 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1070.

FIG. 11 illustrates a computing system 1100 in accordance with at least one embodiment. In at least one embodiment, the computing system 1100 includes a processing subsystem 1101 having one or more processors 1102 and a system memory 1104 in communication via an interconnection path that may include a memory hub 1105. In at least one embodiment, the memory hub 1105 may be a separate component within a chipset component or may be integrated within one or more processors 1102. In at least one embodiment, the memory hub 1105 is coupled to the I/O subsystem 1111 via a communication link 1106. In at least one embodiment, I/O subsystem 1111 includes an I/O hub 1107, which may enable computing system 1100 to receive input from one or more input devices 1108. In at least one embodiment, the I/O hub 1107 may enable a display controller, included in the one or more processors 1102, to provide output to one or more display devices 1110A. In at least one embodiment, the one or more display devices 1110A coupled with I/O hub 1107 may include local, internal, or embedded display devices.

In at least one embodiment, the processing subsystem 1101 includes one or more parallel processors 1112 coupled to a memory hub 1105 via a bus or other communication link 1113. In at least one embodiment, the communication link 1113 may be one of many standards-based communication link technologies or protocols, such as but not limited to PCIe, or may be a communication interface or communication fabric for a vendor. In at least one embodiment, the one or more parallel processors 1112 form a compute-centric parallel or vector processing system that may include a large number of processing cores and/or processing clusters, such as Multiple Integrated Core (MIC) processors. In at least one embodiment, the one or more parallel processors 1112 form a graphics processing subsystem that can output pixels to one of one or more display devices 1110A coupled via I/O hub 1107. In at least one embodiment, the one or more parallel processors 1112 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1110B.

In at least one embodiment, a system storage unit 1114 may be connected to I/O hub 1107 to provide a storage mechanism for computing system 1100. In at least one embodiment, I/O switch 1116 may be used to provide an interface mechanism to enable connection between I/O hub 1107 and other components, such as network adapter 1118 and/or wireless network adapter 1119, which may be integrated into the platform, as well as various other devices that may be added through one or more additional devices 1120. In at least one embodiment, the network adapter 1118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1119 may comprise one or more of Wi-Fi, Bluetooth, NFC, or other network device comprising one or more radios.

In at least one embodiment, computing system 1100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I/O hub 1107. In at least one embodiment, the communication paths interconnecting the various components in FIG. 11 may be implemented using any suitable protocol, such as a PCI (peripheral component interconnect) -based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocols (e.g., NVLink high speed interconnect or interconnect protocol).

In at least one embodiment, one or more parallel processors 1112 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 1112 include circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 1100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more of parallel processor 1112, memory hub 1105, processor 1102, and I/O hub 1107 may be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1100 may be integrated into a single package to form a System In Package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1100 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I/O subsystem 1111 and the display device 1110B are omitted from the computing system 1100.

Processing system

The following figures set forth, but are not limited to, an exemplary processing system that can be used to implement at least one embodiment.

FIG. 12 illustrates an accelerated processing unit ("APU") 1200 in accordance with at least one embodiment. In at least one embodiment, APU 1200 is developed by AMD, Inc. of Santa Clara, Calif. In at least one embodiment, APU 1200 can be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU 1200 includes, but is not limited to, core complex 1210, graphics complex 1240, fabric 1260, I/O interfaces 1270, memory controller 1280, display controller 1292, and multimedia engine 1294. In at least one embodiment, APU 1200 can include, but is not limited to, any combination of any number of core complexes 1210, any number of graphics complexes 1240, any number of display controllers 1292, and any number of multimedia engines 1294. For purposes of illustration, various instances of like objects are referred to herein by reference numerals, wherein the reference numerals identify the object and numerals in parentheses identify the required instances.

In at least one embodiment, core complex 1210 is a CPU, graphics complex 1240 is a GPU, and APU 1200 is a processing unit that will not be limited to 1210 and 1240 being integrated onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1210 while other tasks may be assigned to the graphics complex 1240. In at least one embodiment, core complex 1210 is configured to execute primary control software, such as an operating system, associated with APU 1200. In at least one embodiment, core complex 1210 is the main processor of APU 1200, which controls and coordinates the operation of the other processors. In at least one embodiment, the core complex 1210 issues commands that control the operation of the graphics complex 1240. In at least one embodiment, the core complex 1210 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1240 may be configured to execute device executable code derived from CUDA source code.

In at least one embodiment, core complex 1210 includes, but is not limited to, cores 1220(1) -1220(4) and L3 cache 1230. In at least one embodiment, core complex 1210 may include, but is not limited to, any number of cores 1220 and any combination of any number and type of caches. In at least one embodiment, core 1220 is configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1220 is a CPU core.

In at least one embodiment, each core 1220 includes, but is not limited to, a fetch/decode unit 1222, an integer execution engine 1224, a floating point execution engine 1226, and an L2 cache 1228. In at least one embodiment, the fetch/decode unit 1222 fetches instructions, decodes the instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1224 and the floating point execution engine 1226. In at least one embodiment, the fetch/decode unit 1222 may simultaneously dispatch one microinstruction to the integer execution engine 1224 and another microinstruction to the floating point execution engine 1226. In at least one embodiment, integer execution engine 1224 performs operations that are not limited to integer and memory operations. In at least one embodiment, floating point engine 1226 performs operations that are not limited to floating point and vector operations. In at least one embodiment, the fetch-decode unit 1222 dispatches the microinstructions to a single execution engine that replaces both the integer execution engine 1224 and the floating point execution engine 1226.

In at least one embodiment, each core 1220(i) may access an L2 cache 1228(i) included in core 1220(i), where i is an integer representing a particular instance of core 1220. In at least one embodiment, each core 1220 included in core complex 1210(j) is coupled to other cores 1220 included in core complex 1210(j) via an L3 cache 1230(j) included in core complex 1210(j), where j is an integer representing a particular instance of core complex 1210. In at least one embodiment, a core 1220 included in core complex 1210(j) may access all L3 caches 1230(j) included in core complex 1210(j), where j is an integer representing a particular instance of core complex 1210. In at least one embodiment, L3 cache 1230 may include, but is not limited to, any number of slices (slices).

In at least one embodiment, the graphics complex 1240 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1240 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1240 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1240 is configured to perform graphics-related operations and graphics-independent operations.

In at least one embodiment, the graphics complex 1240 includes, but is not limited to, any number of compute units 1250 and an L2 cache 1242. In at least one embodiment, computing units 1250 share an L2 cache 1242. In at least one embodiment, the L2 cache 1242 is partitioned. In at least one embodiment, the graphics complex 1240 includes, but is not limited to, any number of compute units 1250 and any number (including zero) and type of caches. In at least one embodiment, the graphics complex 1240 includes, but is not limited to, any number of dedicated graphics hardware.

In at least one embodiment, each compute unit 1250 includes, but is not limited to, any number of SIMD units 1252 and shared memory 1254. In at least one embodiment, each SIMD unit 1252 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1250 may execute any number of thread blocks, but each thread block executes on a single compute unit 1250. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, the workgroup is a thread block. In at least one embodiment, each SIMD unit 1252 executes a different thread bundle (warp). In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), where each thread in the thread bundle belongs to a single thread block and is configured to process different sets of data based on a single set of instructions. In at least one embodiment, prediction (prediction) may be used to disable one or more threads in a thread bundle. In at least one embodiment, the channel is a thread. In at least one embodiment, the work items are threads. In at least one embodiment, the wavefront is a thread bundle. In at least one embodiment, the different wavefronts in the thread blocks can be synchronized together and communicated via the shared memory 1254.

In at least one embodiment, fabric 1260 is a system interconnect that facilitates data and control transfers across core complex 1210, graphics complex 1240, I/O interfaces 1270, memory controller 1280, display controller 1292, and multimedia engine 1294. In at least one embodiment, APU 1200 may include, but is not limited to, any number and type of system interconnects, in addition to or in lieu of structure 1260, which structure 1260 facilitates data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1200. In at least one embodiment, I/O interface 1270 represents any number and type of I/O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interface 1270. In at least one embodiment, peripheral devices coupled to the I/O interface 1270 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, and the like.

In at least one embodiment, the display controller AMD92 displays images on one or more display devices, such as Liquid Crystal Display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits such as a video decoder, a video encoder, an image signal processor, and the like. In at least one embodiment, memory controller 1280 facilitates the transfer of data between APU 1200 and unified system memory 1290. In at least one embodiment, the core complex 1210 and the graphics complex 1240 share unified system memory 1290.

In at least one embodiment, APU 1200 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1280 and memory devices (e.g., shared memory 1254) that may be dedicated to one component or shared among multiple components. And (6) assembling. In at least one embodiment, APU 1200 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1328, L3 cache 1230, and L2 cache 1242), each of which may be component private or shared among any number of components (e.g., core 1220, core complex 1210, SIMD unit 1252, compute unit 1250, and graphics complex 1240).

Fig. 13 illustrates a CPU 1300 according to at least one embodiment. In at least one embodiment, CPU 1300 was developed by AMD corporation of Santa Clara, Calif. In at least one embodiment, CPU 1300 may be configured to execute application programs. In at least one embodiment, CPU 1300 is configured to execute primary control software, such as an operating system. In at least one embodiment, CPU 1300 issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU 1300 may be configured to execute host executable code derived from CUDA source code, and an external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 1300 includes, but is not limited to, any number of core complexes 1310, fabric 1360, I/O interfaces 1370, and memory controller 1380.

In at least one embodiment, core complex 1310 includes, but is not limited to, cores 1320(1) -1320(4) and L3 cache 1330. In at least one embodiment, core complex 1310 may include, but is not limited to, any number of cores 1320 and any combination of any number and type of caches. In at least one embodiment, core 1320 is configured to execute instructions of a particular ISA. In at least one embodiment, each core 1320 is a CPU core.

In at least one embodiment, each core 1320 includes, but is not limited to, a fetch/decode unit 1322, an integer execution engine 1324, a floating point execution engine 1326, and an L2 cache 1328. In at least one embodiment, the fetch/decode unit 1322 fetches instructions, decodes the instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1324 and the floating point execution engine 1326. In at least one embodiment, the fetch/decode unit 1322 may dispatch one micro instruction to the integer execution engine 1324 and another micro instruction to the floating point execution engine 1326 concurrently. In at least one embodiment, the integer execution engine 1324 performs operations that are not limited to integer and memory operations. In at least one embodiment, the floating point engine 1326 performs operations that are not limited to floating point and vector operations. In at least one embodiment, the fetch-decode unit 1322 dispatches the microinstructions to a single execution engine that replaces both the integer execution engine 1324 and the floating point execution engine 1326.

In at least one embodiment, each core 1320(i) may access an L2 cache 1328(i) included in core 1320(i), where i is an integer representing a particular instance of core 1320. In at least one embodiment, each core 1320 included in core complex 1310(j) is connected to other cores 1320 in core complex 1310(j) via an L3 cache 1330(j) included in core complex 1310(j), where j is an integer representing a particular instance of core complex 1310. In at least one embodiment, cores 1320 included in core complex 1310(j) may access all L3 caches 1330(j) included in core complex 1310(j), where j is an integer representing a particular instance of core complex 1310. In at least one embodiment, the L3 cache 1330 may include, but is not limited to, any number of slices.

In at least one embodiment, fabric 1360 is a system interconnect that facilitates data and control transfers across core complex 1310(1) -1310(N) (where N is an integer greater than zero), I/O interfaces 1370, and memory controller 1380. In at least one embodiment, CPU 1300 may include, but is not limited to, any number and type of system interconnects in addition to or in place of structure 1360, which structure 1360 facilitates data and control transfer across any number and type of directly or indirectly linked components that may be internal or external to CPU 1300. In at least one embodiment, I/O interface 1370 represents any number and type of I/O interfaces (e.g., PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interface 1370. In at least one embodiment, peripheral devices coupled to the I/O interface 1370 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

In at least one embodiment, memory controller 1380 facilitates data transfer between CPU 1300 and system memory 1390. In at least one embodiment, the core complex 1310 and the graphics complex 1340 share system memory 1390. In at least one embodiment, CPU 1300 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1380 and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1300 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1328 and L3 cache 1330), each of which may be component private or shared among any number of components (e.g., core 1320 and core complex 1310).

Fig. 14 illustrates an exemplary accelerator integration slice 1490 in accordance with at least one embodiment. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of a plurality of graphics processing engines, such as a plurality of graphics acceleration modules. The graphics processing engines may each include a separate GPU. Alternatively, the graphics processing engines may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general purpose package, line card, or chip.

An application effective address space 1482 within the system memory 1414 stores a process element 1483. In one embodiment, the process element 1483 is stored in response to a GPU call 1481 from an application 1480 executing on the processor 1407. The process element 1483 includes the processing state of the corresponding application 1480. The Work Descriptor (WD)1484 contained in the process element 1483 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1484 is a pointer to a queue of job requests in application effective address space 1482.

The graphics acceleration module 1446 and/or the various graphics processing engines may be shared by all or a portion of the processes in the system. In at least one embodiment, an infrastructure for establishing processing state and sending WD 1484 to graphics acceleration module 1446 to begin operations in the virtualized environment may be included.

In at least one embodiment, a dedicated process programming model is implementation specific. In this model, a single process owns either the graphics acceleration module 1446 or an individual graphics processing engine. Since graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integrated circuits for the owning partition, and the operating system initializes the accelerator integrated circuits for the owning partition when graphics acceleration module 1446 is allocated.

In operation, the WD acquisition unit 1491 in the accelerator integration slice 1490 acquires the next WD 1484 that includes an indication of work to be done by one or more graphics processing engines of the graphics acceleration module 1446. Data from WD 1484 may be stored in registers 1445 for use by Memory Management Unit (MMU)1439, interrupt management circuitry 1447, and/or context management circuitry 1448 as shown. For example, one embodiment of the MMU 1439 includes segment/page walk circuitry for accessing segment/page tables 1486 within the OS virtual address space 1485. The interrupt management circuit 1447 may process interrupt events (INT)1492 received from the graphics acceleration module 1446. When performing graphics operations, effective addresses 1493 generated by the graphics processing engine are translated to real addresses by the MMU 1439.

In one embodiment, the same register set 1445 is replicated for each graphics processing engine and/or graphics acceleration module 1446 and may be initialized by a hypervisor or operating system. Each of these copied registers may be contained in the accelerator integration slice 1490. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

TABLE 1 hypervisor initialized registers

1	Slice control register
		2	Real Address (RA) planned processing region pointer
3	Authorization mask override register
		4	Interrupt vector table input offset
5	Interrupt vector table entry restriction
		6	Status register
7	Logical partition ID
		8	Real Address (RA) hypervisor accelerator utilization record pointer
9	Storage description register

Exemplary registers that may be initialized by the operating system are shown in table 2.

TABLE 2 operating System initialization register

In one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and/or a particular graphics processing engine. It contains all the information needed by the graphics processing engine to do or work, or it may be a pointer to a memory location where the application establishes a command queue for the work to be completed.

Fig. 15A-15B illustrate an exemplary graphics processor according to at least one embodiment herein. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores. In at least one embodiment, an exemplary graphics processor is used within a SoC.

Fig. 15A illustrates an exemplary graphics processor 1510 of an SoC integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment. Fig. 15B illustrates an additional exemplary graphics processor 1540 of a SoC integrated circuit, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor 1510 of FIG. 15A is a low power graphics processor core. In at least one embodiment, graphics processor 1540 of fig. 15B is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 can be a variation of graphics processor 1010 of fig. 10.

In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D-1515N-1, and 1515N). In at least one embodiment, graphics processor 1510 may execute different shader programs via separate logic, such that vertex processor 1505 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, vertex processor 1505 performs the vertex processing stages of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1515A-1515N use the primitives and vertex data generated by the vertex processor 1505 to generate frame buffers for display on the display device. In at least one embodiment, the fragment processors 1515A-1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations to pixel shader programs provided in the Direct 3D API.

In at least one embodiment, graphics processor 1510 additionally includes one or more MMUs 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual to physical address mapping for a graphics processor 1510, including for a vertex processor 1505 and/or fragment processors 1515A-1515N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1005, image processors 1015, and/or video processors 1020 of FIG. 10, such that each processor 1005-1020 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to connect with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

In at least one embodiment, graphics processor 1540 includes one or more MMUs 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B of graphics processor 1510 of FIG. 15A. In at least one embodiment, graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F, through 1555N-1, and 1555N) that provide a unified shader core architecture in which a single core or type or core may execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1555A-1555N and blocking unit 1558 to accelerate block operations based on tile rendering, where rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage.

FIG. 16A illustrates a graphics core 1600 in accordance with at least one embodiment. In at least one embodiment, graphics core 1600 may be included within graphics processor 1010 of FIG. 10. In at least one embodiment, graphics core 1600 may be a unified shader core 1555A-1555N of FIG. 15B. In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, texture unit 1618, and cache/shared memory 1620, which are common to the execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices (slices) 1601A-1601N or partitions per core, and a graphics processor may include multiple instances of graphics core 1600. The slices 1601A-1601N may include support logic that includes local instruction caches 1604A-1604N, thread schedulers 1606A-1606N, thread dispatchers 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of Additional Functional Units (AFUs) 1612A-1612N, Floating Point Units (FPUs) 1614A-1614N, integer Arithmetic Logic Units (ALUs) 1616A-1616N, Address Calculation Units (ACUs) 1613A-1613N, Double Precision Floating Point Units (DPFPUs) 1615A-1615N, and Matrix Processing Units (MPUs) 1617A-1617N.

In one embodiment, FPUs 1614A-1614N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1615A-1615N may perform double-precision (64-bit) floating-point operation-point operations. In at least one embodiment, the ALUs 1616A-1616N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision, and may be configured for mixed precision operations. In at least one embodiment, the MPUs 1617A-1617N may also be configured for mixed precision matrix operations, including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1617A-1617N may perform various matrix operations to accelerate the CUDA program, including generic matrix-to-matrix multiplication (GEMM) to enable support for acceleration. In at least one embodiment, AFU 1612A-1612N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

FIG. 16B illustrates a General Purpose Graphics Processing Unit (GPGPU)1630 in at least one embodiment. In at least one embodiment, GPGPU1630 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU1630 may be configured to enable highly parallel computing operations to be performed by the GPU array. In at least one embodiment, GPGPU1630 may be directly linked to other instances of GPGPU1630 to create multi-GPU clusters to increase execution time for CUDA programs. In at least one embodiment, GPGPU1630 includes a host interface 1632 to enable connection with a host processor. In at least one embodiment, host interface 1632 is a PCIe interface. In at least one embodiment, host interface 1632 may be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU1630 receives commands from a host processor and dispatches the execution threads associated with those commands to a set of compute clusters 1636A-1636H using global scheduler 1634. In at least one embodiment, compute clusters 1636A-1636H share cache memory 1638. In at least one embodiment, cache memory 1638 may be used as a high level cache for cache memory within compute clusters 1636A-1636H.

In at least one embodiment, GPGPU1630 includes memory 1644A-1644B coupled with compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memories 1644A-1644B may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory.

In at least one embodiment, compute clusters 1636A-1636H each include a set of graphics cores, such as graphics core 1600 of FIG. 16A, which may include various types of integer and floating point logic units that may perform compute operations at various precisions, including computations suitable for use in connection with a CUDA program. For example, in at least one embodiment, at least a subset of the floating point units in each compute cluster 1636A-1636H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units may be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU1630 may be configured to operate as a compute cluster. Compute clusters 1636A-1636H may implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU1630 communicate through host interface 1632. In at least one embodiment, GPGPU1630 includes an I/O hub 1639 that couples GPGPU1630 with a GPU link 1640 that enables direct connections to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled with a high speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU1630 are located in separate data processing systems and communicate via network devices accessible via host interface 1632. In at least one embodiment, GPU link 1640 may be configured to be capable of connecting to a host processor in addition to or instead of host interface 1632. In at least one embodiment, GPGPU1630 may be configured to execute CUDA programs.

FIG. 17A illustrates a parallel processor 1700 according to at least one embodiment. In at least one embodiment, the various components of parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or an FPGA.

In at least one embodiment, parallel processor 1700 includes parallel processing units 1702. In at least one embodiment, parallel processing unit 1702 includes an I/O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I/O unit 1704 may be directly connected to other devices. In at least one embodiment, the I/O unit 1704 interfaces with other devices using a hub or switch interface (e.g., memory hub 1705). In at least one embodiment, the connection between the memory hub 1705 and the I/O unit 1704 forms a communication link. In at least one embodiment, the I/O unit 1704 interfaces with a host interface 1706 and a memory crossbar 1716, wherein the host interface 1706 receives commands for performing processing operations and the memory crossbar 1716 receives commands for performing memory operations.

In at least one embodiment, when the host interface 1706 receives command buffers via the I/O unit 1704, the host interface 1706 may direct work operations to execute those commands to the front end 1708. In at least one embodiment, the front end 1708 is coupled with a scheduler 1710, the scheduler 1710 configured to assign commands or other work items to the processing array 1712. In at least one embodiment, scheduler 1710 ensures that processing array 1712 is properly configured and in a valid state before allocating a task to processing array 1712 in processing array 1712. In at least one embodiment, the scheduler 1710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 may be configured to perform complex scheduling and work allocation operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1712. In at least one embodiment, the host software may attest to the workload for scheduling on the processing array 1712 by one of the plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically allocated on the processing array 1712 by scheduler 1710 logic within the microcontroller that includes the scheduler 1710.

In at least one embodiment, processing array 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing array 1712 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 may assign jobs to the clusters 1714A-1714N of the processing array 1712 using various scheduling and/or job assignment algorithms, which may vary depending on the workload generated by each program or computing type. In at least one embodiment, the scheduling may be dynamically handled by the scheduler 1710 or may be partially assisted by compiler logic during compilation of program logic configured for execution by the processing array 1712. In at least one embodiment, different clusters 1714A-1714N of processing array 1712 may be assigned for processing different types of programs or for performing different types of computations.

In at least one embodiment, the processing array 1712 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 1712 is configured to perform general purpose parallel computing operations. For example, in at least one embodiment, the processing array 1712 may include logic to perform processing tasks including filtering of video and/or audio data, performing modeling operations, including physical operations, and performing data transformations.

In at least one embodiment, the processing array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1712 may include additional logic to support the performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1702 may transfer data from system memory for processing via I/O unit 1704. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 1722) and then written back to system memory during processing.

In at least one embodiment, when parallel processing unit 1702 is used to perform graph processing, scheduler 1710 may be configured to divide the processing workload into approximately equally sized tasks to better allocate graphics processing operations to the multiple clusters 1714A-1714N of processing array 1712. In at least one embodiment, portions of processing array 1712 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1714A-1714N may be stored in a buffer to allow the intermediate data to be transmitted between the clusters 1714A-1714N for further processing.

In at least one embodiment, the processing array 1712 may receive processing tasks to be executed via a scheduler 1710, which scheduler 1710 receives commands defining the processing tasks from the front end 1708. In at least one embodiment, the processing task may include an index of data to be processed, which may include, for example, surface (patch) data, raw data, vertex data, and/or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1710 may be configured to obtain an index corresponding to a task, or may receive an index from the front end 1708. In at least one embodiment, the front end 1708 may be configured to ensure that the processing array 1712 is configured to a valid state prior to launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

In at least one embodiment, each of the one or more instances of parallel processing unit 1702 may be coupled with a parallel processor memory 1722. In at least one embodiment, the parallel processor memory 1722 may be accessed via a memory crossbar 1716, which memory crossbar 1716 may receive memory requests from the processing array 1712 and the I/O unit 1704. In at least one embodiment, the memory crossbar 1716 may access the parallel processor memory 1722 via the memory interface 1718. In at least one embodiment, memory interface 1718 may include a plurality of partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), which may each be coupled to a portion (e.g., a memory unit) of parallel processor memory 1722. In at least one embodiment, the plurality of partition units 1720A-1720N are configured to equal the number of memory units, such that a first partition unit 1720A has a corresponding first memory unit 1724A, a second partition unit 1720B has a corresponding memory unit 1724B, and an Nth partition unit 1720N has a corresponding Nth memory unit 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not equal the number of memory devices.

In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be eliminated in favor of a unified memory design that utilizes system memory in combination with local cache memory.

In at least one embodiment, any of the clusters 1714A-1714N of processing array 1712 may process data to be written into any of memory units 1724A-1724N within parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 may be configured to transmit the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N on which the clusters 1714A-1714N may perform other processing operations. In at least one embodiment, each cluster 1714A-1714N may communicate with the memory interface 1718 through the memory crossbar 1716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1716 has a connection to memory interface 1718 to communicate with I/O unit 1704 and to a local instance of parallel processor memory 1722 so that processing units within different processing clusters 1714A-1714N communicate with system memory or other memory not local to parallel processing unit 1702. In at least one embodiment, memory crossbar 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

In at least one embodiment, multiple instances of the parallel processing unit 1702 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 may be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and/or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1702 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 1702 or parallel processor 1700 may be implemented in various configurations and form factors, including but not limited to a desktop, laptop or handheld personal computer, server, workstation, gaming console, and/or embedded system.

Fig. 17B illustrates a processing cluster 1794 in accordance with at least one embodiment. In at least one embodiment, processing cluster 1794 is included within a parallel processing unit. In at least one embodiment, processing cluster 1794 is an instance of one of processing clusters 1714A-1714N of FIG. 17A. In at least one embodiment, processing cluster 1794 may be configured to execute a number of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) techniques are used to support parallel execution of a large number of generally simultaneous threads, using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster 1794.

In at least one embodiment, the operation of the processing cluster 1794 may be controlled by a pipeline manager 1732 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 1732 receives instructions from scheduler 1710 of FIG. 17A, and manages execution of these instructions by graphics multiprocessor 1734 and/or texture unit 1736. In at least one embodiment, graphics multiprocessor 1734 is an illustrative example of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within processing cluster 1794. In at least one embodiment, one or more instances of graphics multiprocessor 1734 may be included within processing cluster 1794. In at least one embodiment, graphics multiprocessor 1734 may process data, and data crossbar 1740 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1732 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 1740.

In at least one embodiment, each graphics multiprocessor 1734 within processing cluster 1794 may include the same set of function execution logic (e.g., arithmetic logic unit, Load Store Unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, wherein a new instruction may be issued before a previous instruction completes. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shifting, and computation of various algebraic functions. In at least one embodiment, different operations may be performed by the same functional unit hardware, and any combination of functional units may be present.

In at least one embodiment, the instructions transmitted to the processing cluster 1794 constitute a thread. In at least one embodiment, the set of threads executing across a set of parallel processing engines is a thread set. In at least one embodiment, the thread groups execute programs on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within graphics multiprocessor 1734. In at least one embodiment, the thread groups may include fewer threads than multiple processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during a cycle in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than multiple processing engines within graphics multiprocessor 1734. In at least one embodiment, processing may be performed in consecutive clock cycles when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, multiple thread groups may be executing concurrently on graphics multiprocessor 1734.

In at least one embodiment, graphics multiprocessor 1734 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1734 may relinquish internal caching and use cache memory within processing cluster 1794 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 can also access an L2 cache within partition units (e.g., partition units 1720A-1720N of FIG. 17A) that are shared among all processing clusters 1794 and that can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 may also access off-chip global memory, which may include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to the parallel processing unit 1702 may be used as global memory. In at least one embodiment, processing cluster 1794 includes multiple instances of graphics multiprocessor 1734, which may share common instructions and data, which may be stored in L1 cache 1748.

In at least one embodiment, each processing cluster 1794 may include an MMU1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU1745 may reside within memory interface 1718 of fig. 17A. In at least one embodiment, MMU1745 includes a set of Page Table Entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (discussing more information about tiles) and optionally to cache line indices. In at least one embodiment, MMU1745 may include an address Translation Lookaside Buffer (TLB) or cache that may reside within graphics multiprocessor 1734 or L1 cache 1748 or processing cluster 1794. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

In at least one embodiment, processing cluster 1794 may be configured such that each graphics multiprocessor 1734 is coupled to texture unit 1736 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from L1 cache within graphics multiprocessor 1734, and fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to data crossbar 1740 to provide processed tasks to another processing cluster 1794 for further processing or to store processed tasks in L2 cache, local parallel processor memory, or system memory via memory crossbar 1716. In at least one embodiment, a pre-raster operations unit (preROP)1742 is configured to receive data from the graphics multiprocessor 1734, direct the data to a ROP unit, which may be located with the partition units described herein (e.g., the partition units 1720A-1720N of FIG. 17A). In at least one embodiment, the PreROP1742 unit may perform optimizations for color mixing, organize pixel color data, and perform address translations.

Fig. 17C illustrates a graphics multiprocessor 1796 in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 1796 is graphics multiprocessor 1734 of fig. 17B. In at least one embodiment, graphics multiprocessor 1796 is coupled with pipeline manager 1732 of processing cluster 1794. In at least one embodiment, the graphics multiprocessor 1796 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more GPGPU cores 1762, and one or more LSUs 1766. The GPGPU core 1762 and LSU 1766 are coupled with cache memory 1772 and shared memory 1770 through a memory and cache interconnect 1768.

In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In one embodiment, the instruction unit 1754 may dispatch instructions as thread groups (e.g., thread bundles), with each thread of a thread group being assigned to a different execution unit within the GPGPU core 1762. In at least one embodiment, an instruction may access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 may be used to translate addresses in the unified address space to different memory addresses that may be accessed by the LSU 1766.

In at least one embodiment, the register file 1758 provides a set of registers for the functional units of the graphics multiprocessor 1796. In at least one embodiment, the register file 1758 provides temporary storage for operands connected to the datapaths of the functional units of the graphics multiprocessor 1796 (e.g., GPGPU cores 1762, LSU 1766). In at least one embodiment, register file 1758 is divided among each functional unit such that a dedicated portion of register file 1758 is allocated for each functional unit. In at least one embodiment, the register file 1758 is divided among different thread groups that the graphics multiprocessor 1796 is executing.

In at least one embodiment, the GPGPU cores 1762 may each include an FPU and/or an ALU for executing instructions of the graphics multiprocessor 1796. The GPGPU core 1762 may be similar in architecture or may differ in architecture. In at least one embodiment, the first portion of the GPGPU core 1762 includes single precision FPUs and integer ALUs, while the second portion of the GPGPU core includes double precision FPUs. In at least one embodiment, the FPU may implement the IEEE 754-. In at least one embodiment, the graphics multiprocessor 1796 can additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1762 may also include fixed or special function logic.

In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1762 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network that connects each functional unit of the graphics multiprocessor 1796 to the register file 1758 and the shared memory 1770. In at least one embodiment, memory and cache interconnect 1768 is a crossbar interconnect that allows LSU 1766 to implement load and store operations between shared memory 1770 and register file 1758. In at least one embodiment, register file 1758 may operate at the same frequency as GPGPU core 1762, so that the latency of data transfers between GPGPU core 1762 and register file 1758 is very low. In at least one embodiment, the shared memory 1770 may be used to enable communication between threads executing on functional units within the graphics multiprocessor 1796. In at least one embodiment, the cache memory 1772 may function as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1736. In at least one embodiment, the shared memory 1770 can also serve as a cache for program management. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 1772, a thread executing on the GPGPU core 1762 may also programmatically store data in shared memory.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor/core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPUs are connected, the processor cores may allocate work to the GPUs in the form of a sequence of commands/instructions contained by the WD. In at least one embodiment, the GPU then uses special-purpose circuitry/logic to efficiently process these commands/instructions.

FIG. 18 illustrates a graphics processor 1800 in accordance with at least one embodiment. In at least one embodiment, graphics processor 1800 includes ring interconnect 1802, pipeline front end 1804, media engine 1837, and graphics cores 1880A-1880N. In at least one embodiment, the ring interconnect 1802 couples the graphics processor 1800 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, the graphics processor 1800 is one of many processors integrated within a multi-core processing system.

In at least one embodiment, the graphics processor 1800 receives multiple batches of commands via the ring interconnect 1802. In at least one embodiment, the input commands are interpreted by a command streamer 1803 in the pipeline front end 1804. In at least one embodiment, graphics processor 1800 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1803 provides the commands to the geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, command streamer 1803 provides the commands to video front end 1834, which is coupled to media engine 1837. In at least one embodiment, the media engines 1837 include a Video Quality Engine (VQE)1830 for video and image post-processing, and a multi-format encode/decode (MFX)1833 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 1836 and media engine 1837 each generate execution threads for thread execution resources provided by at least one graphics core 1880A.

In at least one embodiment, the graphics processor 1800 includes scalable thread execution resources featuring modular graphics cores 1880A-1880N (sometimes referred to as core slices), each module core having multiple sub-cores 1850A-1850N, 1860A-1860N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1800 may have any number of graphics cores 1880A-1880N. In at least one embodiment, the graphics processor 1800 includes a graphics core 1880A having at least a first sub-core 1850A and a second sub-core 1860A. In at least one embodiment, graphics processor 1800 is a low power processor with a single sub-core (e.g., 1850A). In at least one embodiment, the graphics processor 1800 includes multiple graphics cores 1880A-1880N, each graphics core including a set of first sub-cores 1850A-1850N and a set of second sub-cores 1860A-1860N. In at least one embodiment, each of the first sub-cores 1850A-1850N includes at least a first set of Execution Units (EU)1852A-1852N and media/texture samplers 1854A-1854N. In at least one embodiment, each of the second sub-cores 1860A-1860N includes at least a second set of execution units 1862A-1862N and samplers 1864A-1864N. In at least one embodiment, each child core 1850A-1850N, 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

Fig. 19 illustrates a processor 1900 in accordance with at least one embodiment. In at least one embodiment, processor 1900 may include, but is not limited to, logic circuits to execute instructions. In at least one embodiment, the processor 1900 can execute instructions including x86 instructions, ARM instructions, special purpose instructions for ASICs, and the like. In at least one embodiment, processor 1910 can include registers for storing package data, such as a 64-bit wide MMXTM register in a microprocessor enabled with MMX technology by Intel corporation of Santa Clara, Calif. In at least one embodiment, MMX registers available in integer and floating point form may be run with packed data elements that accompany SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher version (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, processor 1910 can execute instructions to accelerate the CUAD program.

In at least one embodiment, the processor 1900 includes an in-order front end ("front end") 1901 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 1901 may include several cells. In at least one embodiment, the instruction prefetcher 1926 fetches instructions from memory and provides the instructions to the instruction decoder 1928, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 1928 decodes a received instruction for execution of one or more operations called "micro-instructions" or "micro-operations" (also referred to as "micro-operations" or "micro-instructions"). In at least one embodiment, the instruction decoder 1928 parses an instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations. In at least one embodiment, the trace cache 1930 can assemble decoded microinstructions into a program ordered sequence or trace in the microinstruction queue 1934 for execution. In at least one embodiment, the microcode ROM 1932 provides the microinstructions needed to complete the operation when the trace cache 1930 encounters a complex instruction.

In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, the instruction decoder 1928 may access the microcode ROM 1932 to execute an instruction if more than four microinstructions are needed to complete an instruction. In at least one embodiment, instructions may be decoded into a small number of microinstructions for processing at the instruction decoder 1928. In at least one embodiment, if multiple microinstructions are needed to complete an operation, the instructions may be stored in the microcode ROM 1932. In at least one embodiment, the trace cache 1930 references an entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading a micro-code sequence from the micro-code ROM 1932 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, the front end 1901 of the machine may resume fetching micro-operations from the trace cache 1930 after the microcode ROM 1932 completes ordering the micro-operations for the instruction.

In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 1903 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the stream of instructions to optimize performance as instructions descend down the pipeline and are scheduled to execute. The out-of-order execution engine 1903 includes, but is not limited to, a dispatcher/register renamer 1940, a memory microinstruction queue 1942, an integer/floating point microinstruction queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow/general floating point scheduler ("slow/general FP scheduler") 1904, and a simple floating point scheduler ("simple FP scheduler") 1906. In at least one embodiment, the fast scheduler 1902, the slow/general floating point scheduler 1904, and the simple floating point scheduler 1906 are also collectively referred to as "micro-instruction schedulers 1902, 1904, 1906". Allocator/register renamer 1940 allocates the machine buffers and resources required for sequential execution of each microinstruction. In at least one embodiment, allocator/register renamer 1940 renames logical registers to entries in a register file. In at least one embodiment, allocator/register renamer 1940 also allocates an entry for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 1942 for memory operations and an integer/floating point microinstruction queue 1944 for non-memory operations, in front of memory scheduler 1946 and microinstruction schedulers 1902, 1904, 1906. In at least one embodiment, the microinstruction schedulers 1902, 1904, 1906 determine when a microinstruction is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 1902 of at least one embodiment may schedule on each half of the host clock cycle, while the slow/general floating point scheduler 1904 and the simple floating point scheduler 1906 may schedule once per host processor clock cycle. In at least one embodiment, the micro-instruction schedulers 1902, 1904, 1906 arbitrate for scheduling ports for execution of micro-instructions.

In at least one embodiment, execution block 1911 includes, but is not limited to, integer register file/branch network 1908, floating point register file/branch network ("FP register file/branch network") 1910, address generation units ("AGUs") 1912 and 1914, fast arithmetic logic units ("fast ALUs") 1916 and 1918, slow ALU1920, floating point ALU ("FP") 1922, and floating point move unit ("FP move") 1924. In at least one embodiment, the integer register file/branch network 1908 and the floating point register file/bypass network 1910 are also referred to herein as "register files 1908, 1910". In at least one embodiment, AGUS 1912 and 1914, fast ALUs 1916 and 1918, slow ALU1920, floating point ALU 1922, and floating point move unit 1924 are also referred to herein as "execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924". In at least one embodiment, the execution blocks may include, but are not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

In at least one embodiment, the register files 1908, 1910 may be disposed between the microinstruction schedulers 1902, 1904, 1906 and the execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, the integer register file/branch network 1908 performs integer operations. In at least one embodiment, the floating point register file/tributary network 1910 performs floating point operations. In at least one embodiment, each of the register files 1908, 1910 can include, but is not limited to, a bypass network that can bypass or forward just completed results that have not yet been written to the register file to a new dependent object. In at least one embodiment, register files 1908, 1910 can communicate data with each other. In at least one embodiment, integer register file/bypass network 1908 may include, but is not limited to, two separate register files, one register file for the lower-order 32-bit data and a second register file for the higher-order 32-bit data. In at least one embodiment, the floating point register file/branch network 1910 may include, but is not limited to, 128-bit wide entries because floating point instructions typically have operands that are 64 to 128 bits in width.

In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924 may execute instructions. In at least one embodiment, the register files 1908, 1910 store integer and floating point data operand values that the microinstructions need to execute. In at least one embodiment, processor 1900 may include, but is not limited to, any number and combination of execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924. In at least one embodiment, the floating-point ALU 1922 and floating-point mobile unit 1924 may perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating-point ALU 1922 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform divide, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating point values may be processed with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 1916, 1918. In at least one embodiment, the fast ALUS 1916, 1918 may perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 1920 because the slow ALU 1920 may include, but is not limited to, integer execution hardware for long latency type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be performed by the AGUS 1912, 1914. In at least one embodiment, the fast ALU 1916, the fast ALU 1918, and the slow ALU 1920 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 1916, the fast ALU 1918, and the slow ALU 1920 may be implemented to support a variety of data bit sizes, including 16, 32, 128, 256, and so on. In at least one embodiment, the floating-point ALU 1922 and floating-point move unit 1924 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating-point ALU 1922 and floating-point move unit 1924 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, the microinstruction schedulers 1902, 1904, 1906 schedule dependent operations before the parent load completes execution. In at least one embodiment, the processor 1900 may also include logic to handle memory misses because microinstructions may be speculatively scheduled and executed in the processor 1900. In at least one embodiment, if a data load in the data cache misses, there may be dependent operations running in the pipeline that cause the scheduler to temporarily miss the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture a sequence of instructions for a text string comparison operation.

In at least one embodiment, the term "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify operands. In at least one embodiment, the registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuitry. Rather, in at least one embodiment, the registers may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using a number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and so forth. In at least one embodiment, the integer register stores 32 bits of integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

Fig. 20 illustrates a processor 2000 in accordance with at least one embodiment. In at least one embodiment, the processor 2000 includes, but is not limited to, one or more processor cores (cores) 2002A-2002N, an integrated memory controller 2014, and an integrated graphics processor 2008. In at least one embodiment, the processor 2000 may include additional cores up to and including an additional processor core 2002N, represented by a dashed box. In at least one embodiment, each processor core 2002A-2002N includes one or more internal cache units 2004A-2004N. In at least one embodiment, each processor core may also access one or more units of shared cache 2006.

In at least one embodiment, internal cache units 2004A-2004N and shared cache unit 2006 represent a cache memory hierarchy within processor 2000. In at least one embodiment, the cache memory units 2004A-2004N may include at least one level of instructions and data within each processor core and one or more levels of cache in a shared mid-level cache, such as a level L2, L3, level 4 (L4), or other level of cache, where the highest level of cache is categorized as LLC before external memory. In at least one embodiment, the cache coherency logic maintains coherency between the various cache units 2006 and 2004A-2004N.

In at least one embodiment, processor 2000 may also include a set of one or more bus controller units 2016 and a system agent core 2010. In at least one embodiment, one or more bus controller units 2016 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2010 provides management functions for various processor components. In at least one embodiment, the system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of the processor cores 2002A-2002N include support for simultaneous multithreading. In at least one embodiment, system agent core 2010 includes components for coordinating and operating processor cores 2002A-2002N during multi-threaded processing. In at least one embodiment, system agent core 2010 may additionally include a Power Control Unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2002A-2002N and graphics processor 2008.

In at least one embodiment, processor 2000 additionally includes a graphics processor 2008 to perform graph processing operations. In at least one embodiment, the graphics processor 2008 is coupled with a shared cache unit 2006 and a system agent core 2010 including one or more integrated memory controllers 2014. In at least one embodiment, system agent core 2010 also includes a display controller 2011 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2011 may also be a stand-alone module coupled to graphics processor 2008 via at least one interconnect, or may be integrated within graphics processor 2008.

In at least one embodiment, ring-based interconnect unit 2012 is used to couple the internal components of processor 2000. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other techniques. In at least one embodiment, graphics processor 2008 is coupled with ring interconnect 2012 via an I/O link 2013.

In at least one embodiment, I/O link 2013 represents at least one of a variety of I/O interconnects, including a packaged I/O interconnect that facilitates communication between various processor components and high-performance embedded memory module 2018 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2002A-2002N and the graphics processor 2008 uses the embedded memory module 2018 as a shared LLC.

In at least one embodiment, processor cores 2002A-2002N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2002A-2002N are heterogeneous in ISA, in that one or more processor cores 2002A-2002N execute a common instruction set, while one or more other processor cores 2002A-2002N execute a common instruction set or a subset of different instruction sets. In at least one embodiment, processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, where one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, processor 2000 may be implemented on one or more chips or as an SoC integrated circuit.

Fig. 21 illustrates a graphics processor core 2100 in accordance with at least one embodiment described. In at least one embodiment, graphics processor core 2100 is included within a graphics core array. In at least one embodiment, graphics processor core 2100 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2100 is an example of one graphics core slice, and a graphics processor described herein may include multiple graphics core slices based on target power and performance context. In at least one embodiment, each graphics core 2100 may include fixed function blocks 2130, also referred to as subslices, that include modular blocks of general and fixed function logic coupled to a plurality of sub-cores 2101A-2101F.

In at least one embodiment, the fixed function block 2130 includes a geometry/fixed function pipeline 2136, e.g., in lower performance and/or lower power graphics processor implementations, the geometry/fixed function pipeline 2136 may be shared by all of the sub-cores in the graphics processor 2100. In at least one embodiment, the geometry/fixed function pipeline 2136 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

In at least one embodiment, fixed function block 2130 also includes a graphics SoC interface 2137, a graphics microcontroller 2138, and a media pipeline 2139. Graphics SoC interface 2137 provides an interface between graphics core 2100 and other processor cores in an SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2138 is a programmable sub-processor that may be configured to manage various functions of graphics processor 2100, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 2139 includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing multimedia data including image and video data. In at least one embodiment, the media pipeline 2139 implements media operations via requests to computational or sampling logic within the sub-cores 2101-2101F.

In at least one embodiment, SoC interface 2137 enables graphics core 2100 to communicate with a general purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and/or embedded on-chip or packaged DRAM. In at least one embodiment, SoC interface 2137 may also enable communication with fixed-function devices (e.g., camera imaging pipelines) within the SoC and enable use and/or implementation of global memory atoms that may be shared between graphics core 2100 and CPUs internal to the SoC. In at least one embodiment, SoC interface 2137 may also implement power management control for graphics core 2100 and enable interfaces between the clock domains of graphics core 2100 and other clock domains within the SoC. In at least one embodiment, SoC interface 2137 enables receiving a command buffer from a command streamer and a global thread dispatcher, which is configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to the media pipeline 2139 when a media operation is to be performed or can be distributed to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 2136, the geometry and fixed function pipeline 2114) when a graph processing operation is to be performed.

In at least one embodiment, graphics microcontroller 2138 may be configured to perform various scheduling and management tasks for graphics core 2100. In at least one embodiment, the graphics microcontroller 2138 can execute graphics and/or compute workload scheduling on various graphics parallel engines within the Execution Unit (EU) arrays 2102A-2102F, 2104A-2104F in the sub-cores 2101A-2101F. In at least one embodiment, host software executing on a CPU core of a SoC including graphics core 2100 may submit a workload of one of a plurality of graphics processor doorbell, which invokes a scheduled operation on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload completes. In at least one embodiment, graphics microcontroller 2138 may also facilitate a low power or idle state for graphics core 2100, providing graphics core 2100 with the ability to save and restore registers across low power state transitions within graphics core 2100 independent of the operating system and/or graphics driver software on the system.

In at least one embodiment, graphics core 2100 may have more or fewer sub-cores than the illustrated sub-cores 2101A-2101F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2100 may also include shared function logic 2110, shared and/or cache memory 2112, geometry/fixed function pipeline 2114, and additional fixed function logic 2116 to accelerate various graphics and computing processing operations. In at least one embodiment, shared function logic 2110 may include logic units (e.g., samplers, math and/or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2100. The shared and/or cache memory 2112 may be an LLC of the N sub-cores 2101A-2101F within the graphics core 2100, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, a geometric/fixed function pipeline 2114 may be included in place of the geometric/fixed function pipeline 2136 within the fixed function block 2130 and may include the same or similar logic elements.

In at least one embodiment, graphics core 2100 includes additional fixed function logic 2116, which may include various fixed function acceleration logic for use by graphics core 2100. In at least one embodiment, the additional fixed function logic 2116 includes additional geometric pipelines for use in location-only shading. In position-only shading, there are at least two geometric pipelines, while among the full geometric pipelines and culling pipelines within the geometric/fixed function pipelines 2116, 2136, are additional geometric pipelines that may be included in additional fixed function logic 2116. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline may execute different instances of the application, each instance having a separate environment. In at least one embodiment, the location-only shading may hide long culling runs of discarded triangles so that shading may be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2116 may execute a position shader in parallel with the host application and typically generate critical results faster than a full pipeline, because the culling pipeline fetches and masks the position attributes of the vertices without performing rasterization and rendering the pixels to the frame buffer. In at least one embodiment, the culling pipeline may use the generated critical results to calculate visibility information for all triangles regardless of whether the triangles were culled. In at least one embodiment, the full pipeline (which in this case may be referred to as a replay pipeline) may consume visibility information to skip culled triangles to mask only the visible triangles that are ultimately passed to the rasterization stage.

In at least one embodiment, the additional fixed function logic 2116 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing a slow down CUAD program.

In at least one embodiment, a set of execution resources is included within each graphics sub-core 2101A-2101F that may be used to perform graphics, media, and compute operations in response to requests by a graphics pipeline, media pipeline, or shader program. In at least one embodiment, graphics sub-cores 2101A-2101F includes a plurality of EU arrays 2102A-2102F, 2104A-2104F, thread dispatch and inter-thread communication (TD/IC) logic 2103A-2103F, 3D (e.g., texture) samplers 2105A-2105F, media samplers 2106A-2106F, shader processors 2107A-2107F, and Shared Local Memory (SLM) 2108A-2108F. The EU arrays 2102A-2102F, 2104A-2104F each contain a plurality of execution units, which are GUGPUs, capable of servicing graphics, media, or computing operations, performing floating point and integer/fixed point logical operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD/IC logic 2103A-2103F performs local thread dispatch and thread control operations for execution units within the child core and facilitates communication between threads executing on the execution units of the child core. In at least one embodiment, 3D samplers 2105A-2105F may read data related to textures or other 3D graphics into memory. In at least one embodiment, the 3D sampler may read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2106A-2106F may perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2101A-2101F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2101A-2101F may utilize shared local memory 2108A-2108F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

FIG. 22 illustrates a parallel processing unit ("PPU") 2200 in accordance with at least one embodiment. In at least one embodiment, the PPU 2200 is configured with machine-readable code that, if executed by the PPU 2200, causes the PPU 2200 to perform some or all of the processes and techniques described throughout this document. In at least one embodiment, PPU 2200 is a multithreaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instance of a set of instructions configured to be executed by PPU 2200. In at least one embodiment, PPU 2200 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data in order to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2200 is used to perform computations, such as linear algebraic operations and machine learning operations. FIG. 22 shows an example parallel processor for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

In at least one embodiment, one or more PPUs 2200 are configured to accelerate high performance computing ("HPC"), data centers, and machine learning applications. In at least one embodiment, one or more PPUs 2200 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2200 includes, but is not limited to, I/O unit 2206, front end unit 2210, scheduler unit 2212, work allocation unit 2214, hub 2216, crossbar ("Xbar") 2220, one or more general purpose processing clusters ("GPCs") 2218, and one or more partition units ("memory partition units") 2222. In at least one embodiment, PPU 2200 is connected to a host processor or other PPU 2200 by one or more high-speed GPU interconnects ("GPU interconnect") 2208. In at least one embodiment, PPU 2200 is connected to a host processor or other peripheral device via interconnect 2202. In an embodiment, PPU 2200 is connected to local memory that includes one or more memory devices ("memory") 2204. In at least one embodiment, the memory device 2204 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as a high bandwidth memory ("HBM") subsystem, and multiple DRAM dies are stacked within each device.

In at least one embodiment, high-speed GPU interconnect 2208 may refer to a line-based, multi-channel communication link that a system uses for scaling, and includes one or more PPUs 2200 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPUs 2200 and the CPUs, and CPU hosting. In at least one embodiment, the high-speed GPU interconnect 2208 transmits data and/or commands to other units of the PPU 2200, such as one or more replication engines, video encoders, video decoders, power management units, and/or other components that may not be explicitly shown in fig. 22, through the hub 2216.

In at least one embodiment, the I/O unit 2206 is configured to send and receive communications (e.g., commands, data) from a host processor (not shown in fig. 22) over the system bus 2202. In at least one embodiment, the I/O unit 2206 communicates with the host processor directly over the system bus 2202 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I/O unit 2206 may communicate with one or more other processors (e.g., one or more PPUs 2200) via a system bus 2202. In at least one embodiment, I/O unit 2206 implements a PCIe interface for communicating over a PCIe bus. In at least one embodiment, the I/O unit 2206 implements an interface for communicating with external devices.

In at least one embodiment, the I/O unit 2206 decodes packets received via the system bus 2202. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2200 to perform various operations. In at least one embodiment, I/O unit 2206 sends the decoded command to various other units of PPU 2200 as specified by the command. In at least one embodiment, commands are sent to front end unit 2210 and/or to hub 2216 or other units of PPU 2200, such as one or more replication engines, video encoders, video decoders, power management units, and the like (not explicitly shown in fig. 22). In at least one embodiment, I/O unit 2206 is configured to route communications between various logical units of PPU 2200.

In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to PPU 2200 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffers are regions in memory accessible (e.g., read/write) by both the host processor and the PPU 2200-the host interface unit may be configured to access buffers in system memory coupled to the system bus 2202 via memory requests transmitted by the I/O unit 2206 over the system bus 2202. In at least one embodiment, host processor writes command streams to buffers and then sends pointers to the PPU 2200 that indicate the start of the command streams, such that front end unit 2210 receives pointers to and manages one or more command streams, reads commands from the command streams and forwards the commands to the various units of PPU 2200.

In at least one embodiment, the front end unit 2210 is coupled to a scheduler unit 2212, which scheduler unit 2212 configures various GPCs 2218 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2212 is configured to track state information related to various tasks managed by the scheduler unit 2212, where the state information may indicate which GPCs 2218 the task is assigned to, whether the task is active or inactive, priorities associated with the tasks, and so on. In at least one embodiment, a scheduler unit 2212 manages a plurality of tasks executing on one or more GPCs 2218.

In at least one embodiment, the scheduler unit 2212 is coupled to a work allocation unit 2214, the work allocation unit 2214 configured to dispatch tasks to execute on GPCs 2218. In at least one embodiment, the work allocation unit 2214 tracks a number of scheduled tasks received from the scheduler unit 2212 and the work allocation unit 2214 manages a pending task pool and an active task pool for each GPC 2218. In at least one embodiment, the pool of tasks to be processed includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2218; the active task pool may include multiple slots (e.g., 4 slots) for tasks actively processed by the GPCs 2218, such that as one of the GPCs 2218 completes execution of a task, that task will be evicted from the active task pool of the GPC 2218, and one of the other tasks is selected from the pending task pool and scheduled to execute on the GPC 2218. In at least one embodiment, if the active task is idle on the GPC 2218, e.g., while waiting for a data dependency to resolve, the active task is evicted from the GPC 2218 and returned to the pending task pool while another task in the pending task pool is selected and scheduled to execute on the GPC 2218.

In at least one embodiment, the work allocation unit 2214 communicates with one or more GPCs 2218 via XBar 2220. In at least one embodiment, XBar2220 is an interconnection network that couples many of the units of PPU 2200 to other units of PPU 2200, and may be configured to couple work allocation unit 2214 to a particular GPC 2218. In at least one embodiment, other units of one or more PPUs 2200 may also be connected to XBar2220 through hub 2216.

In at least one embodiment, tasks are managed by a scheduler unit 2212 and allocated to one of the GPCs 2218 by a work allocation unit 2214. GPCs 2218 are configured to process tasks and produce results. In at least one embodiment, results can be consumed by other tasks in a GPC2218, routed to a different GPC2218 through XBar2220 or stored in memory 2204. In at least one embodiment, the results may be written to the memory 2204 through the partition unit 2222, which implements a memory interface for writing data to the memory 2204 or reading data from the memory 2204. In at least one embodiment, the results may be transmitted to another PPU 2200 or CPU via a high speed GPU interconnect 2208. In at least one embodiment, the PPU 2200 includes, but is not limited to, U partition units 2222, which is equal to the number of separate and distinct memory devices 2204 coupled to the PPU 2200.

In at least one embodiment, the host processor executes a driver core that implements an Application Programming Interface (API) that enables one or more applications executing on the host processor to schedule operations to execute on PPU 2200. In one embodiment, multiple computing applications are executed concurrently by PPU 2200, and PPU 2200 provides isolation, quality of service ("QoS"), and independent address spaces for multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by PPU 2200, and the driver core outputs the tasks to one or more streams processed by PPU 2200. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as thread bundles (warp). In at least one embodiment, a thread bundle includes multiple related threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for performing tasks and exchanging data through shared memory.

Fig. 23 illustrates a GPC2300, according to at least one embodiment. In at least one embodiment, GPC2300 is GPC 2218 of fig. 22. In at least one embodiment, each GPC2300 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC2300 includes, but is not limited to, a pipeline manager 2302, a pre-raster operations unit ("PROP") 2304, a raster engine 2308, a work allocation crossbar ("WDX") 2316, a memory management unit ("MMU") 2318, one or more data processing clusters ("DPCs") 2306, and any suitable combination of components.

In at least one embodiment, the operation of the GPCs 2300 is controlled by a pipeline manager 2302. In at least one embodiment, pipeline manager 2302 manages the configuration of one or more DPCs 2306 to process tasks allocated to GPC 2300. In at least one embodiment, pipeline manager 2302 configures at least one of the one or more DPCs 2306 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 2306 is configured to execute vertex shader programs on programmable streaming multiprocessor ("SM") 2314. In at least one embodiment, the pipeline manager 2302 is configured to route data packets received from the work distribution units to the appropriate logic units within the GPC2300, and in at least one embodiment, some data packets may be routed to fixed function hardware units in the PROP 2304 and/or raster engine 2308, while other data packets may be routed to the DPC 2306 for processing by the primitive engine 2312 or SM 2314. In at least one embodiment, pipeline manager 2302 configures at least one of DPCs 2306 to implement a neural network model and/or a computing pipeline. In at least one embodiment, pipeline manager 2302 configures at least one of DPC 2306 to execute at least a portion of a CUDA program.

In at least one embodiment, the PROP unit 2304 is configured to route data generated by the raster engine 2308 and DPC 2306 to raster operation ("ROP") units in partition units, such as memory partition unit 2222, described in more detail above in connection with fig. 22, and the like. In at least one embodiment, PROP unit 2304 is configured to perform optimizations for color mixing, organize pixel data, perform address translation, and so forth. In at least one embodiment, the raster engine 2308 includes, but is not limited to, a plurality of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2308 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to a coarse raster engine to generate coverage information for the base primitive (e.g., x, y coverage masks for tiles); the output of the coarse raster engine will be passed to a culling engine where fragments associated with primitives that fail the z-test will be culled and passed to a clipping engine where fragments that lie outside the viewing cone are clipped. In at least one embodiment, the clipped and culled segments are passed to a fine raster engine to generate attributes for the pixel segments based on a plane equation generated by a setup engine. In at least one embodiment, the output of the raster engine 2308 includes fragments to be processed by any suitable entity (e.g., by fragment shaders implemented within DPC 2306).

In at least one embodiment, each DPC 2306 included in the GPC 2300 includes, but is not limited to, an M-line controller ("MPC") 2310; a primitive engine 2312; one or more SM 2314; and any suitable combination thereof. In at least one embodiment, MPC 2310 controls the operation of DPC 2306, routing packets received from pipeline manager 2302 to the appropriate elements in DPC 2306. In at least one embodiment, packets associated with the vertices are routed to a primitive engine 2312, the primitive engine 2312 configured to retrieve vertex attributes associated with the vertices from memory; instead, data packets associated with the shader programs may be sent to the SM 2314.

In at least one embodiment, the SM 2314 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by a plurality of threads. In at least one embodiment, the SM 2314 is multithreaded and configured to execute multiple threads (e.g., 32 threads) simultaneously from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture in which each thread in a thread group (e.g., a thread bundle) is configured to process different sets of data based on the same set of instructions. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, the SM 2314 implements a single instruction, multi-threaded ("SIMT") architecture, where each thread in a thread group is configured to process different sets of data based on the same instruction set, but where individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle to enable concurrency between the thread bundle and serial execution within the thread bundle as threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, so that there is equal concurrency between all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions may be converged and executed in parallel to improve efficiency. At least one embodiment of SM 2314 is described in more detail below in conjunction with fig. 24.

In at least one embodiment, MMU 2318 provides an interface between the GPC 2300 and a memory partition unit (e.g., partition unit 2222 of FIG. 22), and MMU 2318 provides translation of virtual addresses to physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2318 provides one or more translation lookaside buffers ("TLBs") for performing virtual address to physical address translations in memory.

Fig. 24 illustrates a streaming multiprocessor ("SM") 2400 in accordance with at least one embodiment. In at least one embodiment, the SM 2400 is the SM2314 of fig. 23. In at least one embodiment, SM 2400 includes, but is not limited to, instruction cache 2402; one or more scheduler units 2404; a register file 2408; one or more processing cores ("cores") 2410; one or more special function units ("SFUs") 2412; one or more load/store units ("LSUs") 2414; an interconnection network 2416; shared memory/level one ("L1") cache 2418; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks for execution on a general purpose processing cluster ("GPC") of parallel processing units ("PPUs"), and each task is allocated to a particular data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is allocated to one of the SMs 2400. In at least one embodiment, the scheduler unit 2404 receives tasks from the work allocation unit and manages the scheduling of instructions for one or more thread blocks allocated to the SM 2400. In at least one embodiment, scheduler unit 2404 schedules thread blocks to execute as bundles of parallel threads, where each thread block is assigned at least one bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 2404 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing cores 2410, SFUs 2412, and LSUs 2414) in each clock cycle.

In at least one embodiment, a "collaboration group" may refer to a programming model for organizing a group of communication threads that allows a developer to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient parallel decompositions. In at least one embodiment, the collaborative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of the conventional programming model provides a single, simple construct for synchronizing the cooperative threads: a barrier (e.g., synchrads () function) across all threads of a thread block. However, in at least one embodiment, a programmer may define thread groups at less than thread block granularity and synchronize within the defined groups to achieve greater performance, design flexibility, and software reuse in the form of an aggregate group-wide functional interface. In at least one embodiment, the collaboration group enables programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads in the collaboration group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries so that library and utility functions can be safely synchronized in their local environment without making assumptions about convergence. In at least one embodiment, the collaboration group primitives enable new patterns of collaboration parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the thread block grid.

In at least one embodiment, dispatch unit 2406 is configured to issue instructions to one or more of the functional units, and scheduler unit 2404 includes, but is not limited to, two dispatch units 2406 that enable two different instructions from the same thread bundle to be dispatched each clock cycle. In at least one embodiment, each scheduler unit 2404 includes a single dispatch unit 2406 or additional dispatch units 2406.

In at least one embodiment, each SM 2400 includes, in at least one embodiment but is not limited to, a register file 2408, the register file 2408 providing a set of registers for the functional units of the SM 2400. In at least one embodiment, register file 2408 is divided among each functional unit, such that a dedicated portion of register file 2408 is allocated for each functional unit. In at least one embodiment, the register file 2408 is divided between different thread bundles executed by the SM 2400, and the register file 2408 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2400 includes, but is not limited to, a plurality L of processing cores 2410. In at least one embodiment, the SM 2400 includes, but is not limited to, a number (e.g., 128 or more) of different processing cores 2410. In at least one embodiment, each processing core 2410 includes, in at least one embodiment, but is not limited to, a full-pipeline, single-precision, double-precision, and/or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating point arithmetic logic unit implements the IEEE 754-. In at least one embodiment, the processing cores 2410 include, but are not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, the one or more tensor cores are included in the processing core 2410. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4 × 4 matrix and performs a matrix multiply and accumulate operation D ═ a × B + C, where A, B, C and D are 4 × 4 matrices.

In at least one embodiment, the matrix multiplication inputs a and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on 16-bit floating-point input data. In at least one embodiment, 16-bit floating-point multiplication uses 64 operations and results in a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4 × 4 × 4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C + + API) exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use the tensor core from the CUDA-C + + program. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16 x 16 size matrix that spans all 32 thread bundle threads.

In at least one embodiment, each SM 2400 includes, but is not limited to, M SFUs 2412 that perform a particular function (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, SFU 2412 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFU 2412 includes, but is not limited to, texture units configured to perform texture mapping filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texels) and a sampled texture map from memory to produce sampled texture values for use by a shader program executed by SM 2400. In at least one embodiment, the texture map is stored in shared memory/L1 cache 2418. In at least one embodiment, the texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations, such as filtering operations. In at least one embodiment, each SM 2400 includes, but is not limited to, two texture units.

In at least one embodiment, each SM 2400 includes, but is not limited to, N LSUs 2414 that implement load and store operations between shared memory/L1 cache 2418 and register file 2408. In at least one embodiment, each SM 2400 includes, but is not limited to, an interconnection network 2416, interconnection network 2416 connects each functional unit to register file 2408, and LSU 2414 connects to register file 2408 and shared memory/L1 cache 2418. In at least one embodiment, interconnect network 2416 is a crossbar that may be configured to couple any functional unit to any register in register file 2408, and to couple LSU 2414 to register file 2408 and to memory locations in shared memory/L1 cache 2418.

In at least one embodiment, the shared memory/L1 cache 2418 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 2400 and the primitive engines, and between threads in the SM 2400. In at least one embodiment, the shared memory/L1 cache 2418 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2400 to the partition unit. In at least one embodiment, shared memory/L1 cache 2418 is used in at least one embodiment to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache 2418, L2 cache, and memory are backing stores.

In at least one embodiment, combining data caching and shared memory functions into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, the capacity is used by or as a cache for programs that do not use the shared memory, e.g., texture and load/store operations may use the remaining capacity if the shared memory is configured to use half the capacity. According to at least one embodiment, integration within shared memory/L1 cache 2418 enables shared memory/L1 cache 2418 to function as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computing, a simpler configuration may be used compared to graphics processing. In at least one embodiment, a fixed function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general purpose parallel computing configuration, the work allocation unit allocates and distributes blocks of threads directly to the DPCs. In at least one embodiment, the threads in a block execute the same program, use unique thread IDs in the computations to ensure that each thread generates unique results, execute the program using SM 2400 and perform the computations, communicate between threads using shared memory/L1 cache 2418, and read and write global memory using LSU 2414 through shared memory/L1 cache 2418 and memory partition units. In at least one embodiment, when configured for general purpose parallel computing, the SM 2400 writes to the scheduler unit 2404 a command that can be used to start a new job on the DPC.

In at least one embodiment, the PPU is included in or coupled with a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head mounted display, handheld electronic device, or the like. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, RISCCPU, MMU, digital-to-analog converter ("DAC"), etc.).

In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to connect to a PCIe slot on the desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in a chipset of a motherboard.

Software construction for general purpose computing

The following figures set forth, but are not limited to, exemplary software configurations for implementing at least one embodiment.

FIG. 25 illustrates a software stack of a programming platform in accordance with at least one embodiment. In at least one embodiment, the programming platform is for utilizing hardware on a computing system to accelerate computations A platform for the task. In at least one embodiment, a software developer may access the programming platform through libraries, compiler instructions, and/or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radon open computing platform ("ROCM"), OpenCL (OpenCL developed by Khronos group)^TM) SYCL or Intel One API.

In at least one embodiment, the software stack 2500 of the programming platform provides an execution environment for the application programs 2501. In at least one embodiment, the applications 2501 can include any computer software capable of launching on the software stack 2500. In at least one embodiment, the applications 2501 can include, but are not limited to, artificial intelligence ("AI")/machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

In at least one embodiment, applications 2501 and software stack 2500 run on hardware 2507. In at least one embodiment, the hardware 2507 can include one or more GPUs, CPUs, FPGAs, AI engines, and/or other types of computing devices that support a programming platform. In at least one embodiment, for example with CUDA, software stack 2500 may be vendor specific and compatible only with devices from a particular vendor. In at least one embodiment, software stack 2500 may be used with devices from different vendors, such as in OpenCL. In at least one embodiment, the hardware 2507 includes a host computer connected to one or more devices that can be accessed via Application Programming Interface (API) calls to perform computing tasks. In at least one embodiment, the devices within the hardware 2507 can include, but are not limited to, a GPU, FPGA, AI engine, or other computing device (but can also include a CPU) and memory thereof, as opposed to a host within the hardware 2507, which can include, but is not limited to, a CPU (but can also include a computing device) and memory thereof.

In at least one embodiment, the software stack 2500 of the programming platform includes, but is not limited to, a plurality of libraries 2503, runtime (runtime)2505, and device kernel drivers 2506. In at least one embodiment, each of the libraries 2503 can include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, the library 2503 can include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documents, help data, and/or message templates. In at least one embodiment, library 2503 includes functions optimized for execution on one or more types of devices. In at least one embodiment, the library 2503 can include, but is not limited to, functions for performing mathematical, deep learning, and/or other types of operations on a device. In at least one embodiment, the library 2503 is associated with a corresponding API 2502, and the API 2502 can include one or more APIs that expose functions implemented in the library 2503.

In at least one embodiment, the application program 2501 is written as source code that is compiled into executable code, as discussed in more detail below in connection with FIGS. 30-32. In at least one embodiment, the executable code of the application program 2501 may run, at least in part, on the execution environment provided by the software stack 2500. In at least one embodiment, code that needs to run on the device (as opposed to the host) is available during execution of the application program 2501. In this case, in at least one embodiment, the runtime 2505 can be invoked to load and launch the necessary code on the device. In at least one embodiment, the runtime 2505 can include any technically feasible runtime system capable of supporting execution of the application programs 2501.

In at least one embodiment, the runtimes 2505 are implemented as one or more runtime libraries associated with corresponding APIs (shown as API 2504). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling and/or synchronization, and the like. In at least one embodiment, the memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory and transferring data between host memory and device memory. In at least one embodiment, the execution control functions may include, but are not limited to, functions that launch a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions that set attribute values in a buffer maintained by the runtime library for a given function to be executed on the device.

In at least one embodiment, the runtime libraries and corresponding APIs 2504 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a set of low-level functions for fine-grained control of a device, while another (or any number of) APIs may expose such a set of higher-level functions. In at least one embodiment, the high-level runtime API may be built on top of the low-level API. In at least one embodiment, the one or more runtime APIs may be language specific APIs layered above the language independent runtime APIs.

In at least one embodiment, the device kernel driver 2506 is configured to facilitate communications with the underlying device. In at least one embodiment, the device kernel driver 2506 can provide low-level functions upon which APIs such as API 2504 and/or other software depends. In at least one embodiment, the device kernel driver 2506 may be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2506 may compile non-hardware-specific parallel thread execution ("PTX") IR code at runtime into binary code (cache compiled binary code), sometimes referred to as "final" code, for a particular target device. In at least one embodiment, doing so may allow the final code to run on the target device, which may not be present when the source code was originally compiled as PTX code. Alternatively, in at least one embodiment, the device source code may be compiled offline into binary code without requiring the device kernel driver 2506 to compile the IR code at runtime.

FIG. 26 illustrates a CUDA implementation of the software stack 2500 of FIG. 25 in accordance with at least one embodiment. In at least one embodiment, the CUDA software stack 2600 on which the application programs 2601 may be launched includes a CUDA library 2603, a CUDA runtime 2605, a CUDA driver 2607, and a device kernel driver 2608. In at least one embodiment, CUDA software stack 2600 executes on hardware 2609, which hardware 2609 may include a CUDA-enabled GPU developed by NVIDIA corporation of santa clara, california.

In at least one embodiment, the application 2601, CUDA runtime 2605, and device kernel driver 2608 can perform similar functions as the application 2501, runtime 2505, and device kernel driver 2506, respectively, described above in connection with fig. 25. In at least one embodiment, the CUDA driver 2607 includes a library (libcuda.so) that implements the CUDA driver API 2606. In at least one embodiment, the CUDA driver API 2606 may disclose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, similar to the CUDA runtime API2604 implemented by a CUDA runtime library (cudart). In at least one embodiment, the CUDA driver API 2606 differs from the CUDA runtime API2604 in that the CUDA runtime API2604 simplifies device code management by providing implicit initialization, context (like a process) management, and module (like a dynamically loaded library) management. In contrast to the high-level CUDA runtime APIs 2604, in at least one embodiment, the CUDA driver APIs 2606 are low-level APIs that provide finer-grained control of devices, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2606 can expose functions for context management that are not disclosed by the CUDA runtime API 2604. In at least one embodiment, the CUDA driver APIs 2606 are also language independent and support, for example, OpenCL in addition to CUDA runtime APIs 2604. Further, in at least one embodiment, the development library, including the CUDA runtime 2605, can be viewed as separate from the driver components, including a user mode CUDA driver 2607 and a kernel mode device driver 2608 (also sometimes referred to as a "display" driver).

In at least one embodiment, CUDA library 2603 may include, but is not limited to, a math library, a deep learning library, a parallel algorithms library, and/or a signal/image/video processing library that may be utilized by parallel computing applications (e.g., application 2601). In at least one embodiment, CUDA library 2603 may include a math library, such as a cuBLAS library, which is an implementation of a basic linear algebra subroutine ("BLAS") for performing linear algebra operations; a cuFFT library for computing fast Fourier transforms ("FFT"), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA library 2603 may include deep learning libraries such as a cuDNN library for primitives of a deep neural network and a TensorRT platform for high performance deep learning reasoning, among others.

FIG. 27 illustrates a ROCm implementation of the software stack 2500 of FIG. 25 in accordance with at least one embodiment. In at least one embodiment, the ROcm software stack 2700 on which the application 2701 can be launched includes a language runtime 2703, a system runtime 2705, a thunk2707, and a ROcm kernel driver 2708. In at least one embodiment, the ROCm software stack 2700 executes on hardware 2709, which hardware 2709 can include a GPU supporting ROCm, developed by AMD corporation of santa clara, california.

In at least one embodiment, application 2701 can perform similar functions to application 2501 discussed above in connection with FIG. 25. Additionally, in at least one embodiment, the language runtime 2703 and the system runtime 2705 can perform similar functions as the runtime 2505 discussed above in connection with FIG. 25. In at least one embodiment, language runtime 2703 and system runtime 2705 differ in that system runtime 2705 is a language independent runtime that implements ROCr system runtime API 2704 and utilizes a heterogeneous system architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user mode API that exposes interfaces for access and interaction with the AMD GPU, including functions for memory management, execution control by the framework dispatch kernel, error handling, system and proxy information, and runtime initialization and shutdown, among other functions. In at least one embodiment, the language runtime 2703 is an implementation of language specific runtime APIs 2702 layered on top of the ROCr system runtime APIs 2704 as compared to the system runtime 2705. In at least one embodiment, the language runtime APIs may include, but are not limited to, portable heterogeneous computing interface ("HIP") language runtime APIs, heterogeneous computing compiler ("HCC") language runtime APIs, or OpenCL APIs, among others. In particular, the HIP language is an extension of the C + + programming language, with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes functions similar to the CUDA runtime API 2604 discussed above in connection with fig. 26, such as functions for memory management, execution control, device management, error handling and synchronization, and the like.

In at least one embodiment, thunk (rock) 2707 is an interface that can be used to interact with an underlying rock driver 2708. In at least one embodiment, the ROcm driver 2708 is a ROCK driver, which is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for a GPU developed by AMD that performs similar functions to the device kernel driver 2506 discussed above in connection with fig. 25. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

In at least one embodiment, various libraries (not shown) can be included in ROCm software stack 2700 above language runtime 2703 and provide similar functionality to CUDA library 2603 discussed above in connection with fig. 26. In at least one embodiment, the various libraries may include, but are not limited to, math, deep learning, and/or other libraries, such as a hipplas library that implements a function similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT used to compute FFTs, and the like.

Figure 28 illustrates an OpenCL implementation of the software stack 2500 of figure 25 in accordance with at least one embodiment. In at least one embodiment, the OpenCL software stack 2800 on which the application program 2801 may be launched includes an OpenCL framework 2810, OpenCL runtimes 2806 and drivers 2807. In at least one embodiment, the OpenCL software stack 2800 executes on hardware 2609 that is not vendor specific. In at least one embodiment, since OpenCL is supported by devices developed by different vendors, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

In at least one embodiment, the application program 2801, the OpenCL runtime 2806, the device kernel driver 2807, and the hardware 2808 may perform similar functions to the application program 2501, the runtime 2505, the device kernel driver 2506, and the hardware 2507, respectively, discussed above in connection with fig. 25. In at least one embodiment, the application program 2801 also includes an OpenCL kernel 2802 that has code to be executed on the device.

In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides platform layer APIs and runtime APIs, shown as platform APIs 2803 and runtime APIs 2805. In at least one embodiment, the runtime API2805 uses the context to manage execution of the kernel on the device. In at least one embodiment, each identified device may be associated with a respective context that runtime API2805 may use to manage the device's command queues, program objects and kernel objects, shared memory objects, and so forth. In at least one embodiment, the platform API 2803 discloses functions that allow device context to be used to select and initialize devices, submit work to devices via command queues, and enable data transfers to and from devices, and the like. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

In at least one embodiment, compiler 2804 is also included in OpenCL framework 2810. In at least one embodiment, the source code may be compiled offline prior to execution of the application or online during execution of the application. In contrast to CUDA and ROCm, the OpenCL application in at least one embodiment may be compiled online by compiler 2804, compiler 2804 being included to represent any number of compilers that may be used to compile source code and/or IR code (e.g., standard portable intermediate representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, the OpenCL application can be compiled offline before executing such application.

FIG. 29 illustrates software supported by a programming platform in accordance with at least one embodiment. In at least one embodiment, programming platform 2904 is configured to support various programming models 2903, middleware and/or libraries 2902, and frameworks 2901 upon which application 2900 may depend. In at least one embodiment, the application 2900 may be an AI/ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may rely on libraries such as the cuDNN, NVIDIA Collective Communications Library ("NCCL") "and/or NVIDIA developer data load Library (" DALI ") CUDA libraries to provide accelerated computing on the underlying hardware.

In at least one embodiment, programming platform 2904 may be one of the CUDA, ROCm, or OpenCL platforms described above in connection with fig. 26, 27, and 28, respectively. In at least one embodiment, programming platform 2904 supports multiple programming models 2903, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, programming model 2903 may expose features of the underlying hardware in order to improve performance. In at least one embodiment, programming model 2903 may include, but is not limited to, CUDA, HIP, OpenCL, C + + accelerated massive parallelism ("C + + AMP"), open multiprocessing ("OpenMP"), open accelerators ("OpenACC"), and/or Vulcan computing (Vulcan computer).

In at least one embodiment, libraries and/or middleware 2902 provide an abstract implementation of programming model 2904. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications in addition to those available from programming platform 2904. In at least one embodiment, the libraries and/or middleware 2902 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the libraries and/or middleware 2902 may include NCCL and ROCm communication collection library ("RCCL") libraries that provide communication routines for GPUs, mion libraries for deep learning acceleration, and/or eigenlibraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

In at least one embodiment, the application framework 2901 depends on the library and/or middleware 2902. In at least one embodiment, each application framework 2901 is a software framework for implementing a standard architecture for application software. Returning to the AI/ML example discussed above, in at least one embodiment, the AI/ML application can be implemented using a framework (such as the Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework).

FIG. 30 illustrates compiling code to execute on one of the programming platforms of FIGS. 25-28, in accordance with at least one embodiment. In at least one embodiment, compiler 3001 receives source code 3000, which includes both host code as well as device code. In at least one embodiment, compiler 3001 is configured to convert source code 3000 into host-executable code 3002 for execution on a host and device-executable code 3003 for execution on a device. In at least one embodiment, source code 3000 may be compiled offline prior to execution of the application or online during execution of the application.

In at least one embodiment, source code 3000 may include code in any programming language supported by compiler 3001, such as C + +, C, Fortran, and so forth. In at least one embodiment, the source code 3000 may be included in a single-source (single-source) file that has a mix of host code and device code, and in which the location of the device code is indicated. In at least one embodiment, the single source file may be a cu file that includes a CUDA code or a HIP. cpp file that includes a HIP code. Alternatively, in at least one embodiment, source code 3000 may include multiple source code files, rather than a single source file in which host code and device code are separate.

In at least one embodiment, the compiler 3001 is configured to compile the source code 3000 into host-executable code 3002 for execution on a host and device-executable code 3003 for execution on a device. In at least one embodiment, compiler 3001 performs operations including parsing source code 3000 into an Abstract System Tree (AST), performing optimizations, and generating executable code. In at least one embodiment where the source code 3000 comprises a single source file, the compiler 3001 may separate the device code from the host code in such a single source file, compile the device code and the host code into the device executable code 3003 and the host executable code 3002, respectively, and link the device executable code 3003 and the host executable code 3002 together in a single file, as discussed in more detail below with respect to fig. 31.

In at least one embodiment, the host executable code 3002 and the device executable code 3003 may be in any suitable format, such as binary code and/or IR code. In the case of a CUDA, in at least one embodiment, the host executable code 3002 may comprise native object code, while the device executable code 3003 may comprise code of a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3002 and the device executable code 3003 may comprise target binary code.

FIG. 31 is a more detailed illustration of compiling code to execute on one of the programming platforms of FIGS. 25-28, according to at least one embodiment. In at least one embodiment, compiler 3101 is configured to receive source code 3100, compile source code 3100, and output executable file 3110. In at least one embodiment, source code 3100 is a single source file, such as a cu file, a hip. cpp file, or other format file, that includes both host code and device code. In at least one embodiment, compiler 3101 may be, but is not limited to, an nvidiaguacuda compiler ("NVCC") for compiling CUDA code in a. cu file, or an HCC compiler for compiling HIP code in a. HIP. cpp file.

In at least one embodiment, compiler 3101 includes compiler front end 3102, host compiler 3105, device compiler 3106 and linker 3109. In at least one embodiment, compiler front-end 3102 is configured to separate device code 3104 from host code 3103 in source code 3100. In at least one embodiment, the device code 3104 is compiled by a device compiler 3106 into device executable code 3108, which may include binary code or IR code as described. In at least one embodiment, host code 3103 is separately compiled by host compiler 3105 into host executable code 3107. In at least one embodiment, for NVCCs, host compiler 3105 may be, but is not limited to, a general purpose C/C + + compiler that outputs native object code, while device compiler 3106 may be, but is not limited to, a low-level virtual machine ("LLVM") based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3105 and device compiler 3106 may be, but are not limited to, LLVM-based compilers that output target binary code.

In at least one embodiment, linker 3109 links host and device executable code 3107 and 3108 together in executable file 3110 after source code 3100 is compiled into host executable code 3107 and device executable code 3108. In at least one embodiment, the native object code of the host and PTX or the binary code of the device may be linked together in an executable and linkable format ("ELF") file, which is a container format for storing object code.

FIG. 32 illustrates translating source code prior to compiling the source code in accordance with at least one embodiment. In at least one embodiment, source code 3200 is passed through translation tool 3201, and translation tool 3201 translates source code 3200 into translated source code 3202. In at least one embodiment, compiler 3203 is used to compile the translated source code 3202 into host executable code 3204 and device executable code 3205, a process similar to the process of compiling source code 3000 into host executable code 3002 and device executable code 3003 by compiler 3001, as discussed above in connection with fig. 30.

In at least one embodiment, the translation performed by translation tool 3201 is used to migrate (port) source code 3200 to perform in a different environment than that on which it was originally intended to run. In at least one embodiment, transformation tool 3201 can include, but is not limited to, a HIP transformer for "porting" (hipify) CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCM platform. In at least one embodiment, the transformation of source code 3200 may comprise: the source code 3200 is parsed and calls to APIs provided by one programming model (e.g., CUDA) are translated into corresponding calls to APIs provided by another programming model (e.g., HIP), as discussed in more detail below in conjunction with FIGS. 33A-34. Returning to the example of migrating CUDA code, in at least one embodiment, calls to CUDA runtime APIs, CUDA driver APIs, and/or CUDA libraries may be converted into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by translation tool 3201 may sometimes be incomplete, requiring additional labor to completely migrate source code 3200.

Configuring a GPU for general purpose computing

The following figures set forth, but are not limited to, an exemplary architecture for compiling and executing computing source code in accordance with at least one embodiment.

Fig. 33A illustrates a system 3300 configured to compile and execute CUDA source code 3310 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 3300 includes, but is not limited to, CUDA source code 3310, CUDA compiler 3350, host executable code 3370(1), host executable code 3370(2), CUDA device executable code 3384, CPU 3390, CUDA-enabled GPU 3394, GPU 3392, CUDA-to-HIP conversion tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, and HCC device executable code 3382.

In at least one embodiment, CUDA source code 3310 is a collection of human-readable code of the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code of the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C + + programming language, which includes, but is not limited to, mechanisms to define device code and to distinguish device code from host code. In at least one embodiment, the device code is source code that is executable in parallel on the device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3390, a GPU 3392, or another GPGPU, among others. In at least one embodiment, the host code is source code that may be executed on the host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as CPU 3390.

In at least one embodiment, the CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host/device functions 3318. In at least one embodiment, global functions 3312, device functions 3314, host functions 3316, and host/device functions 3318 may be mixed in CUDA source code 3310. In at least one embodiment, each global function 3312 may execute on a device and may be called from a host. Thus, in at least one embodiment, one or more of global functions 3312 may serve as an entry point for a device. In at least one embodiment, each global function 3312 is a kernel. In at least one embodiment and in one technique referred to as dynamic parallelism, one or more global functions 3312 define a kernel that can be executed on a device and that can be invoked from such a device. In at least one embodiment, the kernel is executed N times in parallel by N different threads on the device during execution (where N is any positive integer).

In at least one embodiment, each device function 3314 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3316 executes on a host and can only be called from such a host. In at least one embodiment, each host/device function 3316 defines both a host version of a function that is executable on the host and can only be called from such host, and a device version of a function that is executable on the device and can only be called from such device.

In at least one embodiment, CUDA source code 3310 may also include, but is not limited to, any number of calls to any number of functions defined through CUDA runtime APIs 3302. In at least one embodiment, the CUDA runtime APIs 3302 may include, but are not limited to, any number of functions executing on the host for allocating and deallocating device memory, transferring data between the host memory and the device memory, managing a system with multiple devices, and the like. In at least one embodiment, CUDA source code 3310 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA APIs may be any APIs designed to be used by CUDA code. In at least one embodiment, the CUDA APIs include, but are not limited to, CUDA runtime APIs 3302, CUDA driver APIs, APIs for any number of CUDA libraries, and the like. In at least one embodiment and with respect to the CUDA runtime APIs 3302, the CUDA driver APIs are lower level APIs, but may provide finer grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cubAS, cuFFT, cuRAND, cuDNN, and the like.

In at least one embodiment, CUDA compiler 3350 compiles the input CUDA code (e.g., CUDA source code 3310) to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, CUDA compiler 3350 is an NVCC. In at least one embodiment, host executable code 3370(1) is a compiled version of host code included in the input source code that is executable on CPU 3390. In at least one embodiment, CPU 3390 may be any processor optimized for sequential instruction processing.

In at least one embodiment, CUDA device executable code 3384 is a compiled version of device code included in input source code executable on CUDA-enabled GPU 3394. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, IR code, such as PTX code, that is further compiled at runtime by a device driver into binary code for a particular target device (e.g., CUDA-enabled GPU 3394). In at least one embodiment, CUDA-enabled GPU 3394 may be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, CUDA-enabled GPU 3394 is developed by NVIDIA corporation of santa clara, california.

In at least one embodiment, CUDA to HIP conversion tool 3320 is configured to convert CUDA source code 3310 into functionally similar HIP source code 3330. In at least one embodiment, HIP source code 3330 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code of a HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C + + programming language, including but not limited to a functionally similar version of the CUDA mechanism, for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language can include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms to define global functions 3312, but such HIP programming languages may lack support for dynamic parallelism, and thus, global functions 3312 defined in HIP code may only be called from a host.

In at least one embodiment, HIP source code 3330 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host/device functions 3318. In at least one embodiment, HIP source code 3330 can also include any number of calls to any number of functions specified in HIP runtime APIs 3332. In one embodiment, the HIP runtime APIs 3332 include, but are not limited to, functionally similar versions of a subset of the functions included in the CUDA runtime API 3302. In at least one embodiment, HIP source code 3330 can also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API can be any API designed for use by HIP code and/or ROCM. In at least one embodiment, the HIP APIs include, but are not limited to, HIP runtime APIs 3332, HIP driver APIs, APIs for any number of HIP libraries, APIs for any number of ROCM libraries, and the like.

In at least one embodiment, CUDA-to-HIP translation tool 3320 translates each kernel call in the CUDA code from the CUDA syntax to the HIP syntax and translates any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, the CUDA call is a call to a function specified in the CUDA API, and the HIP call is a call to a function specified in the HIP API. In at least one embodiment, CUDA to HIP conversion tool 3320 converts any number of calls to functions specified in CUDA runtime APIs 3302 to any number of calls to functions specified in HIP runtime APIs 3332.

In at least one embodiment, CUDA to HIP conversion tool 3320 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, CUDA to HIP conversion tool 3320 is a tool referred to as hipify-clone, which performs a more complex and robust conversion process relative to hipify-perl, which involves parsing the CUDA code using clone (compiler front end) and then converting the resulting symbols. In at least one embodiment, correctly converting the CUDA code to HIP code may require modification (e.g., manual editing) in addition to those performed by CUDA to HIP conversion tool 3320.

In at least one embodiment, HIP compiler driver 3340 is a front end that determines target device 3346 and then configures a compiler compatible with target device 3346 to compile HIP source code 3330. In at least one embodiment, target device 3346 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3340 can determine target device 3346 in any technically feasible manner.

In at least one embodiment, if target device 3346 is compatible with the CUDA (e.g., CUDA-enabled GPU 3394), HIP compiler driver 3340 generates HIP/NVCC compilation commands 3342. In at least one embodiment and described in more detail in connection with FIG. 33B, HIP/NVCC compilation command 3342 configures CUDA compiler 3350 to compile HIP source code 3330 using, but not limited to, a HIP-to-CUDA conversion header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compile command 3342, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384.

In at least one embodiment, HIP compiler driver 3340 generates HIP/HCC compiled command 3344 if target device 3346 is not compatible with the CUDA. In at least one embodiment and as described in more detail in connection with FIG. 33C, HIP/HCC compile command 3344 configures HCC 3360 to compile HIP source code 3330 using the HCC head and HIP/HCC runtime libraries. In at least one embodiment and in response to the HIP/HCC compile command 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, HCC device executable code 3382 is a compiled version of the device code contained in HIP source code 3330 that is executable on GPU 3392. In at least one embodiment, GPU 3392 may be any processor optimized for parallel instruction processing that is not CUDA compatible and is HCC compatible. In at least one embodiment, the GPU 3392 is developed by AMD corporation of Santa Clara, Calif. In at least one embodiment, GPU 3392 is a CUDA-not-enabled GPU 3392.

For illustrative purposes only, three different flows that may be implemented in at least one embodiment as compiling CUDA source code 3310 to execute on CPU 3390 and different devices are depicted in fig. 33A. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3310 for execution on CPU 3390 and CUDA-enabled GPU 3394 without converting CUDA source code 3310 to HIP source code 3330. In at least one embodiment, an indirect CUDA flow converts CUDA source code 3310 to HIP source code 3330, and then compiles HIP source code 3330 to execute on CPU 3390 and CUDA-enabled GPU 3394. In at least one embodiment, the CUDA/HCC flow converts CUDA source code 3310 to HIP source code 3330, and then compiles HIP source code 3330 for execution on CPU 3390 and GPU 3392.

A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as illustrated by bubble annotation A1, CUDA compiler 3350 receives CUDA source code 3310 and CUDA compile commands 3348 that configure CUDA compiler 3350 to compile CUDA source code 3310. In at least one embodiment, the CUDA source code 3310 used in the direct CUDA flow is written in a CUDA programming language that is based on programming languages other than C + + (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compile command 3348, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384 (represented with bubble annotation A2). In at least one embodiment and as illustrated with bubble note a3, host executable code 3370(1) and CUDA device executable code 3384 may execute on CPU 3390 and CUDA-enabled GPU 3394, respectively. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

An indirect CUDA flow that may be implemented in at least one embodiment may be described by a dashed line and a series of bubble annotations B1-B6. In at least one embodiment and as illustrated by bubble note B1, CUDA to HIP conversion tool 3320 receives CUDA source code 3310. In at least one embodiment and as illustrated by bubble note B2, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330. In at least one embodiment and as illustrated by bubble annotation B3, HIP compiler driver 3340 receives HIP source code 3330 and determines whether target device 3346 is CUDA enabled.

In at least one embodiment and as illustrated by bubble annotation B4, HIP compiler driver 3340 generates HIP/NVCC compilation command 3342 and sends both HIP/NVCC compilation command 3342 and HIP source code 3330 to CUDA compiler 3350. In at least one embodiment and as described in more detail in connection with FIG. 33B, HIP/NVCC compilation command 3342 configures CUDA compiler 3350 to compile HIP source code 3330 using, but not limited to, a HIP-to-CUDA conversion header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command 3342, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384 (represented by bubble annotation B5). In at least one embodiment and as illustrated by bubble note B6, host executable code 3370(1) and CUDA device executable code 3384 may execute on CPU 3390 and CUDA-enabled GPU 3394, respectively. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

The CUDA/HCC flow that may be implemented in at least one embodiment may be described by a solid line and a series of bubble annotations C1-C6. In at least one embodiment and as illustrated by bubble note C1, CUDA to HIP conversion tool 3320 receives CUDA source code 3310. In at least one embodiment and as illustrated by bubble note C2, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330. In at least one embodiment and as illustrated by bubble annotation C3, HIP compiler driver 3340 receives HIP source code 3330 and determines that target device 3346 is not CUDA enabled.

In at least one embodiment, HIP compiler driver 3340 generates HIP/HCC compiled command 3344 and sends both HIP/HCC compiled command 3344 and HIP source code 3330 to HCC 3360 (represented by bubble annotation C4). In at least one embodiment and as described in more detail in connection with FIG. 33C, HIP/HCC compiled command 3344 configures HCC 3360 to compile HIP source code 3330 using, but not limited to, an HCC header and HIP/HCC runtime libraries. In at least one embodiment and in response to HIP/HCC compilation command 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382 (represented by bubble annotation C5). In at least one embodiment and as shown by bubble note C6, host executable code 3370(2) and HCC device executable code 3382 may execute on CPU 3390 and GPU 3392, respectively.

In at least one embodiment, after converting CUDA source code 3310 to HIP source code 3330, HIP compiler driver 3340 can then be used to generate executable code for CUDA-enabled GPU 3394 or GPU 3392 without having to re-execute the CUDA as HIP conversion tool 3320. In at least one embodiment, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330, which is then stored in memory. In at least one embodiment, HIP compiler driver 3340 then configures HCC 3360 to generate host executable code 3370(2) and HCC device executable code 3382 based on HIP source code 3330. In at least one embodiment, HIP compiler driver 3340 then configures CUDA compiler 3350 to generate host executable code 3370(1) and CUDA device executable code 3384 based on stored HIP source code 3330.

Fig. 33B illustrates a system 3304 configured to compile and execute the CUDA source code 3310 of fig. 33A using the CPU 3390 and the CUDA-enabled GPU 3394 in accordance with at least one embodiment. In at least one embodiment, system 3304 includes, but is not limited to, CUDA source code 3310, CUDA to HIP translation tool 3320, HIP source code 3330, HIP compiler driver 3340, CUDA compiler 3350, host executable code 3370(1), CUDA device executable code 3384, CPU 3390, and CUDA enabled GPU 3394.

In at least one embodiment and as previously described herein in connection with fig. 33A, the CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of plant functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host/plant functions 3318. In at least one embodiment, CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330. In at least one embodiment, CUDA to HIP translation tool 3320 translates each kernel call in CUDA source code 3310 from a CUDA syntax to a HIP syntax and any number of other CUDA calls in CUDA source code 3310 to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver 3340 determines that target device 3346 is CUDA enabled and generates HIP/NVCC compilation commands 3342. In at least one embodiment, HIP compiler driver 3340 then configures CUDA compiler 3350 via HIP/NVCC compilation commands 3342 to compile HIP source code 3330. In at least one embodiment, HIP compiler driver 3340 provides access to HIP-to-CUDA conversion head 3352 as part of configuring CUDA compiler 3350. In at least one embodiment, HIP-to-CUDA conversion header 3352 converts any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3350 uses HIP-to-CUDA conversion header 3352 in conjunction with CUDA runtime library 3354 corresponding to CUDA runtime APIs 3302 to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, the host executable 3370(1) and the CUDA device executable 3384 may then be executed on the CPU 3390 and the CUDA-enabled GPU 3394, respectively. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

Fig. 33C illustrates a system 3306 according to at least one embodiment, the system 3306 configured to compile and execute the CUDA source code 3310 of fig. 33A using a CPU 3390 and a CUDA-not-enabled GPU 3392. In at least one embodiment, system 3306 includes, but is not limited to, CUDA source code 3310, CUDA to HIP conversion tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, host executable code 3370(2), HCC device executable code 3382, CPU 3390, and GPU 3392.

In at least one embodiment, and as previously described herein in connection with fig. 33A, the CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of plant functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host/plant functions 3318. In at least one embodiment, CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330. In at least one embodiment, CUDA to HIP translation tool 3320 translates each kernel call in CUDA source code 3310 from the CUDA syntax to the HIP syntax and any number of other CUDA calls in source code 3310 to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver 3340 then determines that target device 3346 is not CUDA enabled and generates HIP/HCC compiled command 3344. In at least one embodiment, HIP compiler driver 3340 then configures HCC 3360 to execute HIP/HCC compile commands 3344 to compile HIP source code 3330. In at least one embodiment, HIP/HCC compilation command 3344 configures HCC 3360 to generate host executable code 3370(2) and HCC device executable code 3382 using, but not limited to, HIP/HCC runtime library 3358 and HCC header 3356. In at least one embodiment, the HIP/HCC runtime library 3358 corresponds to the HIP runtime API 3332. In at least one embodiment, HCC head 3356 includes, but is not limited to, any number and type of interoperability mechanisms for HIPs and HCCs. In at least one embodiment, the host executable code 3370(2) and the HCC device executable code 3382 may execute on a CPU 3390 and a GPU 3392, respectively.

FIG. 34 illustrates an exemplary kernel converted by the CUDA to HIP conversion tool 3320 of FIG. 33C in accordance with at least one embodiment. In at least one embodiment, the CUDA source code 3310 divides the overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads. In at least one embodiment, each sub-problem is divided into relatively thin parts (pieces) that can be solved in parallel by the cooperation of threads in the thread block. In at least one embodiment, the threads within a thread block may cooperate by sharing memory sharing data and by executing synchronously to coordinate memory accesses.

In at least one embodiment, CUDA source code 3310 organizes the thread blocks associated with a given kernel into a one-, two-, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

In at least one embodiment, the kernel is a function in device code defined using the "__ global __" declarative specifier (specifier). In at least one embodiment, the CUDA kernel launch syntax 3410 is used to specify the size of the grid and associated flows for a given kernel call execution kernel. In at least one embodiment, the CUDA kernel launch syntax 3410 is designated as "KernelName < < GridSize, blockasize, SharedMemorySize, Stream > (kernelaugments); ". In at least one embodiment, the execution configuration grammar is a "< < > > >" construct that is inserted between the kernel name ("KernelName") and the parenthesis list of kernel parameters ("kernelarms"). In at least one embodiment, the CUDA kernel start syntax 3410 includes, but is not limited to, the CUDA start function syntax instead of the execute configuration syntax.

In at least one embodiment, "GridSize" is of the dim3 type and specifies the size and dimensions of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of gridsize.x, gridsize.y, and gridsize.z. In at least one embodiment, "BlockSize" is of the dim3 type and specifies the size and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of blocksize.x, blocksize.y, and blocksize.z. In at least one embodiment, given a unique thread ID for each thread of the execution core, the thread ID may be accessible within the core through a built-in variable (e.g., "threadIdx").

In at least one embodiment, with respect to the CUDA kernel start syntax 3410, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to the CUDA kernel launch syntax 3410, SharedMemorySize defaults to zero. In at least one embodiment and with respect to the CUDA kernel startup syntax 3410, a "flow" is an optional parameter that specifies an associated flow and defaults to zero to specify a default flow. In at least one embodiment, the stream is a sequence of commands (which may be issued by different host threads) that are executed in sequence. In at least one embodiment, different streams may execute commands out of order or simultaneously with respect to each other.

In at least one embodiment, the CUDA source code 3310 includes, but is not limited to, a kernel definition and a master function for the exemplary kernel "MatAdd". In at least one embodiment, the primary function is host code executing on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, as shown, kernel MatAdd adds two matrices a and B of size NxN, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the master function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N/16x N/16. In at least one embodiment, the master function then specifies a kernel call "MatAdd < < < numBlocks >, threeadsPerBlock > (A, B, C); ". In at least one embodiment, and in accordance with CUDA kernel startup syntax 3410, kernel MatAdd is executed using a grid of thread blocks of size N/16 × N/16, where each thread block is of size 16 × 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes the kernel MatAdd to perform a pair-by-pair addition.

In at least one embodiment, concurrently with converting CUDA source code 3310 to HIP source code 3330, CUDA-to-HIP conversion tool 3320 converts each kernel call in CUDA source code 3310 from CUDA kernel start syntax 3410 to HIP kernel start syntax 3420 and converts any number of other CUDA calls in source code 3310 to any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel launch syntax 3420 is designated as "hipLaunchKernelgGL (KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments); ". In at least one embodiment, each of KernelName, GridSize, blockasize, ShareMemorySize, Stream, and kernelaugments has the same meaning in HIP kernel start syntax 3420 as in CUDA kernel start syntax 3410 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in HIP kernel start syntax 3420 and are optional in CUDA kernel start syntax 3410.

In at least one embodiment, the portion of HIP source code 3330 depicted in FIG. 34 is the same as the portion of CUDA source code 3310 depicted in FIG. 34, except for kernel calls that cause the kernel MatAdd to execute on the device. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 3330 with the same "__ global __" declaration specifier as the kernel MatAdd is defined in the CUDA source code 3310. In at least one embodiment, the kernel call in HIP source code 3330 is "hipLaunchKernelgGL (MatAdd, numBlocks, thredesPerBlock, 0, A, B, C); ", and the corresponding kernel call in the CUDA source code 3310 is" MatAdd < < < numBlocks, threadsPerBlock > > (A, B, C); ".

Fig. 35 illustrates CUDA-not-enabled GPU 3392 of fig. 33C in more detail in accordance with at least one embodiment. In at least one embodiment, the GPU 3392 is developed by AMD corporation of Santa Clara. In at least one embodiment, GPU 3392 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, GPU 3392 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, GPU 3392 is configured to perform graphics-independent operations. In at least one embodiment, GPU 3392 is configured to perform both graphics-related and non-graphics-related operations. In at least one embodiment, GPU 3392 can be configured to execute device code included in HIP source code 3330.

In at least one embodiment, GPUs 3392 include, but are not limited to, any number of programmable processing units 3520, command processors 3510, L2 cache 3522, memory controller 3570, DMA engine 3580(1), system memory controller 3582, DMA engine 3580(2), and GPU controller 3584. In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, a workload manager 3530 and any number of computing units 3540. In at least one embodiment, the command handler 3510 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3530. In at least one embodiment, for each programmable processing unit 3520, the associated workload manager 3530 distributes the work to the compute units 3540 included in the programmable processing units 3520. In at least one embodiment, each compute unit 3540 may execute any number of thread blocks, but each thread block executes on a single compute unit 3540. In at least one embodiment, the workgroup is a thread block.

In at least one embodiment, each compute unit 3540 includes, but is not limited to, any number of SIMD units 3550 and shared memory 3560. In at least one embodiment, each SIMD unit 3550 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3550 includes, but is not limited to, a vector ALU 3552 and a vector register file 3554. In at least one embodiment, each SIMD unit 3550 executes a different thread bundle. In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), where each thread in the thread bundle belongs to a single thread block and is configured to process different sets of data based on a single set of instructions. In at least one embodiment, prediction can be used to disable one or more threads in a bundle of threads. In at least one embodiment, the channel is a thread. In at least one embodiment, the work items are threads. In at least one embodiment, the wavefront is a thread bundle. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicated via the shared memory 3560.

In at least one embodiment, programmable processing unit 3520 is referred to as a "shading engine". In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, any number of dedicated graphics hardware in addition to the computational unit 3540. In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render backend, a workload manager 3530, and any number of compute units 3540.

In at least one embodiment, the compute units 3540 share the L2 cache 3522. In at least one embodiment, the L2 cache 3522 is partitioned. In at least one embodiment, all compute units 3540 in GPU 3392 may access GPU memory 3590. In at least one embodiment, memory controller 3570 and system memory controller 3582 facilitate data transfers between GPU 3392 and a host, and DMA engine 3580(1) enables asynchronous memory transfers between GPU 3392 and this host. In at least one embodiment, memory controller 3570 and GPU controller 3584 facilitate data transfer between GPU 3392 and other GPUs 3392, and DMA engine 3580(2) enables asynchronous memory transfer between GPU 3392 and other GPUs 3392.

In at least one embodiment, GPU 3392 includes, but is not limited to, any number and type of system interconnections that facilitate data and control transfers between any number and type of directly or indirectly linked components internal or external to GPU 3392. In at least one embodiment, GPU 3392 includes, but is not limited to, any number and type of I/O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPUs 3392 may include, but are not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3392 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3570 and system memory controller 3582) and memory devices dedicated to one component or shared among multiple components (e.g., shared memory 3560). In at least one embodiment, GPU 3392 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3522), each of which may be private or shared among any number of components (e.g., SIMD unit 3550, compute unit 3540, and programmable processing unit 3520).

FIG. 36 illustrates how threads of an exemplary CUDA grid 3620 are mapped to different compute units 3540 of FIG. 35 in accordance with at least one embodiment. In at least one embodiment, and for purposes of illustration only, grid 3620 has GridSize that BX times BY times 1 and BlockSize that TX times TY times 1. Thus, in at least one embodiment, the grid 3620 includes, but is not limited to, (BX BY) thread blocks 3630, each thread block 3630 including, but not limited to, (TX TY) threads 3640. Thread 3640 is depicted in FIG. 36 as a curved arrow.

In at least one embodiment, grid 3620 is mapped to programmable processing units 3520(1), the programmable processing units 3520(1) including, but not limited to, computational units 3540(1) - (3540 (C). In at least one embodiment and as shown, (BJ BY) thread blocks 3630 are mapped to compute units 3540(1) and remaining thread blocks 3630 are mapped to compute units 3540 (2). In at least one embodiment, each thread block 3630 can include, but is not limited to, any number of thread bundles, and each thread bundle is mapped to a different SIMD cell 3550 of fig. 35.

In at least one embodiment, the thread bundles in a given thread block 3630 can be synchronized together and communicate through a shared memory 3560 included in an associated computing unit 3540. For example and in at least one embodiment, the thread bundles in thread block 3630(BJ, 1) can be synchronized together and communicate through shared memory 3560 (1). For example and in at least one embodiment, the thread bundles in thread block 3630(BJ +1, 1) can be synchronized together and communicate through shared memory 3560 (2).

Other variations are within the spirit of the present disclosure. Accordingly, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (meaning "including, but not limited to,") unless otherwise noted. The term "connected" (where unmodified it refers to a physical connection) is to be construed as partially or fully contained, attached, or connected together, even if there is some intervening. Unless otherwise indicated herein, references to ranges of values herein are intended merely to serve as shorthand methods of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated or contradicted by context, use of the term "set" (e.g., "set of items") or "subset" should be interpreted as including a non-empty set of one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a respective set does not necessarily denote an appropriate subset of the corresponding set, but rather the subset and the corresponding set may be equal.

Unless explicitly stated otherwise or clearly contradicted by context, conjunctions such as phrases in the form of "at least one of a, B, and C" or "at least one of a, B, and C" are understood in context to be used generically to refer to items, clauses, etc., which may be a or B or C, or any non-empty subset of the set of a and B and C. For example, in an illustrative example of a set having three members, the conjunctive phrases "at least one of a, B, and C" and "at least one of a, B, and C" refer to any of the following sets: { a }, { B }, { C }, { a, B }, { a, C }, { B, C }, { a, B, C }. Thus, such conjunctive language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, the term "plurality" means the state of a plurality (e.g., "a plurality of items" means a plurality of items) unless otherwise stated or contradicted by context. The number of items in the plurality of items is at least two, but may be more if indicated explicitly or by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based only on".

The operations of processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, processes such as those described herein (or variations and/or combinations thereof) are performed under control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that is executed collectively by hardware or combinations thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., propagating transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) that, when executed by one or more processors of a computer system (i.e., as a result of being executed), cause the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory computer-readable storage media of the plurality lack all of the code, but the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors, e.g., a non-transitory computer-readable storage medium stores instructions and a main central processing unit ("CPU") executes some instructions while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer system is configured with suitable hardware and/or software that enables the operations to be performed. Further, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate differently, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all of the operations.

The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Unless specifically stated otherwise, it may be appreciated that throughout the description, terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (e.g., electronic) within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.

In a similar manner, the term "processor" may refer to any device or portion of memory that processes electronic data from registers and/or memory and converts that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, a "processor" may be a CPU or GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to a plurality of processes to execute instructions sequentially or in parallel continuously or intermittently. The terms "system" and "method" may be used interchangeably herein, as long as the system may embody one or more methods, and the methods may be considered a system.

In this document, reference may be made to obtaining, receiving, or entering analog or digital data into a subsystem, computer system, or computer-implemented machine. The process of obtaining, receiving or inputting analog and digital data may be accomplished in a number of ways, such as by receiving the data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data from the providing entity to the acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transferring, sending, or rendering analog or digital data may be accomplished by transferring the data as input or output parameters of a function call, parameters of an application programming interface, or an interprocess communication mechanism.

While the above discussion sets forth example implementations of the described techniques, other architectures can be used to implement the described functionality, and are intended to fall within the scope of the present disclosure. Further, although a particular allocation of responsibilities is defined above for purposes of discussion, the various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the claimed subject matter may not necessarily be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.