阅读说明：本技术 一种可重构硬件任务动态布局方法 (Reconfigurable hardware task dynamic layout method ) 是由 程胜 赵新鹏 蔡铭 邱化强 崔小磊 于 2020-07-27 设计创作，主要内容包括：本发明公开的可重构硬件任务动态布局方法,涉及计算机技术领域,通过将新到达的硬件任务放置在己布局硬件任务的顶点处,通过对可重构芯片内部计算单元进行编码,可以迅速判断新任务是否可放置在该顶点。顶点除了包括硬件任务的顶点外,还包括硬件任务外延到x、y轴的顶点,如果硬件任务无法放置,可以通过旋转该硬件任务再进行判断,提高了可重构芯片空间的利用率,有效地减少了布局开销,提高了布局速度。(The invention discloses a dynamic layout method of a reconfigurable hardware task, which relates to the technical field of computers. The vertex comprises the vertex of the hardware task and also comprises the vertex of the hardware task extending to the x axis and the y axis, if the hardware task can not be placed, the judgment can be carried out by rotating the hardware task, the utilization rate of the reconfigurable chip space is improved, the layout expense is effectively reduced, and the layout speed is improved.)

1. A method for dynamically laying out reconfigurable hardware tasks is characterized by comprising the following steps:

s1, for a reconfigurable chip with H multiplied by W reconfigurable logic units, establishing a two-dimensional weight matrix M [ H, W ], wherein each element of the matrix M [ H, W ], namely a reconfigurable logic unit, has a value of a binary group { H, W }, H and W respectively represent the column number and the row number counted from the lower left foot of the reconfigurable logic unit, and H or W is an integer;

s2 creating record list C, saving vertex V (h) of current running hardware task₁，w₁) The initial state of the record table C comprises 1 vertex (0, 0) of the reconfigurable chip, wherein only the coordinates of the lower right corner of the running hardware task and the projection points of the layout area on the x axis and the y axis are stored in the record table C, the information in the record table C is sorted according to the ascending order of the distance between the vertex of the hardware task and the origin, and h is₁Indicates that the vertex V is located above the coordinate by h₁Available in a single unit, w₁Indicating that the vertex V is located at the right side of the coordinate with w₁A unit is available;

s3 hardware task T (h)₂，w₂) When the vertex V (h, w) in the record table C is reached, the vertex V (h, w) is extracted and matched with the vertex V (h, w) in the record table C in sequence, and the matching process is as follows:

if h₁Not less than h₂And w₁Not less than w₂If the vertex is the lower left vertex of the hardware task and there is enough space for laying out the hardware task, the matching is successful, and the process goes to step S4;

searching next vertex information in the record table C for continuous matching, and if the matching is successful, turning to the step S4; if not, turning to step S3, extracting the next vertex in the record table C and repeating the above matching process until the end of the record table C;

s4 accepts hardware task T (h)₂，w₂) Triggering hardware task T (h) at the right moment₂，w₂) Updating the information of the projection point and the hardware task vertex in the record table C according to the rule of the record table and finishing all the steps;

s5 determining that the current chip can not allocate enough space for the hardware task, and sending the hardware task T (h)₂，w₂) Put into wait queue or reject hardware task T (h)₂，w₂) And all steps are ended.

2. The reconfigurable hardware task dynamic layout method of claim 1, further comprising:

and after the execution of one hardware task is finished, recovering the space occupied by the hardware task, updating the information of the projection point and the hardware task in the record table C according to the rule of the record table, and recovering redundant record table space.

3. The method according to claim 1, wherein the step of extracting the next vertex in the record table C and repeating the matching process until the end of the record table C comprises:

if the end of the record C has been searched, the matching is not obtained yet and the hardware task T (h) is not rotated₂，w₂) Then rotate hardware task T (h)₂，w₂) Forming a rotating hardware task T' (w)₂，h₂) And hardware task matching is carried out again.

4. The method according to claim 3, wherein the step of extracting the next vertex in the record table C and repeating the matching process until the end of the record table C further comprises:

if the hardware task T (h) is already processed₂，w₂) When the rotation operation is performed, the hardware task T (h) is described₂，w₂) After the rotation, the layout cannot be completed, and the matching fails, the process goes to step S5.

Technical Field

The invention relates to the technical field of computers, in particular to a reconfigurable hardware task dynamic layout method.

Background

In a computing platform, each reconfigurable hardware task occupies corresponding resources on a reconfigurable chip and requires occupied reconfigurable logic units to be continuous in space. These hardware tasks run in parallel on the reconfigurable resources. When the hardware tasks are distributed in an inappropriate manner, a large number of pieces that cannot be merged may result. When a new hardware task makes a space requirement, even if the remaining resources on the reconfigurable chip exceed the required amount, the request of the hardware task cannot be received because the spatial distribution is discontinuous. If such a situation occurs frequently, the performance of the reconfigurable system will be severely degraded. If the memory management policy is not good, the execution efficiency of the operating system is also reduced.

Managing idle resources and online distribution on a reconfigurable chip is one of core problems of a software-defined dynamic reconfigurable system, namely the layout problem of the reconfigurable system. The layout not only relates to the reasonable and effective utilization of the resources of the reconfigurable chip, but also is a basis for researching the relocation, the dispatching and the arrangement of the hardware modules on the reconfigurable chip, and the efficiency of the layout is the enabling technology of the reconfigurable system.

As a bottleneck of a dynamic reconfigurable system, the dynamic layout method of the reconfigurable hardware task needs to increase the utilization rate of the reconfigurable chip as much as possible on the basis of ensuring the operation speed. In view of the prior art, most of the existing hardware layout methods have the problems of low layout quality, excessive layout method overhead and the like, and some methods have the limitations that hardware task reuse is not considered, a two-dimensional resource model is not supported, and excessive prerequisite information needs to be provided, so that the methods are difficult to apply in practice and are to be further optimized and promoted.

The existing dynamic layout method for reconfigurable hardware tasks mainly comprises the following schemes:

(1) non-overlapping free rectangle layout: when a hardware task is placed on the reconfigurable device, a certain vertex of the hardware task is coincided with the vertex of the free rectangle, and the rest free part is divided into non-overlapped rectangles. The dividing method is determined by different heuristic rules, and the common heuristic rules comprise the steps of selecting a shorter dividing line, selecting a longer dividing line and enabling the divided maximum rectangle to be closer to a square;

(2) based on the maximum free rectangular layout overlapping each other: and generating and maintaining all maximum idle matrix information on the reconfigurable chip, wherein the matrixes can be overlapped with each other. When a new hardware task arrives, searching for an idle matrix which is enough to accommodate the new hardware task. If the search is successful, placing the hardware task in the selected maximum idle matrix, and updating the remaining maximum idle matrix information;

(3) the layout method for keeping the vertex of the hardware task comprises the following steps: when a new hardware task reaches a reconfigurable system, trying to match the hardware task with each vertex in a reconfigurable chip, if the matching is successful, returning the vertex according to a binary backpack strategy, or continuing to match subsequent vertices in the chip to obtain a vertex with the lowest cost function; and if the matching fails, continuing to match the hardware task with the residual vertexes in the chip. These solutions have the following drawbacks:

(1) slow layout speed

The non-overlapping free rectangular layout and the maximum free rectangular layout based on mutual overlapping are searched for too many times when in use, resulting in slow layout speed.

(2) Large layout overhead

The existing layout method needs to introduce a complex structure to maintain the correlation between the idle matrixes, brings a large amount of layout overhead, and cannot be adopted in an actual reconfigurable system.

(3) Low chip utilization rate

The layout obtained in use has the problem of low quality, a lot of fragments which cannot be used can be generated, and a large amount of precious chip resources are wasted.

Disclosure of Invention

In order to solve the defects of the prior art, an embodiment of the present invention provides a method for dynamically laying out reconfigurable hardware tasks, including the following steps:

s1, for a reconfigurable chip with H multiplied by W reconfigurable logic units, establishing a two-dimensional weight matrix M [ H, W ], wherein each element of the matrix M [ H, W ], namely a reconfigurable logic unit, has a value of a binary group { H, W }, H and W respectively represent the column number and the row number counted from the lower left foot of the reconfigurable logic unit, and H or W is an integer;

s2 creating record C and storing itVertex V (h) of the hardware task in the front run₁，w₁) The initial state of the record table C comprises 1 vertex (0, 0) of the reconfigurable chip, only the coordinates of the lower right corner of the running hardware task and the projection points of the layout area on the x axis and the y axis are stored in the record table C, the information in the record table C is sorted according to the ascending order of the distance between the vertex of the hardware task and the origin, wherein h is₁Indicates that the vertex V is located above the coordinate by h₁Available in a single unit, w₁Indicating that the vertex V is located at the right side of the coordinate with w₁A unit is available;

s3 hardware task T (h)₂，w₂) When the vertex V (h, w) in the record table C is reached, the vertex V (h, w) is extracted and matched with the vertex V (h, w) in the record table C in sequence, and the matching process is as follows:

if h₁Not less than h₂And w₁Not less than w₂If the vertex is the lower left vertex of the hardware task and there is enough space for laying out the hardware task, the matching is successful, and the process goes to step S4;

searching next vertex information in the record table C for continuous matching, and if the matching is successful, turning to the step S4; if not, turning to step S3, extracting the next vertex in the record table C and repeating the above matching process until the end of the record table C;

s4 accepts hardware task T (h)₂，w₂) Triggering hardware task T (h) at the right moment₂，w₂) Updating the information of the projection point and the hardware task vertex in the record table C according to the rule of the record table and finishing all the steps;

s5 determining that the current chip can not allocate enough space for the hardware task, and sending the hardware task T (h)₂，w₂) Put into wait queue or reject hardware task T (h)₂，w₂) And all steps are ended.

Preferably, the method further comprises:

and after the execution of one hardware task is finished, recovering the space occupied by the hardware task, updating the information of the projection point and the hardware task in the record table C according to the rule of the record table, and recovering redundant record table space.

Preferably, extracting the next vertex in the record table C and repeating the above matching process until the end of the record table C includes:

if the end of the record C has been searched, the matching is not obtained yet and the hardware task T (h) is not rotated₂，w₂) Then rotate hardware task T (h)₂，w₂) Forming a rotating hardware task T' (w)₂，h₂) And hardware task matching is carried out again.

Preferably, extracting the next vertex in the record table C and repeating the above matching process until the end of the record table C further includes:

if the hardware task T (h) is already processed₂，w₂) When the rotation operation is performed, the hardware task T (h) is described₂，w₂) After the rotation, the layout cannot be completed, and the matching fails, the process goes to step S5.

The dynamic layout method for the reconfigurable hardware task provided by the embodiment of the invention has the following beneficial effects:

(1) when the space required by the hardware task is large, the hardware task can be arranged along the X axis or the Y axis due to the rotation of the hardware task, so that the utilization rate of the reconfigurable chip is improved;

(2) the idle matrix information table maintained by the two-dimensional data can accurately reflect the distribution condition of the idle resources of the reconfigurable chip, so that the matching process is more efficient, the layout overhead is effectively reduced, and the layout speed is improved.

Drawings

FIGS. 1 a-1 c are schematic diagrams of three different configurations of the same hardware task according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a dynamic layout method for reconfigurable hardware tasks according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a two-dimensional weight matrix corresponding to a reconfigurable chip according to an embodiment of the present invention;

fig. 4 is a schematic diagram of vertex records corresponding to the two-dimensional weight matrix shown in fig. 3 according to an embodiment of the present invention.

Detailed Description

The invention is described in detail below with reference to the following figures and examples.

Noun interpretation

Hardware tasks: generally refers to a functional block, which may be configured into a reconfigurable device after synthesis, and is generally a rectangular block.

The reconfigurable chip comprises: is composed of a certain number of minimum reconfigurable logic units and the interconnection logic between them.

An idle rectangle: refers to a rectangular area on the reconfigurable chip that is not currently occupied by hardware tasks.

Fragmenting: refers to resources that cannot be utilized outside the boundary of a hardware task.

Minimum reconfigurable logic cell: the reconfigurable chip is the minimum unit of configuration of the reconfigurable chip, and when the circuit function is changed randomly, the reconfigurable system at least needs the minimum unit of configuration.

It is generally believed that the variability in the shape of the hardware tasks is a major cause of layout fragmentation. Past definitions of hardware tasks default to hardware tasks that cannot be rotated. With the development of the technology, a minimum reconfigurable logic unit and the minimum reconfigurable logic units at the upper, lower, left and right sides of the minimum reconfigurable logic unit are completely the same, and there is no difference in direction. Therefore, after two configuration files of the (1, 4) rectangular hardware task and the rotated (4, 1) rectangular hardware task can be generated by one (1, 4) rectangular hardware task, the layout can be carried out along two directions of the X axis or the Y axis, and the hardware structure is kept completely isomorphic. If a (1, 4) rectangular hardware task is to be converted into a (2, 2) square hardware task, a hardware wiring change within the hardware task is involved, and the change may be preset in the hardware task configuration database. When the hardware task shape needs to be changed, the corresponding configuration file is called from the database. If the shapes of the hardware tasks are converted into squares as much as possible, the hardware task layout algorithm is simplified.

Therefore, the shape of the hardware task does not affect the function of the hardware task, and the function of the hardware task is kept unchanged as long as the hardware task is composed of the same number of continuous minimum reconfigurable logic units. Fig. 1 a-1 c show three different configurations of the same hardware task. In order to form a rectangle, both fig. 1b and fig. 1c are supplemented with virtual cells, so-called tiles.

On the premise that the hardware task shape on the reconfigurable chip does not influence the hardware task function, the embodiment of the invention provides a method for finishing the dynamic layout of the reconfigurable hardware task by adjusting the task shape by generating the rotatable hardware task in advance and adapting the layout requirements in the X axis or the Y axis, as shown in FIG. 2, and the method comprises the following steps:

s101, establishing a two-dimensional weight matrix M [ H, W ] for a reconfigurable chip with H multiplied by W reconfigurable logic units, wherein each element of the matrix M [ H, W ] is a reconfigurable logic unit, the value of the matrix M [ H, W ] is a binary group { H, W }, H and W respectively represent the column number and the row number counted from the lower left foot of the reconfigurable logic unit, and H or W is an integer.

As a specific embodiment of the present invention, in the two-dimensional weight matrix shown in FIG. 3, there are three running tasks T1, T2 and T3, and the P point is the projection point of the laid out region on the x axis.

S102, establishing a record table C, and storing a vertex V (h) of the current running hardware task₁，w₁) The initial state of the record table C comprises 1 vertex (0, 0) of the reconfigurable chip, wherein only the coordinates of the lower right corner of the running hardware task and the projection points of the layout area on the x axis and the y axis are stored in the record table C, the information in the record table C is sorted according to the ascending order of the distance between the vertex of the hardware task and the origin, and h is₁Indicates that the vertex V is located above the coordinate by h₁Available in a single unit, w₁Indicating that the vertex V is located at the right side of the coordinate with w₁A single cell is available.

As a specific embodiment of the present invention, as shown in FIG. 4, the weight values of the lower right vertex and the vertex on the y-axis of the hardware task T2 are (0, 0), so it is not necessary to store them into the record table C. In addition, Px is the projected point of the layout area on the x-axis, and when the weight value of the vertex is (0, 0), a new hardware task cannot be placed at the vertex, and the vertex is deleted from the record table C.

S103, when the hardware task T (h)₂，w₂) When the vertex V (h, w) in the record table C is reached, the vertex V (h, w) is extracted and matched with the vertex V (h, w) in the record table C in sequence, and the matching process is as follows:

s1031 if h₁Not less than h₂And w₁Not less than w₂If the vertex is taken as the lower left vertex of the hardware task and there is enough space for laying out the hardware task, the matching is successful, and the process goes to step S104;

s1032, searching the next vertex information in the record table C for continuous matching, and if the matching is successful, turning to the step S104; if not, turning to step S103, extracting the next vertex in the record table C and repeating the matching process until the end of the record table C;

s104, receiving the hardware task T (h)₂，w₂) Triggering hardware task T (h) at the right moment₂，w₂) Updating the information of the projection point and the hardware task vertex in the record table C according to the rule of the record table and finishing all the steps;

s105, determining that the current chip can not allocate enough space for the hardware task, and executing the hardware task T (h)₂，w₂) Put into wait queue or reject hardware task T (h)₂，w₂) And all steps are ended.

Optionally, the method further comprises:

and after the execution of one hardware task is finished, recovering the space occupied by the hardware task, updating the information of the projection point and the hardware task in the record table C according to the rule of the record table, and recovering redundant record table space.

Optionally, extracting a next vertex in the record table C and repeating the above matching process until the end of the record table C includes:

if the end of the record C has been searched, the matching is not obtained yet and the hardware task T (h) is not rotated₂，w₂) Then rotate hardware task T (h)₂，w₂) Forming a rotating hardware task T' (w)₂，h₂) And hardware task matching is carried out again.

Optionally, extracting a next vertex in the record table C and repeating the matching process until the end of the record table C further includes:

if the hardware task T (h) is already processed₂，w₂) When the rotation operation is performed, the hardware task T (h) is described₂，w₂) After the rotation, the layout cannot be completed, the matching fails, and the process goes to step S105.

According to the dynamic layout method for the reconfigurable hardware task, the newly arrived hardware task is placed at the vertex of the hardware task which is already laid out, and the internal computing unit of the reconfigurable chip is coded, so that whether the new task can be placed at the vertex or not can be quickly judged. The vertex comprises the vertex of the hardware task and also comprises the vertex of the hardware task extending to the x axis and the y axis, if the hardware task can not be placed, the judgment can be carried out by rotating the hardware task, the utilization rate of the reconfigurable chip space is improved, the layout expense is effectively reduced, and the layout speed is improved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It will be appreciated that the relevant features of the method and apparatus described above are referred to one another. In addition, "first", "second", and the like in the above embodiments are for distinguishing the embodiments, and do not represent merits of the embodiments.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.