Clock tree anti-interference method and device based on noise timing sequence
阅读说明：本技术 一种基于噪声时序的时钟树抗干扰方法及装置 (Clock tree anti-interference method and device based on noise timing sequence ) 是由 王锐 刘一杰 莫军 李建军 王亚波 于 2020-07-03 设计创作，主要内容包括：本发明公开了一种基于噪声时序的时钟树抗干扰方法及装置,抗干扰方法包括：抓取时钟树所有的扇出单元,并根据扇出单元抓取时钟树的延时弧；抓取所有延时弧中的最大延时；根据时钟树的工艺节点以及时钟频率设定预设检测标准；将最大延时与预设检测标准进行比对,根据比对结果对时钟树进行抗干扰处理。本发明实施例通过抓取时钟树所有的扇出单元,从而抓取出时钟树的延时弧,并抓取延时弧中的最大延时,根据时钟树的工艺节点以及时钟频率设定预设检测标准,能够全面且准确地检测得到时钟树是否存在噪声干扰,在检测到噪声干扰时,根据检测得到的结果对时钟树进行抗干扰处理,不仅能够提高时钟树的抗干扰性,还能够提高整体时钟延时的平衡性。(The invention discloses a clock tree anti-interference method and a device based on noise timing sequence, wherein the anti-interference method comprises the following steps: grabbing all fan-out units of the clock tree, and grabbing delay arcs of the clock tree according to the fan-out units; capturing the maximum delay in all delay arcs; setting a preset detection standard according to the process node of the clock tree and the clock frequency; and comparing the maximum delay with a preset detection standard, and performing anti-interference processing on the clock tree according to a comparison result. According to the embodiment of the invention, all fan-out units of the clock tree are grabbed, so that the delay arc of the clock tree is grabbed, the maximum delay in the delay arc is grabbed, the preset detection standard is set according to the process node and the clock frequency of the clock tree, whether noise interference exists in the clock tree can be comprehensively and accurately detected, and when the noise interference is detected, the anti-interference processing is carried out on the clock tree according to the detected result, so that the anti-interference performance of the clock tree can be improved, and the balance of the whole clock delay can be improved.)
1. A clock tree anti-interference method based on noise timing sequence is characterized by comprising the following steps:
grabbing all fan-out units of a clock tree, and grabbing delay arcs of the clock tree according to the fan-out units;
capturing the maximum delay in all the delay arcs;
setting a preset detection standard according to the process node of the clock tree and the clock frequency;
and comparing the maximum delay with the preset detection standard, and performing anti-interference processing on the clock tree according to a comparison result.
2. The clock tree anti-jamming method based on noise timing sequence according to claim 1, wherein the grabbing the delay arcs of the clock tree according to the fan-out unit specifically includes:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
3. The clock tree anti-interference method based on the noise timing sequence according to claim 1, wherein the preset detection criteria are set according to the process node and the clock frequency of the clock tree, specifically:
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
4. The clock tree anti-interference method based on the noise timing sequence according to claim 3, wherein the comparing the maximum delay time with the preset detection standard and performing anti-interference processing on the clock tree according to the comparison result specifically comprises:
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists in the clock tree connection line when the maximum delay exceeds the threshold condition;
when NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
when detecting that there is no NDR winding in the clock tree, adding the NDR winding in a placement and routing tool of the clock tree.
5. An anti-interference device of a clock tree based on a noise timing sequence is characterized by comprising:
the first grabbing unit is used for grabbing all fan-out units of the clock tree and grabbing the delay arcs of the clock tree according to the fan-out units;
the second grabbing unit is used for grabbing the maximum delay in all the delay arcs;
the setting unit is used for setting a preset detection standard according to the process node of the clock tree and the clock frequency;
and the anti-interference processing unit is used for comparing the maximum delay with the preset detection standard and carrying out anti-interference processing on the clock tree according to a comparison result.
6. The clock tree anti-jamming device based on noise timing sequence of claim 5, wherein the grabbing the delay arcs of the clock tree according to the fan-out units specifically comprises:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
7. The clock tree anti-jamming device based on noise timing sequence of claim 5, wherein the setting unit is specifically configured to:
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
8. The clock tree immunity device based on noise timing as claimed in claim 7, wherein the immunity processing unit is specifically configured to:
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists in the clock tree connection line when the maximum delay exceeds the threshold condition;
when NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
when detecting that there is no NDR winding in the clock tree, adding the NDR winding in a placement and routing tool of the clock tree.
Technical Field
The invention relates to the technical field of chip design, in particular to a clock tree anti-interference method and device based on noise timing sequence.
Background
At present, the integrated circuit is developed vigorously, and along with the higher and higher integration level of the chip, the chip area is larger and larger, and the time sequence convergence of the chip is more and more difficult. The establishment of a heavily stressed clock tree for timing convergence is also the subject of intensive research and development in the industry. Major electronic design automation tool vendors have developed many algorithms for clock trees to improve and upgrade the quality of the clock trees. But the setup requirements and implementation of clock trees are diverse in different process and chip application directions and are of great relevance to the thoughts and experiences of the engineers using the tools. After the clock tree is established, in order to reduce the difficulty and cost of clock tree timing convergence, the clock tree needs to be subjected to anti-interference processing.
The inventor of the present invention finds in research that, in the existing clock tree anti-interference method, when a timing sequence is checked, a difference value calculated by a common path of a clock on an OCV is recalculated and cancelled to eliminate an interference influence caused by a delay difference on the common path, but the difference caused by noise interference cannot be cancelled, so that the clock on the common path is easily influenced by interference, and the balance of the overall clock delay is poor.
Disclosure of Invention
The invention provides a clock tree anti-interference method and device based on noise timing sequence, and aims to solve the technical problem that in the prior art, a clock on a public path is easily influenced by interference, so that the balance of overall clock delay is poor.
The first embodiment of the present invention provides a clock tree anti-interference method based on a noise timing sequence, including:
grabbing all fan-out units of a clock tree, and grabbing delay arcs of the clock tree according to the fan-out units;
capturing the maximum delay in all the delay arcs;
setting a preset detection standard according to the process node of the clock tree and the clock frequency;
and comparing the maximum delay with the preset detection standard, and performing anti-interference processing on the clock tree according to a comparison result.
Further, the grabbing the delay arcs of the clock tree according to the fan-out unit specifically includes:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
Further, the setting of the preset detection standard according to the process node of the clock tree and the clock frequency specifically includes:
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
Further, the comparing the maximum delay with the preset detection standard, and performing anti-interference processing on the clock tree according to the comparison result specifically include:
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists in the clock tree connection line when the maximum delay exceeds the threshold condition;
when NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
when detecting that there is no NDR winding in the clock tree, adding the NDR winding in a placement and routing tool of the clock tree.
A second embodiment of the present invention provides a clock tree anti-interference apparatus based on a noise timing sequence, including:
the first grabbing unit is used for grabbing all fan-out units of the clock tree and grabbing the delay arcs of the clock tree according to the fan-out units;
the second grabbing unit is used for grabbing the maximum delay in all the delay arcs;
the setting unit is used for setting a preset detection standard according to the process node of the clock tree and the clock frequency;
and the anti-interference processing unit is used for comparing the maximum delay with the preset detection standard and carrying out anti-interference processing on the clock tree according to a comparison result.
Further, the grabbing the delay arcs of the clock tree according to the fan-out unit specifically includes:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
Further, the setting unit is specifically configured to:
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
Further, the anti-interference processing unit is specifically configured to:
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists in the clock tree connection line when the maximum delay exceeds the threshold condition;
when NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
when detecting that there is no NDR winding in the clock tree, adding the NDR winding in a placement and routing tool of the clock tree.
According to the embodiment of the invention, all fan-out units of the clock tree are grabbed, so that the delay arc of the clock tree is grabbed, the maximum delay in the delay arc is grabbed, the preset detection standard is set according to the process node and the clock frequency of the clock tree, whether noise interference exists in the clock tree can be comprehensively and accurately detected, and when the noise interference is detected, the anti-interference processing is carried out on the clock tree according to the detected result, so that the anti-interference performance of the clock tree can be improved, and the balance of the whole clock delay can be improved.
Drawings
Fig. 1 is a schematic flowchart of a clock tree anti-interference method based on a noise timing sequence according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a general winding of a clock tree according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of NDR routing of a clock tree according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an NDR routing isolation layer of a clock tree according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a clock tree interference rejection apparatus based on a noise timing sequence according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, a first embodiment of the present invention is shown in fig. 1, which illustrates a clock tree interference rejection method based on noise timing, including:
s1, grabbing all fan-out units of the clock tree, and grabbing the delay arcs of the clock tree according to the fan-out units, specifically:
set CELLS[get_clock_network_objects$CLOCKS-include-type cell]。
in the embodiment of the present invention, in a static timing analysis environment, all fan-out units of a clock tree are captured, and a PrimeTime tool command is used to capture relevant connection lines of the fan-out units, specifically:
set NETS[get_clock_network_objects$CLOCKS-include-type net]。
s2, capturing the maximum delay in all delay arcs;
specifically, a PrimeTime tool command is used to continuously capture the relevant connecting line to obtain four relevant delay arcs (timing arc) on the connecting line. The method specifically comprises the following steps:
set net_arc[get_timing_arcs-of_objects$net]
set delta_maxr[get_attribute$net_arc"annotated_delay_delta_max_rise"]
set delta_maxf[get_attribute$net_arc"annotated_delay_delta_max_fall"]
set delta_minr[get_attribute$net_arc"annotated_delay_delta_min_rise"]
set delta_minf[get_attribute$net_arc"annotated_delay_delta_min_fall"]。
maximum delay:
max_delta＝max($delta_maxr,$delta_maxf,$delta_minr,$delta_minf)。
s3, setting a preset detection standard according to the process node of the clock tree and the clock frequency;
in the embodiment of the present invention, it should be noted that the clock trees of different process nodes have different standards for detecting whether the clock trees have noise delays. The embodiment of the invention sets different detection standards according to different process nodes of the clock tree, and is favorable for improving the detection accuracy of the clock tree delay noise, thereby being favorable for improving the anti-interference efficiency of the clock tree. In order to further improve the efficiency of interference resistance, the embodiment of the invention divides the clock path into a conventional path and a critical path according to the clock frequency, and each path corresponds to different threshold conditions.
And S4, comparing the maximum delay with a preset detection standard, and performing anti-interference processing on the clock tree according to the comparison result.
According to the embodiment of the invention, all fan-out units of the clock tree are grabbed, so that the delay arc of the clock tree is grabbed, the maximum delay in the delay arc is grabbed, the preset detection standard is set according to the process node and the clock frequency of the clock tree, whether noise interference exists in the clock tree can be comprehensively and accurately detected, and when the noise interference is detected, the anti-interference processing is carried out on the clock tree according to the detected result, so that the anti-interference performance of the clock tree can be improved, and the balance of the whole clock delay can be improved.
As a specific implementation manner of the embodiment of the present invention, capturing a delay arc of a clock tree according to a fan-out unit specifically includes:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
It will be appreciated that analyzing or verifying the timing aspects of a circuit design includes primarily dynamic and static timing simulation analysis. PrimeTime (PT) is a static timing analysis tool for sign-off quality (sign-off) of Synopsys, Inc. According to the embodiment of the invention, the PrimeTime tool command is used for grabbing the delay arcs according to the fan-out unit, all possible paths are checked, and the delay arcs of the fan-out unit can be quickly and accurately grabbed.
As a specific implementation manner of the embodiment of the present invention, the setting of the preset detection standard according to the process node of the clock tree and the clock frequency specifically includes:
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
As a specific implementation manner of the embodiment of the present invention, a clock path with a clock frequency less than 1GHz is divided into a conventional path, a clock path with a clock frequency greater than or equal to 1GHz is divided into a critical path, and a preset detection standard shown in table 1 below is obtained by combining process nodes of a clock tree:
TABLE 1 Preset test standards
Referring to table 1, when a high frequency clock exists in the chip set, i.e. a clock with a clock frequency of 1.2GHz, the threshold of the threshold condition is lower in the same process node than the threshold in the clock frequency environment of the conventional path <1 GHz. According to the embodiment of the invention, the clock tree which is missed to be subjected to NDR (non Default rule) winding processing can be detected in the layout and wiring tool, the clock tree defect which influences the timing sequence convergence of the chip when the clock tree is seriously interfered can also be detected, and the whole quality of the chip can be improved. Alternatively, clock trees for 0.18um and above processes do not check for noise interference.
According to the method and the device, the preset detection standard is set according to the process node and the clock frequency of the clock tree, the maximum delay of the clock to be detected is compared with the corresponding threshold condition in the preset detection standard, the detection result is obtained, and the comprehensiveness and accuracy of interference detection can be improved. Specifically, if the maximum delay is greater than the threshold condition, detecting that the clock tree to be monitored has noise delay, and obtaining the conclusion that the clock tree to be monitored has noise interference.
As a specific implementation manner of the embodiment of the present invention, the maximum delay is compared with a preset detection standard, and the anti-interference processing is performed on the clock tree according to a comparison result, specifically:
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists on a clock tree connecting line when the maximum delay exceeds the threshold condition;
in the embodiment of the present invention, when the maximum delay exceeds the threshold condition, that is, when the interference of noise delay in the clock tree is detected, whether an NDR winding exists in the clock tree connection is detected by the layout and routing tool, and when the NDR winding exists in the clock tree connection, it is described that the reason for causing the interference of delay in the clock tree is not that the NDR winding is lacked, but that the clock tree is interfered by the peripheral noise. The embodiment of the invention can accurately and comprehensively detect the reason causing the clock tree noise delay interference so as to perform anti-interference processing on the clock tree according to the detection result and improve the anti-interference performance of the clock tree.
When NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
in the embodiment of the invention, when NDR winding is detected to exist in the clock tree connection line, the isolation layers are respectively arranged on the two sides of the clock wiring line to isolate the influence of noise around the clock tree, so that the anti-interference performance of the clock tree is improved.
When the clock tree is detected to have no NDR winding, the NDR winding is added in a layout and wiring tool of the clock tree, so that the crosstalk between lines can be effectively avoided.
Referring to fig. 2, a diagram of a common winding of a clock tree according to the present embodiment is shown, wherein two clock windings 1 are respectively disposed on two sides of a clock winding 1 at a certain distance. In the embodiment of the invention, when the clock tree is detected to have no NDR winding, the NDR winding is added in a layout and wiring tool of the clock tree so as to improve the anti-interference performance of the clock tree. Referring to fig. 3, a schematic diagram of NDR routing of a clock tree according to an embodiment of the present invention is shown, where the NDR routing is performed in the following manner: the clock winding 1 is 2 times as wide as the clock winding 1 in the normal winding, and the distance between the interference signal winding 2 and the clock winding 1 is 2 times as long as the distance in the normal winding. As a specific implementation manner of the embodiment of the present invention, after the NDR routing is added, if the maximum delay of the clock tree still exceeds the corresponding threshold condition, isolation layers are respectively disposed on two sides of the clock routing, so as to further improve the anti-interference performance of the clock tree. Referring to fig. 4, a schematic diagram of an arrangement of an NDR routing isolation layer of a clock tree according to an embodiment of the present invention is shown, where the isolation layer includes, but is not limited to, an isolation layer ground routing 3, where the isolation layer ground routing 3 is disposed between a clock routing 1 and an
The embodiment of the invention has the following beneficial effects:
the method comprises the steps of adding an NDR winding in a clock tree wiring tool and arranging isolation layers on two sides of a clock wiring respectively, so that the influence of noise in a clock can be effectively reduced, the anti-interference performance of the clock tree can be improved, and the balance of the whole clock delay can be improved.
Referring to fig. 5, a clock tree interference rejection apparatus based on noise timing sequence according to a second embodiment of the present invention is shown in fig. 5, which includes:
the first grabbing
set CELLS[get_clock_network_objects$CLOCKS-include-type cell]。
in the embodiment of the invention, in the static timing analysis environment, all fan-out units of a clock tree are captured, and the related connecting lines of the fan-out units are captured by using a PrimeTime tool command. The method specifically comprises the following steps:
set NETS[get_clock_network_objects$CLOCKS-include-type net]。
a second grasping
specifically, a PrimeTime tool command is used to continuously capture the relevant connecting line to obtain four relevant delay arcs (timing arc) on the connecting line. The method specifically comprises the following steps:
set net_arc[get_timing_arcs-of_objects$net]
set delta_maxr[get_attribute$net_arc"annotated_delay_delta_max_rise"]
set delta_maxf[get_attribute$net_arc"annotated_delay_delta_max_fall"]
set delta_minr[get_attribute$net_arc"annotated_delay_delta_min_rise"]
set delta_minf[get_attribute$net_arc"annotated_delay_delta_min_fall"]
maximum delay:
max_delta＝max($delta_maxr,$delta_maxf,$delta_minr,$delta_minf)。
the
in the embodiment of the present invention, it should be noted that the clock trees of different process nodes have different standards for detecting whether the clock trees have noise delays. The embodiment of the invention sets different detection standards according to different process nodes of the clock tree, and is favorable for improving the detection accuracy of the clock tree delay noise, thereby being favorable for improving the anti-interference efficiency of the clock tree. In order to further improve the efficiency of interference resistance, the embodiment of the invention divides the clock path into a conventional path and a critical path according to the clock frequency, and each path corresponds to different threshold conditions.
And the
According to the embodiment of the invention, all fan-out units of the clock tree are grabbed, so that the delay arcs of the clock tree are grabbed, the maximum delay in the delay arcs is grabbed, the preset detection standard is set according to the process nodes and the clock frequency of the clock tree, whether noise interference exists in the clock tree can be comprehensively and accurately detected, when the noise interference is detected, the clock tree is subjected to anti-interference processing according to the detected result, and the anti-interference performance of the clock tree is improved.
As a specific implementation manner of the embodiment of the present invention, capturing a delay arc of a clock tree according to a fan-out unit specifically includes:
and grabbing the delay arcs according to the fan-out unit according to a PrimeTime tool command.
It will be appreciated that analyzing or verifying the timing aspects of a circuit design includes primarily dynamic and static timing simulation analysis. PrimeTime (PT) is a static timing analysis tool for sign-off quality (sign-off) of Synopsys, Inc. According to the embodiment of the invention, the PrimeTime tool command is used for grabbing the delay arcs according to the fan-out unit, all possible paths are checked, and the delay arcs of the fan-out unit can be quickly and accurately grabbed.
As a specific implementation manner of the embodiment of the present invention, the setting
dividing a clock path into a conventional path and a critical path according to the clock frequency of a clock tree;
and setting threshold conditions corresponding to the plurality of process nodes respectively according to the process nodes of the clock tree, wherein the threshold conditions comprise a conventional path threshold and a critical path threshold.
As a specific implementation manner of the embodiment of the present invention, a clock path with a clock frequency less than 1GHz is divided into a conventional path, a clock path with a clock frequency greater than or equal to 1GHz is divided into a critical path, and a preset detection standard shown in table 1 below is obtained by combining process nodes of a clock tree:
TABLE 1 Preset test standards
Referring to table 1, when a high frequency clock exists in the chip set, i.e. a clock with a clock frequency of 1.2GHz, the threshold of the threshold condition is lower in the same process node than the threshold in the clock frequency environment of the conventional path <1 GHz. According to the embodiment of the invention, the clock tree which is missed to be subjected to NDR winding processing can be detected in the layout wiring tool, the clock tree defect that the clock tree influences the timing sequence convergence of the chip when the clock tree is seriously interfered can also be detected, and the integral quality of the chip can be improved. Alternatively, clock trees for 0.18um and above processes do not check for noise interference.
According to the method and the device, the preset detection standard is set according to the process node and the clock frequency of the clock tree, the maximum delay of the clock to be detected is compared with the corresponding threshold condition in the preset detection standard, the detection result is obtained, and the comprehensiveness and accuracy of interference detection can be improved. Specifically, if the maximum delay is greater than the threshold condition, detecting that the clock tree to be monitored has noise delay, and obtaining the conclusion that the clock tree to be monitored has noise interference.
As a specific implementation manner of the embodiment of the present invention, the
comparing the maximum delay with a threshold condition corresponding to the process node according to the process node of the clock tree to be detected, and detecting whether an NDR winding exists on a clock tree connecting line when the maximum delay exceeds the threshold condition;
in the embodiment of the present invention, when the maximum delay exceeds the threshold condition, that is, when the interference of noise delay in the clock tree is detected, whether an NDR winding exists in the clock tree connection is detected by the layout and routing tool, and when the NDR winding exists in the clock tree connection, it is described that the reason for causing the interference of delay in the clock tree is not that the NDR winding is lacked, but that the clock tree is interfered by the peripheral noise. The embodiment of the invention can accurately and comprehensively detect the reason causing the clock tree noise delay interference so as to perform anti-interference processing on the clock tree according to the detection result and improve the anti-interference performance of the clock tree.
When NDR winding of the clock tree connecting line is detected, isolating layers are respectively arranged on two sides of the clock wiring;
in the embodiment of the invention, when NDR winding is detected to exist in the clock tree connection line, the isolation layers are respectively arranged on the two sides of the clock wiring line to isolate the influence of noise around the clock tree, so that the anti-interference performance of the clock tree is improved.
When the clock tree is detected to have no NDR winding, the NDR winding is added in a layout and wiring tool of the clock tree, so that the crosstalk between lines can be effectively avoided.
Referring to fig. 2, a diagram of a common winding of a clock tree according to an embodiment of the present invention is shown, wherein two clock windings 1 are respectively disposed on two sides of a clock winding 1 at a certain distance. In the embodiment of the invention, when the clock tree is detected to have no NDR winding, the NDR winding is added in a layout and wiring tool of the clock tree so as to improve the anti-interference performance of the clock tree. Referring to fig. 3, a schematic diagram of NDR routing of a clock tree according to an embodiment of the present invention is shown, where the NDR routing is performed in the following manner: the clock winding 1 is 2 times as wide as the clock winding 1 in the normal winding, and the distance between the interference signal winding 2 and the clock winding 1 is 2 times as long as the distance in the normal winding. As a specific implementation manner of the embodiment of the present invention, after the NDR routing is added, if the maximum delay of the clock tree still exceeds the corresponding threshold condition, isolation layers are respectively disposed on two sides of the clock routing, so as to further improve the anti-interference performance of the clock tree. Referring to fig. 4, a schematic diagram of an arrangement of an NDR routing isolation layer of a clock tree according to an embodiment of the present invention is shown, where the isolation layer includes, but is not limited to, an isolation layer ground routing 3, where the isolation layer ground routing 3 is disposed between a clock routing 1 and an
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention sets the preset detection standard according to the process node and the clock frequency of the clock tree, compares the maximum time delay obtained by grabbing with the preset detection standard, judges whether the clock tree is interfered by noise according to the comparison result, and performs anti-interference processing when the clock tree is interfered by the noise.
The foregoing is a preferred embodiment of the present invention, and it should be noted that it would be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the principles of the invention, and such modifications and enhancements are also considered to be within the scope of the invention.
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